cvw/pipelined/src
2022-06-21 20:30:33 +00:00
..
cache Removing unused signals 2022-05-12 14:36:15 +00:00
ebu Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals 2022-06-10 20:43:56 -07:00
fpu postprocess out of fpu critical path 2022-06-15 22:58:33 +00:00
generic Cleaned bram interface 2022-06-08 01:39:44 +00:00
hazard added #1 delays to Stalls and Flushes in hazard unit 2022-06-08 16:28:09 +00:00
ieu switched comparator to dc flip version 2022-06-21 20:30:33 +00:00
ifu Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors 2022-06-08 15:03:15 -07:00
lsu Added more comments 2022-06-13 12:26:08 -07:00
mmu Clean up unused signals 2022-05-12 14:49:58 +00:00
muldiv Clean up unused signals 2022-05-12 14:49:58 +00:00
ppa cleanup, plots for paper 2022-06-15 18:28:36 +00:00
privileged Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
uncore Cleanup on RAM module 2022-06-13 19:37:43 +00:00
wally postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00