Ross Thompson 8a6ca027c2 The valid and dirty bits match the SRAM implementation now.		2022-09-22 16:09:09 -05:00
..
cache	The valid and dirty bits match the SRAM implementation now.	2022-09-22 16:09:09 -05:00
ebu	Fixed up IFU ahb interface names and widths.	2022-09-19 10:54:22 -05:00
fpu	For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc	2022-09-21 13:30:35 -07:00
generic	Solved the sram write first / read first issue. Works correctly with read first now.	2022-09-22 14:16:26 -05:00
hazard	Added comments about planned changes.	2022-08-29 09:48:00 -05:00
ieu	Eliminated store after store stall when no cache; simplified divshiftcalc logic.	2022-09-21 13:02:34 -07:00
ifu	Cleaned up the IFU and LSU around dtim and irom address calculation.	2022-09-21 18:23:56 -05:00
lsu	Solved the sram write first / read first issue. Works correctly with read first now.	2022-09-22 14:16:26 -05:00
mmu	Created two new pma regions for dtim and irom.	2022-08-28 13:50:50 -05:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Cleaned up fcvt selection control to IEU and FPUIllegalInst signals	2022-08-23 12:17:19 -07:00
uncore	Renamed brom1p1r to rom1p1r.	2022-09-21 12:31:20 -05:00
wally	Found the ahb burst bug.	2022-09-17 20:30:01 -05:00
sdc