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2070 Commits

Author SHA1 Message Date
Ross Thompson
ebe4339953 Updated fpga test bench. 
Solved read delay cache bug.  Introduced during cache optimizations.
 2022-08-21 15:59:54 -05:00
Ross Thompson
85dbec5969 Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation. 2022-08-21 15:28:29 -05:00
Ross Thompson
f3f0f12904 Removed logic from Verilog wrapper. 2022-08-21 14:07:43 -05:00
Ross Thompson
82cce9a627 Updated fpga testbench. 2022-08-21 14:07:26 -05:00
Katherine Parry
a191603a1a fixed -1 issue in division 2022-08-20 00:53:45 +00:00
Ross Thompson
2ba390adf4 Possible reduction of ignorerequest. 2022-08-19 18:07:44 -05:00
Ross Thompson
517c0f6c35 Changed signal names. 2022-08-17 16:12:04 -05:00
Ross Thompson
f6e5746e59 Better name for LSUBusWriteCrit. Changed to SelLSUBusWord. 2022-08-17 16:09:20 -05:00
Ross Thompson
299aefb76a Removed old code from interlockfsm. 2022-08-17 12:52:56 -05:00
Katherine Parry
9549c23f45 sqrt tests in regression uncommented and pass 2022-08-07 23:38:10 +00:00
Katherine Parry
cb0c1b7488 radix-2 1 copy passes testfloat 2022-08-06 22:54:05 +00:00
Katherine Parry
de6ae471bc fixed fsw problem and removed 2 bit shift from shift correction 2022-08-03 22:16:51 +00:00
David Harris
898dbc8e74 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
7e5b78f240 plic-s debug 2022-08-03 12:33:09 +00:00
David Harris
e70b28f7f6 FMA cleanup 2022-08-02 07:42:32 -07:00
David Harris
2b932c4b80 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-02 07:34:12 -07:00
David Harris
887e4c73fb Moved InvA to sign block; simplified fmaexpadd coding 2022-08-02 07:34:09 -07:00
Ross Thompson
413a9bf58b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 22:09:11 -05:00
Ross Thompson
57fcf0ef79 Fixed fstore2 in cache? 2022-08-01 22:04:44 -05:00
David Harris
06c4f18cd1 merged lza back into main 2022-08-01 19:45:21 -07:00
David Harris
8147f75399 Fixed fmaadd to work with new LZA 2022-08-01 19:40:55 -07:00
Ross Thompson
797d9e3610 Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris. 2022-08-01 21:12:25 -05:00
Ross Thompson
3cd8404917 Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask. 2022-08-01 21:08:14 -05:00
Ross Thompson
3612db2d70 pulled swbbytemask out of subword write. 2022-08-01 20:48:45 -05:00
David Harris
7e4b04ff64 Parameterized fmalza 2022-08-01 16:18:02 -07:00
David Harris
94fa7a00e7 Completed LZA simplificaiton 2022-08-01 16:13:16 -07:00
David Harris
3b937b73fd lza cleanup 2022-08-01 16:01:02 -07:00
David Harris
b614f165fb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 15:47:58 -07:00
David Harris
91597bba87 lza cleanup 2022-08-01 15:47:03 -07:00
David Harris
f56b26ec40 lza cleanup 2022-08-01 15:43:48 -07:00
David Harris
c3e9719c99 lza cleanup 2022-08-01 15:40:12 -07:00
David Harris
d6b5e7a6ef lza cleanup 2022-08-01 15:37:09 -07:00
Katherine Parry
8ff3a693af regression passes fpu tests 2022-08-01 19:56:25 +00:00
Katherine Parry
9c68f85822 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-01 19:55:50 +00:00
David Harris
2869d67e50 more lza cleanup 2022-08-01 12:34:00 -07:00
David Harris
b34d2065c3 LZA cleanup 2022-08-01 12:30:42 -07:00
David Harris
99462049e7 LZA refactoring switched to Pp1, Gm1, Km1 2022-08-01 12:20:23 -07:00
David Harris
3c08aabcd3 LZA refactoring 2022-08-01 11:36:21 -07:00
Katherine Parry
eddf6e9ee1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-01 18:35:07 +00:00
David Harris
7f9b601467 fmalza edits to match textbook 2022-08-01 18:23:39 +00:00
David Harris
257107f908 Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
Ross Thompson
1ee613ae6c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-31 12:48:51 -05:00
Katherine Parry
1bd6351e1f re-added FStore2 in Cache 2022-07-29 22:54:49 +00:00
David Harris
93d7d7179e Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
David Harris
75a265159b Increased timeout threshold to avoid timeout building riscof tests on slow machine 2022-07-27 04:05:21 +00:00
David Harris
9ecef0c4cd fixed testbench merge comflict 2022-07-26 06:21:46 -07:00
David Harris
2d7f4b133c More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
766252db1b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-25 23:29:08 +00:00
David Harris
5c54c5b521 Added rv32f tests to RV64gc 2022-07-25 23:29:05 +00:00
David Harris
c6a58eb5b6 Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd 2022-07-25 16:23:10 -07:00
David Harris
416f5edfe0 More riscof makefile tuning 2022-07-25 21:15:56 +00:00
David Harris
7f7b3359b0 Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings 2022-07-25 20:50:38 +00:00
Ross Thompson
40e7cda84a Don't use this commit yet. Untested. 2022-07-24 15:40:52 -05:00
Ross Thompson
719b00e338 Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested. 2022-07-24 01:20:29 -05:00
Ross Thompson
69d520a7eb Removed replay from the config files. 2022-07-24 00:34:11 -05:00
Ross Thompson
f3cf46d633 Added more i-cache signals to wave file. 2022-07-24 00:24:13 -05:00
Ross Thompson
cd68896637 Merged evict dirty clear with flush write back. 2022-07-24 00:22:43 -05:00
Ross Thompson
8193946996 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-23 08:41:59 -05:00
Ross Thompson
05484c4c05 signal name cleanup. 2022-07-22 23:36:27 -05:00
Ross Thompson
27e32980ad cache cleanup after removing replay on cpubusy. 2022-07-22 23:30:25 -05:00
Ross Thompson
17ae1a1b1b cache fsm cleanup after removal of replay. 2022-07-22 23:25:09 -05:00
Ross Thompson
abc79c6c8e Possible improvement to cache which removes the cpu_busy states. 2022-07-22 23:20:37 -05:00
Katherine Parry
655e2d3810 merged radix-2 sqrt into divider - doesnt work yet 2022-07-23 00:41:18 +00:00
slmnemo
bfced6bfe8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
ca4511b6dc Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Daniel Torres
d0aaae26fe fixed wally rv32e tests, updated regression makefile to new testflow 2022-07-22 17:09:46 -07:00
Katherine Parry
b3d932cd61 divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
Daniel Torres
24828db612 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
4198145ce2 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00
slmnemo
ba2dcf6da4 fixed error in tests.vh 2022-07-22 14:55:55 -07:00
slmnemo
ec1ed5bd94 Added UART test to peripheral test 2022-07-22 14:55:34 -07:00
Daniel Torres
574e603d69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 13:52:19 -07:00
Daniel Torres
139e657fcc commented out embench test that should be commented out 2022-07-22 13:52:13 -07:00
slmnemo
df411497e0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 12:36:06 -07:00
slmnemo
cb16a75119 Added PLIC test to regression 2022-07-22 12:35:37 -07:00
Daniel Torres
0e75142ef4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 11:16:09 -07:00
Daniel Torres
95fdd408ee commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
cturek
e2691c02b7 Square root negative exponent handling 2022-07-22 16:45:19 +00:00
slmnemo
df568fd202 Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
David Harris
d22587090b Reset MSR on read 2022-07-22 04:29:27 +00:00
Daniel Torres
ae0f8de2b5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-21 20:59:01 -07:00
Daniel Torres
8dcb794bbb added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64 2022-07-21 20:58:58 -07:00
slmnemo
95822b77f0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-21 20:35:52 -07:00
slmnemo
3d2c6683d8 Fixed UART bug related to parity and MSR/LSR 2022-07-21 20:35:46 -07:00
cturek
8bfb233204 Changed testbench to operate on two inputs and one output, changed all test generators, changed srt module to return only one output and take in Mod as a signal to compute integer remainder 2022-07-22 01:27:08 +00:00
cturek
c7e84f8e40 Renamed variables, moved output handling to postprocessor, added remainder handling 2022-07-21 20:45:08 +00:00
Daniel Torres
9421b77613 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-21 12:50:04 -07:00
Daniel Torres
a8faddf81f removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes 2022-07-21 12:47:51 -07:00
Katherine Parry
0630e2a9a2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-21 19:38:15 +00:00
Katherine Parry
fbe8bb2298 radix-4 division integrated into srt - not tested 2022-07-21 19:38:06 +00:00
cturek
86ebdd05f0 Division working too 2022-07-21 17:59:10 +00:00
cturek
4793267bd7 Updated Radix2 Sqrt to follow new algorithm 2022-07-21 17:36:21 +00:00
Katherine Parry
7950a675ea added input enables and improved forwarding 2022-07-21 01:20:06 +00:00
Katherine Parry
a30d9c6bd8 turn off 2 word store durring non-fp instructions 2022-07-20 21:57:23 +00:00
Ross Thompson
1cad05fef9 Minor cleanup of cache. 2022-07-19 23:04:23 -05:00
Ross Thompson
8698799077 Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction. 2022-07-19 22:42:25 -05:00
Katherine Parry
b26297e874 moved ctrl signal registers into fctrl, also a lot of code cleaning 2022-07-20 02:27:39 +00:00
cturek
cce57fdcc5 divsqrt working for floating point 2022-07-20 02:04:20 +00:00
cturek
c3a4a2abdf New radix-2 algorithm implemented and working 2022-07-20 02:00:43 +00:00
cturek
0f94177765 small changes 2022-07-20 01:36:25 +00:00
Katherine Parry
70d2b2fdd7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-19 23:44:41 +00:00
Katherine Parry
d61f84e751 oprimized zeros and replaced complex ?: with always_comb 2022-07-19 23:44:37 +00:00
Daniel Torres
5b1adc7a67 commented out embench 2.0 tests 2022-07-19 13:36:18 -07:00
Ross Thompson
a79e5e11f6 Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added. 2022-07-18 23:37:18 -05:00
Katherine Parry
514674417e moved Se into execute stage 2022-07-19 01:10:10 +00:00
Katherine Parry
64b3e4117b reworked fmashiftcalc to match book 2022-07-19 00:04:24 +00:00
David Harris
9fd772ce83 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-18 23:11:12 +00:00
Katherine Parry
cce5fb8dfd moved Ss to execute stage 2022-07-18 20:48:56 +00:00
Katherine Parry
7268b4b334 removed underflow from inexactct calculation 2022-07-18 17:51:18 +00:00
Katherine Parry
d6f1fc12db Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-18 17:31:29 +00:00
Katherine Parry
0210718f19 renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
Ross Thompson
0ef6137ab9 Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN. 2022-07-17 21:05:31 -05:00
Ross Thompson
8356e5d742 Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width. 2022-07-17 16:20:04 -05:00
David Harris
03f573351a Rewrote convert shift calculation with always for ease of reading 2022-07-17 16:40:58 +00:00
David Harris
622773343f restored intPending logic to be sticky for PLIC 2022-07-16 17:43:31 -07:00
Katherine Parry
e3ed40620c forgot some files 2022-07-15 21:42:45 +00:00
Katherine Parry
304c81eb17 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-15 20:17:08 +00:00
Katherine Parry
5cb9c9f319 merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
cturek
8c57eca262 Square root radix 2 working, does not work with division 2022-07-14 22:52:09 +00:00
cturek
2f96989aab Square root 2022-07-14 21:19:45 +00:00
cturek
cabd41a5a0 Six tests passing and a bunch of sizizing issues fixed 2022-07-14 19:38:27 +00:00
Katherine Parry
83cc429700 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-14 18:16:13 +00:00
Katherine Parry
2fe8b6e34c fixed error in divsqrt 2022-07-14 18:16:00 +00:00
cturek
8f7ffc3f29 S and SM are updating but are not correct yet 2022-07-14 00:39:30 +00:00
Katherine Parry
66bef379cb renamed a file to fit diagram 2022-07-13 23:44:54 +00:00
cturek
0b91e7526f DIVLEN and counter updated for sqrt computation and rounding 2022-07-13 22:42:39 +00:00
Katherine Parry
3dcddf8453 some code cleanup 2022-07-13 15:28:22 -07:00
Katherine Parry
b874c5c05d removed minus 1 case in rounding 2022-07-13 15:01:38 -07:00
cturek
97a1548356 radix 4 files removed from srt and divlen modified for sqrt 2022-07-13 19:46:48 +00:00
cturek
b1906399aa Lint error fixed and added comments to preprocessing 2022-07-13 19:34:04 +00:00
cturek
5975d0d470 Testbench accepts standard test vector files 2022-07-13 18:30:18 +00:00
cturek
3ed6b8d1ff Test generation files in common format 2022-07-13 18:11:13 +00:00
cturek
120994b42b Finalized sqrt, ready for debugging 2022-07-13 17:56:23 +00:00
cturek
6e96ca2c9b Added adder input selection to on the fly converter 2022-07-13 17:47:27 +00:00
cturek
e9ce71ca20 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-13 17:36:56 +00:00
Katherine Parry
b45b3baec2 removed the +1 in the cvt 2022-07-13 09:41:35 -07:00
Katherine Parry
3c1bea1104 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
cturek
8d5081e8e9 little fix 2022-07-12 23:04:33 +00:00
cturek
b505ef135d Square root implemented 2022-07-12 22:45:54 +00:00
Katherine Parry
12a54161c0 found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
18d7fee541 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
cturek
8edf44063a C register and other various fixes 2022-07-12 22:18:56 +00:00
cturek
c60991f2bf On the fly conversion for square root 2022-07-12 02:21:38 +00:00
Katherine Parry
1267d33d3c forgot a file 2022-07-11 18:31:51 -07:00
Katherine Parry
ba339fc794 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-11 18:30:29 -07:00
Katherine Parry
bea4ec078d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00
DTowersM
fe7d03a3da added some preliminary support for coremark XLEN=32, made sure rv64 not impacted 2022-07-11 21:13:09 +00:00
David Harris
03a20610aa added comment about checking SRAM size 2022-07-10 12:48:51 +00:00
David Harris
d1a7832dd9 added comment about RAMs in cacheway 2022-07-10 12:47:34 +00:00
Katherine Parry
62205ebb3b renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
97e7e619d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
cturek
0dc30a0acf F Selection 2022-07-08 21:53:52 +00:00
Katherine Parry
c56fdd7e0f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-08 12:30:50 -07:00
Katherine Parry
88b4f9b40a renamed signals in cvt and prostproc 2022-07-08 12:30:43 -07:00
James Stine
99fed5d59f Update SRAM to /proj/wally 2022-07-08 08:09:55 -05:00
David Harris
8be1dafbd6 Removed testbench code that ignores mismatch on zero signatures 2022-07-08 09:17:31 +00:00
David Harris
87ea95e6c5 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-08 09:09:07 +00:00
David Harris
5ae88dbef0 Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc 2022-07-08 09:09:02 +00:00
David Harris
96cc66d151 Adjusting byte writes to RAM 2022-07-08 08:45:21 +00:00
David Harris
38ef8eebbb Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables 2022-07-08 08:44:37 +00:00
David Harris
234175f236 Removed unused swbytemask from CLINT 2022-07-08 08:43:24 +00:00
Katherine Parry
b67792086c moved unsused division code again 2022-07-07 16:41:26 -07:00
cturek
ccc97d6fee Sqrt exponents 2022-07-07 23:34:56 +00:00
Katherine Parry
2e772dee69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-07 16:29:44 -07:00
Katherine Parry
b1e2a1e5a1 Revert "moved old divsqrt to unusedsrc" 
This reverts commit 5dd07c76bd.
 2022-07-07 16:29:17 -07:00
DTowersM
4786fb9fd6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD 2022-07-07 23:11:35 +00:00
DTowersM
aa8580b2dc new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory 2022-07-07 23:11:02 +00:00
Katherine Parry
5dd07c76bd moved old divsqrt to unusedsrc 2022-07-07 16:09:56 -07:00
Katherine Parry
75a8cea4e4 srt divider merged into fpu 2022-07-07 16:01:33 -07:00
cturek
010ab2e90e Seventeen Square Root Tests 2022-07-07 22:48:46 +00:00
David Harris
425fec0f41 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 22:00:59 +00:00
Katherine Parry
c581fba4aa modified wally shared 2022-07-07 21:59:43 +00:00
David Harris
f865994ba1 fixing port errors 2022-07-07 21:57:10 +00:00
Katherine Parry
7771f7b3eb added load and store test 2022-07-07 21:48:51 +00:00
cturek
269884b672 Preprocessing for square root 2022-07-07 21:23:30 +00:00
David Harris
f2915129ab Preliminary SRAM integration 2022-07-07 19:56:20 +00:00
David Harris
bf5168873e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 15:51:33 +00:00
slmnemo
261248538c sim-buildroot-batch now runs wally-pipelined-batch 
with option buildroot buildroot-no-trace to boot linux from step 0
 2022-07-06 18:06:43 -07:00
David Harris
8ae7139545 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 23:44:47 +00:00
DTowersM
5dfff900b1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD 2022-07-06 23:44:27 +00:00
DTowersM
67c5d66209 added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu 2022-07-06 23:43:57 +00:00
David Harris
21fb120aac Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 23:43:05 +00:00
Ross Thompson
d716c25275 Fixed an issue with direct map cache's nextway logic. 
Also found a small error in the replacement policy.
 2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye
ad29e19a27 fixed width mismatch for rv64 ieuadrM and readdatawordM 2022-07-06 22:39:35 +00:00
David Harris
529f48ed58 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 13:26:26 +00:00
David Harris
76302a8599 PLIC and UART passing tests on APB 2022-07-06 13:26:14 +00:00
Madeleine Masser-Frye
52562c9190 new priority onehot module for better area/time 2022-07-06 00:08:59 +00:00
Madeleine Masser-Frye
b5454f3a55 took first match out of pmpadrdec 2022-07-06 00:02:01 +00:00
Madeleine Masser-Frye
d8ea12c6f4 fixed concatenation syntax 2022-07-05 22:36:54 +00:00
cturek
2faa8847f4 Radix 2 Integer division working (without signs or remainder) 2022-07-05 21:34:49 +00:00
David Harris
72e216d053 APB CLINT passing regression 2022-07-05 15:51:35 +00:00
David Harris
5f5ad77d4a Modified uncore to use AHB bridge to GPIO 2022-07-05 05:02:21 +00:00
David Harris
c8ac05ba7b AHB bridge for gpio 2022-07-05 05:01:59 +00:00
David Harris
ca95b46de5 Added reference to Schmookler01 for LOA 2022-07-05 05:01:12 +00:00
David Harris
1a356312b2 Added comments to PLIC about likely bug 2022-07-05 05:00:29 +00:00
David Harris
abfd935e06 removed delay in ahblite 2022-07-05 04:59:28 +00:00
David Harris
f5bdbbe219 Removed sig4 spurious message from testbench 2022-07-05 03:27:14 +00:00
David Harris
1bf701d958 Added check to halt testbench on failing to find file 2022-07-05 02:28:59 +00:00
Katherine Parry
2fc795ca70 added missing files 2022-07-03 21:40:47 -07:00
Katherine Parry
8ac722f693 Renaming signals to match chapter 2022-07-03 12:26:22 -07:00
David Harris
0fa35acbc5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-02 19:37:14 +00:00
David Harris
89b319aa1b FMA ZAligned name 2022-07-02 19:35:13 +00:00
Katherine Parry
8930cdcfbb some prostprocessing cleanup 2022-07-01 14:55:46 -07:00
slmnemo
454facc1cd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-29 13:40:15 -07:00
slmnemo
39831e3a40 ./regression-wally -buildroot or ./regression-wally -all now builds Linux from instruction 0 instead of trying to reach instruction 246000000 2022-06-29 13:40:11 -07:00
Daniel Torres
d1eebac73f reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished 2022-06-29 12:32:30 -07:00
Daniel Torres
2ae22ac6cb added changes to testbench, tests and riscof for additional riscof compatability 2022-06-29 12:23:40 -07:00
Katherine Parry
8f98f3bfab added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
Katherine Parry
d13a4c3378 removed an adder out of early termination 2022-06-28 18:01:11 +00:00
slmnemo
228028c837 Add CLINT tests from book 2022-06-27 20:09:58 -07:00
Katherine Parry
071abc9d82 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-28 00:16:36 +00:00
Katherine Parry
0417a6a45b very basic early termination passes testfloat 64-bit tests 2022-06-28 00:16:22 +00:00
cturek
7249295f53 Updated radix 2 divider to work with integers and floats in new structure. Integers still might not work. 2022-06-27 23:55:21 +00:00
cturek
487553077f Added int tests 2022-06-27 21:44:06 +00:00
Katherine Parry
a5fb60eb1a radix-4 early termination working for special cases - not working completely 2022-06-27 20:43:55 +00:00
Katherine Parry
adaee899bb radix-4 divider passing all double precision testfloat tests 2022-06-27 17:04:51 +00:00
Katherine Parry
70a1bb8377 fixed commented out error and removed killprod from result selection 2022-06-25 01:42:23 +00:00
Katherine Parry
fa1623551c passing regression again 2022-06-25 00:31:32 +00:00
Katherine Parry
6d6cc7bb48 commented out error - also some divider bugs fixed 2022-06-25 00:04:53 +00:00
Katherine Parry
43882d5878 modified result select to account for x/inf 2022-06-24 21:23:15 +00:00
Katherine Parry
a85a868b56 radix 4 division denormal result handeling 2022-06-24 21:02:50 +00:00
Katherine Parry
9eefba5b58 added denormal input handeling - radix 4 2022-06-24 19:41:40 +00:00
Katherine Parry
b5c20bf112 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-24 01:09:53 +00:00
Katherine Parry
ff1fae74d8 division by zero added 2022-06-24 01:09:44 +00:00
slmnemo
6cbd7f4f6e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-23 16:51:51 -07:00
slmnemo
528869ef14 Removed references to initialization files 2022-06-23 16:50:27 -07:00
Katherine Parry
ec2c446c7e forgot a file 2022-06-23 23:01:30 +00:00
Katherine Parry
b16e55906a div debug - accounted for 1 bit normalization in exponent calculation 2022-06-23 22:59:43 +00:00
Katherine Parry
749d405da8 lint warning fix 2022-06-23 22:37:44 +00:00
Katherine Parry
de71773d69 added radix-4 0/d handling 2022-06-23 22:36:19 +00:00
slmnemo
851335ac98 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-23 14:39:59 -07:00
slmnemo
bca8fe1694 Removed big64.txt reference, fixing a warning 2022-06-23 14:39:53 -07:00
Katherine Parry
a5fc6757a1 generate qsel4 in verilog 2022-06-23 21:38:04 +00:00
slmnemo
3a471ac7d6 Added wally32periph to regression 2022-06-23 14:37:18 -07:00
David Harris
44216b3967 Fixed typo in clint 2022-06-23 21:27:46 +00:00
David Harris
d969edeb99 Reset mtimecmp in clint 2022-06-23 21:20:55 +00:00
James Stine
4ff866b39e Update 2022-06-23 11:59:05 -05:00
James Stine
fe1b7a67cb Add sqrt qlsc table generator 2022-06-23 11:46:44 -05:00
Katherine Parry
d7a363aaa7 fixt lint error 2022-06-23 16:11:50 +00:00
Katherine Parry
1612daa294 Testfloat running division - not passing 2022-06-23 00:07:34 +00:00
slmnemo
48c65db35c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-21 16:10:25 -07:00
slmnemo
09a633d7d1 changed order of makefiles and fixed warnings when running makes 2022-06-21 16:10:18 -07:00
David Harris
a2814898c8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 22:56:02 +00:00
David Harris
ac5dfc41f1 Trimmed lint-wally 2022-06-21 22:56:01 +00:00
slmnemo
6ba3a7615c added individual makes for arch and wally tests as well as memfiles to Makefile. run using make archtests/wallytests/memfiles 2022-06-21 15:54:24 -07:00
Katherine Parry
6001956bd8 using memread for quotent select 2022-06-21 15:49:52 -07:00
Katherine Parry
03b9878005 removed rv64fp from lint 2022-06-21 15:48:47 -07:00
David Harris
d865a1ce95 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 22:45:28 +00:00
Daniel Torres
1fab7605f5 fixed issue where the unused spike elf files were being used to find objdump files that didn't exist causing makefile-memfile to fail prematurely 2022-06-21 15:39:04 -07:00
Madeleine Masser-Frye
6229779b97 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 20:31:06 +00:00
Madeleine Masser-Frye
3c08861479 switched comparator to dc flip version 2022-06-21 20:30:33 +00:00
James Stine
b1f12f3345 Add hex output in bad but okay way 2022-06-21 15:07:24 -05:00
James Stine
ca0815ce0d Add MATLAB scripts for PD plot 2022-06-21 10:14:53 -05:00
slmnemo
80a57d0469 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-21 02:16:26 -07:00
slmnemo
b2cea45de0 Added rudimentary GPIO test according to testplans in chapter 15 2022-06-21 02:16:21 -07:00
Katherine Parry
0c6d36bbb2 made fixes to radix-2 divider testbench - divider doesn't pass 2022-06-20 23:01:53 +00:00
Katherine Parry
a0abfdefe6 radix-4 divider passing tests 2022-06-20 22:56:08 +00:00
Katherine Parry
03d823f5d7 added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
James Stine
46bf9c351c Update C program for r=4 division by recurrence to match Table in EL 2022-06-20 11:32:40 -05:00
Daniel Torres
397783812d embench and testbench now support running both O2 and Os build variations without overwriting one another 2022-06-17 21:15:42 -07:00
Daniel Torres
1d4c543f71 arch tests now run on spike and sail and compare signatures during build 2022-06-17 20:53:15 -07:00
Daniel Torres
0ede7c412e removed old code from makefile, simplified code in testbench 2022-06-17 15:13:38 -07:00
Daniel Torres
475220a5ff arch bug fixes and testbench changes 2022-06-17 15:07:16 -07:00
David Harris
a911077a01 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-17 15:45:24 +00:00
Katherine Parry
2a8c17170c hopefully fixed lint error 2022-06-17 00:14:39 +00:00
Katherine Parry
c9cbf6082d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-15 22:58:42 +00:00
Katherine Parry
0ffaec850b postprocess out of fpu critical path 2022-06-15 22:58:33 +00:00
Madeleine Masser-Frye
154a1c80c1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-15 18:30:27 +00:00
Madeleine Masser-Frye
84256924e7 cleanup, plots for paper 2022-06-15 18:28:36 +00:00
James Stine
c660403ff2 Add back SV for integer division to use 8-bit CPA in qslc 2022-06-15 11:46:39 -05:00
James Stine
a078015271 Add r=4 C code 2022-06-15 11:44:09 -05:00
Katherine Parry
08b2481917 some synth fpu optimizations 2022-06-14 23:58:39 +00:00
David Harris
f6e52c7f08 Removed testbench.sv.bak 2022-06-14 22:04:38 +00:00
Katherine Parry
8e19331ad5 removed false critical path from fpu 2022-06-14 16:50:46 +00:00
Katherine Parry
674c31ce59 fixed acciedental critical path in FPU 2022-06-14 00:02:38 +00:00
DTowersM
7c0f4dd954 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 23:34:35 +00:00
DTowersM
39ed36d0ba added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug) 2022-06-13 23:23:57 +00:00
Katherine Parry
5f7072bd96 postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
David Harris
802bfd74fb Cleanup on RAM module 2022-06-13 19:37:43 +00:00
David Harris
3c44b5842b Typo in gpio reset 2022-06-13 19:37:05 +00:00
slmnemo
3626d5880e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-13 12:30:33 -07:00
David Harris
9e1ec0255f Removed SRT testvectors from repo 2022-06-13 19:27:33 +00:00
slmnemo
05a217c7e7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-13 12:27:23 -07:00
slmnemo
c5d2037a7f Merge branch 'cacheburstmode' into main. 
Cache burst mode is now working! It also uses the new RAM.
 2022-06-13 12:26:18 -07:00
slmnemo
a21d731834 Added more comments 2022-06-13 12:26:08 -07:00
David Harris
9080e35e54 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 19:26:07 +00:00
David Harris
09d72a33c5 Fixed XOR logic in GPIO 2022-06-13 19:26:03 +00:00
slmnemo
9f4ca06f7f Added comment about name of LSUBusInit/Lock signal 2022-06-13 10:56:02 -07:00
slmnemo
a79737e95b Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals 2022-06-10 20:43:56 -07:00
slmnemo
d6a1ee1141 Added comments to signals added so the bus is easier to analyze 2022-06-10 20:30:04 -07:00
slmnemo
31852fdb19 Fixed failed regression state by only enabling counting when doing cached operations 2022-06-10 20:00:09 -07:00
slmnemo
0e10435fb6 Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01. 2022-06-10 19:10:01 -07:00
Madeleine Masser-Frye
032385aee3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-10 21:11:47 +00:00
Madeleine Masser-Frye
374dfd1fc2 added 'd' suffix to muxes for data-critical synths 2022-06-10 21:11:05 +00:00
DTowersM
a61d1ab087 simplified coremark 2022-06-10 19:15:17 +00:00
slmnemo
5ac17eca1d Passed Regression: Seems to work perfectly fine 2022-06-09 18:21:13 -07:00
slmnemo
75dffe4dcc Merge branch 'main' into cacheburstmode 2022-06-09 17:51:03 -07:00
slmnemo
a4c7d1d936 ? 2022-06-09 17:50:47 -07:00
DTowersM
d280f10a8d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-10 00:38:07 +00:00
DTowersM
4e5d7ec3d6 changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability 2022-06-10 00:37:53 +00:00
slmnemo
c4bc608268 Changes made on 9th Jun 2022-06-09 17:33:51 -07:00
slmnemo
cc8acd947d Fixed lint error 2022-06-09 17:22:04 -07:00
David Harris
c1a40a15dd New RAM for further testing 2022-06-09 23:50:43 +00:00
stineje
d3ad512d3c Update integer division for r4 and qslc_r4a2.c 2022-06-09 16:45:13 -05:00
David Harris
5612ca7041 qslc_r4a2 generator 2022-06-09 17:26:47 +00:00
slmnemo
8ae57f075f Fixed error when doing uncached accesses where HTRANS was always 2 2022-06-08 18:58:07 -07:00
slmnemo
1605544bfc Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request. 2022-06-08 17:34:02 -07:00
Madeleine Masser-Frye
88285c684c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-09 00:08:15 +00:00
Madeleine Masser-Frye
a54837b102 added one bit muxes for data critical synths 2022-06-09 00:06:12 +00:00
slmnemo
655266a216 Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending 2022-06-08 15:59:15 -07:00
slmnemo
a64e65e54c Fixed ifu displaying LSU bus state in wave.do 2022-06-08 15:30:32 -07:00
slmnemo
dd33f2a009 Working version: Fixed error where Word count would always increment even without AHB to bus ACK 2022-06-08 15:29:32 -07:00
slmnemo
be658d3933 Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors 2022-06-08 15:03:15 -07:00
DTowersM
571eb21f41 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-08 16:28:18 +00:00
DTowersM
38382e3a11 added #1 delays to Stalls and Flushes in hazard unit 2022-06-08 16:28:09 +00:00
slmnemo
a5aa75e5de Merge branch 'main' into cacheburstmode 2022-06-08 02:21:33 +00:00
slmnemo
1d22fc707a Added lock signal to ensure AHB speaks with the right bus 2022-06-08 02:19:21 +00:00
David Harris
b53aef33f5 Modified RAM for single-cycle latency 2022-06-08 02:06:00 +00:00
David Harris
cc06fa1c55 Cleaned bram interface 2022-06-08 01:39:44 +00:00
David Harris
f81719337e Added ahbapbbridge and cleaning RAM 2022-06-08 01:31:34 +00:00
DTowersM
1d41e98504 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-07 23:58:58 +00:00
DTowersM
3d654fd481 modified testbench.sv- now works with coremark 2022-06-07 23:58:50 +00:00
DTowersM
930c806753 cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000 2022-06-07 23:27:54 +00:00
slmnemo
85801e75db Fixed off-by-one error in busdp capture 2022-06-07 19:36:39 +00:00
slmnemo
90c5e5d319 Reworked bus to handle burst interfacing 2022-06-07 11:22:53 +00:00
DTowersM
4cadf139a6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-07 06:03:19 +00:00
DTowersM
fbfae61ba8 added support for 64 bit rv tests 2022-06-07 06:02:23 +00:00
Katherine Parry
b8cff98e48 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-06 16:06:54 +00:00
Katherine Parry
eb93bd46d7 fma synth warnings and errors removed 2022-06-06 16:06:04 +00:00
slmnemo
3a276f4c39 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-03 18:56:29 -07:00
slmnemo
8c3d7b404b Fixed recurrent issue with testbench where it would never stop 2022-06-03 18:56:24 -07:00
cturek
0e308cfccc Added integer division in srt, parametrized everything to work with integers and floating points, parametrized testbench. 2022-06-04 00:14:10 +00:00
DTowersM
23d524b439 testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh 2022-06-03 22:07:14 +00:00
Madeleine Masser-Frye
2383ca4f53 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-03 21:08:49 +00:00
Madeleine Masser-Frye
6c6a12cfd5 added muxes and inv, fixed priority encoder 2022-06-03 21:03:13 +00:00
Katherine Parry
b785b6a9bc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-03 15:34:27 +00:00
Katherine Parry
5ae63f913a fixed compilation errors 2022-06-03 15:34:17 +00:00
slmnemo
0011a1b269 Changed NO_SPOOFING from 0 to 1 in buildroot-no-trace to better facilitate wally booting linux without following QEMU's trace 2022-06-03 04:55:14 -07:00
Katherine Parry
019994c802 removed some debuging code accedentally pushed 2022-06-02 22:45:19 +00:00
Katherine Parry
dfec6bda8a added rv64fpquad 2022-06-02 22:10:00 +00:00
Katherine Parry
39101fcbb3 added config rv64fpquad 2022-06-02 22:09:11 +00:00
David Harris
12399ba924 renamed sim-fp to sim-testfloat 2022-06-02 15:05:29 -07:00
Katherine Parry
c5bde75e30 added createallvectors 2022-06-02 21:56:05 +00:00
slmnemo
b35824eadd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-02 12:54:08 -07:00
Katherine Parry
ccda4c771e fpu paramaterized - except fdivsqrt 2022-06-02 19:50:28 +00:00
slmnemo
568b83a647 Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do" 
This reverts commit 7d2bfb6db8.
 2022-06-02 12:45:21 -07:00
slmnemo
40abe59d33 Revert "Fixed buildroot by adding a second ." 
This reverts commit 0982417054.
 2022-06-02 12:43:59 -07:00
slmnemo
581c950193 Revert "Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py" 
This reverts commit 05d14bdb3c.
 2022-06-02 12:41:01 -07:00
slmnemo
74319c2af6 Revert "Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace" 
This reverts commit a5490c7096.
 2022-06-02 12:40:46 -07:00
David Harris
9065b684f8 Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit 2022-06-02 09:37:59 -07:00
David Harris
62865d9398 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-02 15:48:36 +00:00
David Harris
7cf5d481c0 Cleaned up comments in controller 2022-06-02 15:48:33 +00:00
David Harris
9cd6b309b4 Cleaned up test cases in testbench 2022-06-02 08:44:28 -07:00
David Harris
129fab3794 Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
slmnemo
61f077f62c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-02 02:52:03 +00:00
slmnemo
35caa03e46 Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files 2022-06-02 02:51:51 +00:00
Katherine Parry
74b549ddc8 paramerterized some small fma units 2022-06-01 23:34:29 +00:00
DTowersM
4fbce9fc45 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-01 21:00:51 +00:00
DTowersM
d3c8ee7154 added support for embench post processing to testbench.sv 2022-06-01 21:00:44 +00:00
Katherine Parry
707067548f unpacker optimizations 2022-06-01 16:52:21 +00:00
slmnemo
108f32e9df Fixed double assignment on LSUBurstType 2022-06-01 01:04:49 +00:00
cturek
e3a0ee333f Fixed typos 2022-06-01 00:07:36 +00:00
slmnemo
56121b3587 Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access 2022-05-31 16:33:05 -07:00
slmnemo
2b80788235 Merge branch 'cacheburstmode' of github.com:davidharrishmc/riscv-wally into cacheburstmode 2022-05-31 15:57:55 -07:00
slmnemo
c24f88c2e9 Redid the FSM to prepare for burst mode implementation 2022-05-31 15:57:42 -07:00
David Harris
efe4b3e8fe Unpackinput cleanup 2022-05-31 22:31:21 +00:00
David Harris
99da6537cc Removed normalized output from unpack and simplified interface 2022-05-31 21:32:31 +00:00
David Harris
79df271a6f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-31 21:12:45 +00:00
David Harris
31815422d2 ../src/privileged/csrc.sv 2022-05-31 21:12:17 +00:00
DTowersM
f7491e8445 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-31 20:13:41 +00:00
DTowersM
2088c0cd7c added testbench.sv support for embench tests, test output still WIP 2022-05-31 20:13:32 +00:00
DTowersM
abb6ba97cf removed delapidated signals SIE_REGW SIP_REGW TimerIntM SwIntM 2022-05-31 20:10:56 +00:00
DTowersM
ea07588999 added embench tests to tests.vh 2022-05-31 20:08:04 +00:00
Katherine Parry
cd7fe9af61 reorginized unpackinput signals 2022-05-31 17:40:34 +00:00
Katherine Parry
559c0c278e added unpackinput.sv 2022-05-31 16:18:50 +00:00
David Harris
2935188035 Moved delegation logic from privmode to trap to simplify interface 2022-05-31 14:58:11 +00:00
David Harris
d1ef3b8981 Removed unused fp add and convert modules 2022-05-29 23:07:56 +00:00
Katherine Parry
835a4e4606 fixed lint error 2022-05-28 10:20:13 -07:00
slmnemo
3b9ae58f59 Reverted commit 9b55e9da38 2022-05-28 04:00:01 -07:00
slmnemo
2f3689063a Revert Commit 61ebf68939 2022-05-28 03:35:17 -07:00
slmnemo
9b55e9da38 Changed NO_IE_MTIME_CHECKPOINT so it uses the new parameter name 2022-05-28 03:16:55 -07:00
slmnemo
61ebf68939 Deparametrized Linux testbench and removed mentions of parameters in wally-pipelined.do 2022-05-28 03:14:49 -07:00
slmnemo
f426850bc7 Reverted incorrect Ack 2022-05-28 10:06:26 +00:00
David Harris
80315fedff fixed merge conflicts 2022-05-28 09:44:55 +00:00
David Harris
4335895b21 Added comments to some files, added a+b = 0 detector to comparator.sv 2022-05-28 09:41:48 +00:00
Katherine Parry
822866fd0a removed unused signal from FMA 2022-05-27 16:47:56 -07:00
Katherine Parry
d5c249bf71 unpacker adds 1 to denorm expoents 2022-05-27 14:37:10 -07:00
Katherine Parry
3c63db9554 some optimizations in unpacker 2022-05-27 11:36:04 -07:00
Katherine Parry
b288f812ab moved lzc to generic and small optimizations on fcvt 2022-05-27 09:04:02 -07:00
Katherine Parry
efb972c6d3 Removed guard bit from fma rounding 2022-05-27 08:23:46 -07:00
slmnemo
bddc32ed21 changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word 2022-05-26 18:41:27 -07:00
slmnemo
efce3e4953 added LSUBurstDone signal to signal when a burst has finished 2022-05-26 16:29:13 -07:00
cturek
f7a3855af1 fixed sizing issues in expcalc 2022-05-26 22:35:17 +00:00
cturek
a025014650 Implemented on-the-fly conversion for unsigned numbers 2022-05-26 22:20:43 +00:00
Katherine Parry
b13c3d5385 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-26 20:48:30 +00:00
Katherine Parry
550c4d380c fcvt.sv paramaterized 2022-05-26 20:48:22 +00:00
slmnemo
ae460eccd4 Added signal to monitor HBURST and comments for each burst in busdp 2022-05-26 13:35:49 -07:00
DTowersM
ea882e7271 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-26 19:05:21 +00:00
DTowersM
a983791d64 fixed indent spacing (cosmetic change) 2022-05-26 19:04:21 +00:00
cturek
0f1da722bf Set up the divider for on-the-fly conversion 2022-05-26 16:45:28 +00:00
slmnemo
80965f953c added burst size signals to the IFU, EBU, LSU, and busdp 2022-05-25 18:02:50 -07:00
slmnemo
1d3752b0b3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-25 17:41:04 -07:00
slmnemo
466fb71add added a todo to riscv-wally so that long buildroot looks for a successful boot rather than a specific instruction 2022-05-25 17:40:57 -07:00
slmnemo
87cfd62e19 Added line to testbench to prevent annoying burst sizes 2022-05-25 17:29:45 -07:00
slmnemo
95d64fe4ae idk lol it says this has an unadded change 2022-05-25 17:17:49 -07:00
DTowersM
41f6233a70 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-26 00:12:46 +00:00
slmnemo
3efe43af60 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-25 17:11:03 -07:00
slmnemo
5a9e3a852a see commit 9042cc3c 2022-05-25 17:10:59 -07:00
Katherine Parry
f4b9ade942 added fcvt.sv 2022-05-26 00:10:51 +00:00
DTowersM
aa574d545c Merge branch 'embench' into main 
embench contained the working makefiles for embench and is being merged into main as it working and done
 2022-05-26 00:10:50 +00:00
DTowersM
5e87506772 working makefile for embench and removed testbench-f64 2022-05-26 00:08:18 +00:00
slmnemo
17dff315f4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-25 17:03:26 -07:00
slmnemo
d43d340e31 added logic to prevent cache line length from exceeding the max size of a burst. 2022-05-25 17:03:15 -07:00
cturek
366cd5f1d5 Renamed variables for readability 2022-05-26 00:01:51 +00:00
cturek
650779318d Fixed exponent verification, added sign module and added sign tests 2022-05-25 23:36:21 +00:00
Katherine Parry
c264585fe8 single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
Madeleine Masser-Frye
c8892f2847 ppaAnalyze: docstrings and tsmc28 plotting 2022-05-25 13:52:20 +00:00
Madeleine Masser-Frye
7d1448d2ad added support for tsmc28, fixed ff modules/analysis for timing 2022-05-25 06:44:22 +00:00
slmnemo
cd9f0cd6bd fixed a comment spelling typo 2022-05-23 19:24:28 -07:00
Katherine Parry
18bdaf0179 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-23 23:11:41 +00:00
Katherine Parry
37e74648a9 added exponents to srt divider 2022-05-23 23:07:27 +00:00
David Harris
2d175e2a37 Checked in qst2.c from James 2022-05-23 20:26:05 +00:00
Ross Thompson
1dde9db2ce Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 23:54:33 -05:00
Ross Thompson
13f7f48776 Possible plic fix? 2022-05-22 23:47:01 -05:00
Madeleine Masser-Frye
99aa110615 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-22 23:23:39 +00:00
Madeleine Masser-Frye
378523087f added widths for csa in ppa 2022-05-22 23:23:02 +00:00
Ross Thompson
ff8e158ec4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 10:55:33 -05:00
Ross Thompson
848abf29b5 Fixed receive fifo ITNR bug. 2022-05-22 10:55:28 -05:00
Ross Thompson
1318f702cf Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Madeleine Masser-Frye
0bcae85792 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-05-21 09:53:31 +00:00
Madeleine Masser-Frye
fcaf032a0d ppa updates 
added widths to modules, automated frequency sweep synthesis, added slack violation color coding to plots
 2022-05-21 09:53:26 +00:00
slmnemo
a5d5bd272b changes suggested by ben, hopefully fixing buildroot (which is now not running) 2022-05-20 18:42:38 -07:00
Katherine Parry
6bc31f2e78 Fixed unpacker bug LT EQ LE pass testfloat 2022-05-20 17:19:50 +00:00
slmnemo
af675bbefb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-19 18:31:56 -07:00
slmnemo
4a2538455d added documentation for ahblite burst types to ahblite.sv 2022-05-19 18:31:46 -07:00
slmnemo
3b4286ec33 fixed lint autofailing due to no log being produced in regression-wally 2022-05-19 18:30:59 -07:00
slmnemo
6c237e43d8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-19 17:51:45 -07:00
slmnemo
a5490c7096 Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace 2022-05-19 17:51:26 -07:00
slmnemo
05d14bdb3c Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py 2022-05-19 17:50:48 -07:00
slmnemo
0982417054 Fixed buildroot by adding a second . 2022-05-19 17:49:32 -07:00
slmnemo
7d2bfb6db8 parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do 2022-05-19 16:21:38 -07:00
Katherine Parry
bc4804d90a fixed lint warning 2022-05-19 20:34:06 +00:00
Katherine Parry
b0881495a9 Bug fixed in unpacker and sub/add/mul tests pass TestFloat 2022-05-19 20:31:23 +00:00
mmasserfrye
b255f61521 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-19 20:24:57 +00:00
mmasserfrye
710905b239 updated synth plotting and regression 2022-05-19 20:24:47 +00:00
Katherine Parry
cc0ab94ebc Added fp tests - doesnpass yet 2022-05-19 16:32:30 +00:00
slmnemo
af14c8a064 added instructions to slack notifier 2022-05-18 16:50:31 -07:00
mmasserfrye
1442afe4e2 added support for plotting and fitting power 2022-05-18 17:01:55 +00:00
mmasserfrye
1888a9a665 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-18 16:10:36 +00:00
mmasserfrye
0265d1988e adapted shifter in ppa.sv for widths beside 32 and 64 
modified plotting and regression in ppaAnalyze.py
 2022-05-18 16:08:40 +00:00
Ross Thompson
9079e67aae Updated fpga debugger. 2022-05-17 23:04:01 -05:00
slmnemo
7cd673fa6e simplified make-tests.sh to run the current makefile in regression 2022-05-17 17:29:34 -07:00
slmnemo
ebeebf3bfc Revert "same as last breaking commit, testing if the bisect works to output a breaking commit." 
This reverts commit 910475ea56.

gottem
 2022-05-17 17:26:33 -07:00
slmnemo
910475ea56 same as last breaking commit, testing if the bisect works to output a breaking commit. 2022-05-17 17:22:09 -07:00
slmnemo
36ea0f9126 Revert "broke it again but this time it doesn't compile due to a missing semicolon on Rs1D." 
This reverts commit 0dea11fc73.

fixed it
 2022-05-17 17:05:11 -07:00
slmnemo
0dea11fc73 broke it again but this time it doesn't compile due to a missing semicolon on Rs1D. 2022-05-17 17:03:16 -07:00
slmnemo
73d19b0956 Revert "Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression" 
This reverts commit 83e4ab711c.

unbroke wally
 2022-05-17 16:57:29 -07:00
slmnemo
29bc8d6902 Revert "Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main"" 
This reverts commit c15aab9c6f.

reverted the wrong commit
 2022-05-17 16:57:00 -07:00
slmnemo
c15aab9c6f Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main" 
This reverts commit d601c89d2a, reversing
changes made to 1131d41343.

undid things
 2022-05-17 16:54:29 -07:00
slmnemo
83e4ab711c Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression 2022-05-17 16:33:09 -07:00
slmnemo
d601c89d2a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Added empty directory '/wkdir' to /pipelined/regression to avoid tests failing out of box due to the missing directory
 2022-05-17 20:32:53 +00:00
slmnemo
1131d41343 added wkdir in regression so regression runs out of box (assuming the old version of arch tests) 2022-05-17 20:32:38 +00:00
David Harris
83494e349b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 15:09:52 +00:00
David Harris
20c861ee6f Restored srt to working without exponent unit 2022-05-17 15:09:48 +00:00
mmasserfrye
43cf4f35cd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 01:11:58 +00:00
mmasserfrye
24420dea6c added 8 and 128 bit versions, adjusted alu 2022-05-17 01:11:43 +00:00
slmnemo
ba572b46f4 Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature. 2022-05-17 01:04:13 +00:00
slmnemo
ede0a3237d quit 2022-05-17 01:03:09 +00:00
David Harris
0fb6fe4cc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 00:07:09 +00:00
David Harris
b992a61ca3 removed exptestgen 2022-05-17 00:06:44 +00:00
David Harris
7aba83a35c Cleaned up unpacker changes in srt and lint errors 2022-05-17 00:06:14 +00:00
slmnemo
c84731d6d0 Fixed grammar on two comments in bpred.sv 2022-05-16 22:41:18 +00:00
mmasserfrye
c8e43e9798 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
resolved merge conflict
 2022-05-16 15:42:59 +00:00
mmasserfrye
2ca897620f tuning modules for ppa 2022-05-16 15:39:15 +00:00
David Harris
f5e2cff45a Cause simplification 2022-05-12 23:47:21 +00:00
David Harris
6303d4e81f Cause simplification 2022-05-12 23:39:10 +00:00
David Harris
c4621c5b6b Cause simplification 2022-05-12 23:37:40 +00:00
David Harris
7daf631c13 Cause simplification 2022-05-12 23:33:35 +00:00
David Harris
de51c7eeb3 Cause simplification 2022-05-12 23:33:22 +00:00
David Harris
803bfc4fe4 Cause simplification 2022-05-12 23:29:35 +00:00
David Harris
2d27d20db9 Cause simplification 2022-05-12 23:27:02 +00:00
David Harris
87dadc8208 trap/csr cleanup 2022-05-12 22:26:21 +00:00
David Harris
ea0d9fd9a8 More trap/csr simplification 2022-05-12 22:06:03 +00:00
David Harris
2eb6a65fa2 More trap/csr simplification 2022-05-12 22:04:20 +00:00
David Harris
2d8ccbd4ea More trap/csr simplification 2022-05-12 22:00:23 +00:00
David Harris
417e36bff5 More trap/csr simplification 2022-05-12 21:55:50 +00:00
David Harris
ca6b7716e2 Simplifying trap/csr interface 2022-05-12 21:50:15 +00:00
David Harris
56c154f2e7 Simplified MTVAL logic 2022-05-12 21:36:13 +00:00
David Harris
730bcac6ba Partitioned privileged pipeline registers into module 2022-05-12 20:45:45 +00:00
David Harris
c5868b81e4 privileged cleanup 2022-05-12 20:21:33 +00:00
mmasserfrye
517e44746e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 20:20:40 +00:00
mmasserfrye
2675c217e0 cleaned lint for ppa.sv 2022-05-12 20:20:05 +00:00
David Harris
5537c33196 Formatting cleanup 2022-05-12 18:37:47 +00:00
mmasserfrye
57a69d0f67 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 18:08:20 +00:00
mmasserfrye
30a1ba7bcf renamed madzscript, modified ppa.sv alu and shifter 2022-05-12 18:05:02 +00:00
David Harris
449472ba58 Moved Breakpoint and Ecall fault logic into privdec 2022-05-12 16:45:53 +00:00
David Harris
9f8dca5190 Moved TLB Flush logic into privdec 2022-05-12 16:41:52 +00:00
David Harris
1d01bc98a4 Moved WFI timeout into privdec 2022-05-12 16:22:39 +00:00
David Harris
21c1e58829 Partitioned privilege mode fsm into new module 2022-05-12 16:16:42 +00:00
David Harris
61199ccd13 More signal cleanup 2022-05-12 15:39:44 +00:00
David Harris
4c5e361b00 More unused signal cleanup 2022-05-12 15:26:08 +00:00
David Harris
5acb526375 More unused signal cleanup 2022-05-12 15:21:09 +00:00
David Harris
7e764fbda1 More unused signal cleanup 2022-05-12 15:15:30 +00:00
David Harris
e2dea3bb89 Removed more unused signals, simplified csri state 2022-05-12 15:10:10 +00:00
David Harris
fb725a9e0a Clean up unused signals 2022-05-12 14:49:58 +00:00
David Harris
8372bc86a7 Removing unused signals 2022-05-12 14:36:15 +00:00
David Harris
15659b05e4 Simplifed mstatus.TSR handling 2022-05-12 14:09:52 +00:00
David Harris
877c4eefd1 Fixed typo in csrm 2022-05-12 06:55:39 -07:00
mmasserfrye
cf900cf44d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 07:24:04 +00:00
mmasserfrye
52b0e7d567 filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
David Harris
32f8841f79 Added MCONFIGPTR CSR hardwired to 0 2022-05-12 04:31:45 +00:00
David Harris
c738c130de merged ppa.sv 2022-05-11 18:14:16 +00:00
David Harris
e37d262e4c PPA script progress 2022-05-11 18:11:51 +00:00
mmasserfrye
70fe1184db ed 
modified ppa.sv
 2022-05-11 16:22:12 +00:00
David Harris
a8c9f504fa Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt 2022-05-11 15:08:33 +00:00
David Harris
91472eb948 Removed M suffix from interrupts because they are generated asynchronously to pipeline 2022-05-11 14:41:55 +00:00
David Harris
91b786c58d Updated PPA experiment 2022-05-10 23:09:42 +00:00
David Harris
d53e4b1b1f Initial PPA study 2022-05-10 20:48:47 +00:00
David Harris
b869190161 endian swapper 2022-05-08 06:51:50 +00:00
David Harris
8066ba45e8 Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
David Harris
2792d77e4e Fixed bug in delegated interrupts not being taken 2022-05-08 04:50:27 +00:00
David Harris
2cdd49c7d2 WFI terminates when an interrupt is pending even if interrupts are globally disabled 2022-05-08 04:30:46 +00:00
David Harris
7024293a59 Zero'd wfiM when ZICSR not supported to fix hang in E tests 2022-05-05 15:32:13 +00:00
David Harris
66424a8246 SFENCE.VMA should be illegal in user mode 2022-05-05 15:15:02 +00:00
David Harris
866540580a SFENCE.VMA should be illegal in user mode 2022-05-05 14:59:52 +00:00
David Harris
c100c9893b wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
David Harris
94459ade3d Changed WFI to stall pipeline in memory stage 2022-05-05 02:03:44 +00:00
Kip Macsai-Goren
25ad39939f put privileged tests back into rv32/64gc 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
0f70e48b6b updated makefrag and tests.vh to reflect removed tests, new names 2022-05-04 21:20:25 +00:00
David Harris
8eee0c0ca3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-03 18:32:04 +00:00
David Harris
554c2b3550 Illegal instruction fault when running FPU instruction with STATUS_FS = 0 2022-05-03 18:32:01 +00:00
David Harris
cb1a7d54a4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-03 08:53:35 -07:00
David Harris
4fbf78e049 clean up sram1p1rw; still doesn't work on Modelsim 2022.1 2022-05-03 08:31:54 -07:00
David Harris
9c4de0e9c1 FPU generates illegal instruction if MSTATUS.FS = 00 2022-05-03 11:56:31 +00:00
David Harris
dee32f70bf Switched to behavioral comparator for best PPA 2022-05-03 11:00:39 +00:00
David Harris
bc123b5564 Comparator experiments 2022-05-03 10:54:30 +00:00
David Harris
7e3f75a35d Formatting cache.sv 2022-05-03 10:53:20 +00:00
David Harris
bc132c3e20 sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera 2022-05-03 03:50:41 -07:00
David Harris
3f2ec0499f Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense. 2022-05-03 03:45:41 -07:00
David Harris
7268ff1fd4 Changed loop variable in CLINT because of error only seen on VLSI 2022-05-03 10:10:28 +00:00
Kip Macsai-Goren
e557e420b6 added missing SIE test 2022-04-29 19:54:29 +00:00
Kip Macsai-Goren
5df381e26f renamed PIE-stack tests to status-mie for clarity 2022-04-29 18:30:39 +00:00
Kip Macsai-Goren
c3ffcd0e95 removed old unused tests from wally arch tests 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
3d1e1202f3 set WFI timeout to after 16 bits of counting for all configs 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
0e5cc40360 added 32 bit versions of new tests. all but timeout wait pass regression 2022-04-28 18:14:07 +00:00
Skylar Litz
970f6c4222 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-27 10:50:19 -07:00
Skylar Litz
594db170de fix AttemptedInstructionCount from ground zero 2022-04-27 10:45:40 -07:00
David Harris
6e8b27de17 Added torture.tv test vectors 2022-04-27 13:08:36 +00:00
David Harris
ffd4713fd1 Checked in torture.tv 2022-04-27 13:06:24 +00:00
David Harris
9042844b38 Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv 2022-04-26 19:41:30 +00:00
Kip Macsai-Goren
89cce88d33 fixed incorrect configs in regression 2022-04-25 19:28:47 +00:00
Kip Macsai-Goren
0f4ca62157 added working tests to test list, updated regression for new configs 2022-04-25 19:18:15 +00:00
Kip Macsai-Goren
8ad920fcb3 fixed initial value, timing on fs bits changing after floating point instruction 2022-04-25 19:17:29 +00:00
Kip Macsai-Goren
da29193f9b removed atomic, floating point from privileged tests configs 2022-04-25 19:13:15 +00:00
Kip Macsai-Goren
7ff85258f0 added new tests to tests.vh, comented out until they pass regression 2022-04-25 18:22:44 +00:00
Kip Macsai-Goren
7fe33b2147 Lowered WFI timeout wait time for privileged configs 2022-04-25 17:47:10 +00:00
David Harris
cf1fde62fb Restored MPRV behavior per spec 2022-04-25 14:52:18 +00:00
David Harris
0ede295e88 Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields 2022-04-25 14:49:00 +00:00
David Harris
851d5e8c5e Added MTINST hardwired to 0, and added timeout of U-mode WFI 2022-04-24 20:00:02 +00:00
David Harris
16ad1e0cab Fixed InstrMisalignedFaultM mtval 2022-04-24 17:31:30 +00:00
David Harris
f1ddbb169c Improved priority order and mtval of traps to match spec 2022-04-24 17:24:45 +00:00
David Harris
03f84bf11c Extended sim time to fully boot Linux. Added comments to hazard unit 2022-04-24 13:51:00 +00:00
Kip Macsai-Goren
7bc6943527 Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address) 2022-04-22 22:46:11 +00:00
bbracker
5e76c83309 deprecate unused LINUX_FIX_READ macro 2022-04-21 19:14:47 -07:00
bbracker
afc38abe08 change how tristate I/O is spoofed in GPIO loopback test 2022-04-21 10:31:16 -07:00
Ross Thompson
8fcd4d47b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-21 09:52:42 -05:00
Ross Thompson
165a36acac Modified wally-pipelined.do for no trace linux sim. 2022-04-21 09:52:33 -05:00
David Harris
5c607f2b6b Simplified profile for UART boot; added warnings on UART Rx errors 2022-04-21 04:54:45 +00:00
Kip Macsai-Goren
cd53163d9a added new tests to tests.vh 2022-04-20 17:34:40 +00:00
Kip Macsai-Goren
080963c381 fixed rv32ia to support clint and GPIO for priv tests 2022-04-20 17:31:34 +00:00
Kip Macsai-Goren
510021af65 added working general trap tests to regression 2022-04-20 06:48:01 +00:00
Ross Thompson
546ef08eb2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-19 14:09:50 -05:00
David Harris
1f7a95637a Added baby torture tests 2022-04-19 15:13:06 +00:00
David Harris
a8ad7be246 Fixed WFI decoding in IFU 2022-04-18 19:02:08 +00:00
Kip Macsai-Goren
1ba328324b Added GPIO loopback to let outputs cause interrupts 2022-04-18 07:22:49 +00:00
Kip Macsai-Goren
64698aa806 Added working trap test to regression, fixed hanfling of some interrupts 2022-04-18 07:22:16 +00:00
Shreya Sanghai
fd3920b217 replaced k with bpred size 2022-04-18 04:21:03 +00:00
Shreya Sanghai
c3164f0ce1 added bpred size to wally config 2022-04-18 04:21:03 +00:00
David Harris
462158ea92 LSU name cleanup 2022-04-18 03:18:38 +00:00
Ross Thompson
a99466a487 Fixed bug I introduced by csrc cleanup and changes to ILA. 2022-04-17 21:45:46 -05:00
David Harris
4a7effaf9e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-18 01:30:11 +00:00
David Harris
2882460c94 Renamed FinalAMOWriteDataM to AMOWriteDataM 2022-04-18 01:30:03 +00:00
David Harris
861fbd698b Run 4M instructions in buildroot test to get through kernel & VirtMem startup 2022-04-18 01:29:38 +00:00
Ross Thompson
c045e3afd8 Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
Ross Thompson
c409bde6ae fixed no forcing bug in linux testbench. 2022-04-17 17:49:51 -05:00
David Harris
2819a1c305 Remvoed bytemask anding from FinalWriteDataM in subwordwrite 2022-04-17 22:33:25 +00:00
David Harris
812b56acc6 Prefix comparator cleanup 2022-04-17 21:53:11 +00:00
David Harris
de5b61291f Experiments with prefix comparator; minor fixes in WFI and testbench warnings 2022-04-17 21:43:12 +00:00
Kip Macsai-Goren
1f9c987efe added new tests to makefrag and tests.vh 2022-04-17 21:00:36 +00:00
Ross Thompson
059c04e2a8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-17 15:23:46 -05:00
Ross Thompson
c16dec88de Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
David Harris
2436534687 First implementation of WFI timeout wait 2022-04-17 17:20:35 +00:00
David Harris
83d283354c Added comments in fcvt 2022-04-17 16:53:10 +00:00
David Harris
aa1bac361d Simplified SLT logic 2022-04-17 16:49:51 +00:00
Ross Thompson
238cc9f9fd Commented output power analysis to speed simulation. 2022-04-16 15:32:59 -05:00
Ross Thompson
16b3c64234 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-16 14:59:03 -05:00
Ross Thompson
b9a19304db Fixed possible bugs in LRSC. 2022-04-16 14:45:31 -05:00
David Harris
68d9c99fba Added WFI support to IFU to keep it in the pipeline 2022-04-14 17:26:17 +00:00
David Harris
a28831b83e Added WFI to the testbench instruction name decoder 2022-04-14 17:12:11 +00:00
David Harris
855d68afde WFI should set EPC to PC+4 2022-04-14 17:05:22 +00:00
bbracker
fe53dd1683 fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM 2022-04-14 09:23:21 -07:00
bbracker
eb21e34000 fix ReadDataM forcing 2022-04-13 15:32:00 -07:00
Ross Thompson
2e8afd071e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 13:39:47 -05:00
bbracker
5de92af0b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 05:35:56 -07:00
bbracker
735c75af55 change interrupt spoofing to happen at negative clock edges 2022-04-13 04:31:23 -07:00
bbracker
52ed99ca1b improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS 2022-04-13 03:37:53 -07:00
bbracker
03f1c01f14 whoops forgot to update AttemptedInstructionCount in interrupt spoofing 2022-04-13 00:49:37 -07:00
bbracker
d3e9703c19 change testbench-linux to by default use attempted instruction count for warning/error messages 2022-04-12 21:22:08 -07:00
Ross Thompson
bb6f1cf816 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 19:38:04 -05:00
Ross Thompson
fc173a7954 Missed the force on uart for no tracking. 2022-04-12 19:37:44 -05:00
Ross Thompson
ff826fdb02 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 17:56:48 -05:00
Ross Thompson
7d0462dc59 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
ab9738d3be Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
Ross Thompson
02d6829f8e Found the complex TrapM giving back the wrong instruction bug. 
As I was reviewing the busfsm I found a typo.

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

It should be

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event.  Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into.   The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation.  IgnoreRequest is is high if there is a TrapM | ITLBMissF.  Without the & ~IgnoreRequest the invalid address translation makes the request.
 2022-04-11 13:07:52 -05:00
Ross Thompson
f995ec2a54 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-10 13:41:27 -05:00
Ross Thompson
c3d9eafe60 Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing. 2022-04-10 13:27:54 -05:00
bbracker
aa71fe542d upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs 2022-04-08 13:45:27 -07:00
bbracker
3b6cb5f0ba small signs of life on new interrupt spoofing 2022-04-08 12:32:30 -07:00
Ross Thompson
2294cbc1c6 Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction. 2022-04-07 16:56:28 -05:00
Ross Thompson
5e4682fb65 Fixed typo in tests.vh 2022-04-07 16:28:28 -05:00
Katherine Parry
c307cff503 fixed errors and warnings in rv32e 2022-04-07 17:21:20 +00:00
Kip Macsai-Goren
7425c49f58 updated test signature locations 2022-04-06 07:28:38 +00:00
Kip Macsai-Goren
c82667653c Added missing ZFH macro to new configs 2022-04-06 07:13:51 +00:00
David Harris
c4f5b3fd7c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-05 23:23:47 +00:00
David Harris
c22d6f2848 Added bootmem source ccode 2022-04-05 23:22:53 +00:00
Ross Thompson
9517fe9faf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-05 15:42:07 -05:00
Ross Thompson
7abde2b566 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Katherine Parry
20885f4dea generating all testfloat vectors 2022-04-04 17:17:12 +00:00
Ross Thompson
0ed34b8e63 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-04 10:56:10 -05:00
Ross Thompson
64846c800e Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
0806d1a134 Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash. 2022-04-04 10:38:37 -05:00
Ross Thompson
d83db2cde5 Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
Ross Thompson
fd9a33e453 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-03 17:56:55 -05:00
Ross Thompson
e7abcd862f fpga simulation works again. 2022-04-03 17:31:07 -05:00
David Harris
6966554ee8 Fixed bug with CSRRS/CSRRC for MIP/SIP 2022-04-03 20:18:25 +00:00
Ross Thompson
d135866098 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-02 16:39:54 -05:00
Ross Thompson
5ef6cde52e Added more ILA signals. 2022-04-02 16:39:45 -05:00
Kip Macsai-Goren
cdea062287 added RV64IA config to have a config without compressed instructions 2022-04-02 18:24:08 +00:00
Ross Thompson
987236e463 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 17:18:25 -05:00
Ross Thompson
57eba4355e Updated the fpga test bench. 2022-04-01 17:14:47 -05:00
Ross Thompson
f58a1eff9e Fixed linting issues. 2022-04-01 15:20:45 -05:00
Ross Thompson
178ecaa451 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 12:50:34 -05:00
Ross Thompson
0340c0fd44 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
bbracker
cbff9a7755 expand WALLY-PERIPH test to use SEIP on PLIC context 1 2022-03-31 18:02:06 -07:00
bbracker
36c30b14c1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 17:54:43 -07:00
bbracker
e60139d3ee fix lingering overrun error bug 2022-03-31 17:54:32 -07:00
Ross Thompson
cb945a6a6a Added PLIC to ILA. 2022-03-31 16:44:49 -05:00
Ross Thompson
1586f893b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 16:30:55 -05:00
Ross Thompson
7e05935348 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 15:50:04 -05:00
Ross Thompson
e81f317764 Notes on what to change in ram.sv. 2022-03-31 15:48:15 -05:00
bbracker
d32e1147bf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 13:46:32 -07:00
bbracker
34c94f150e simplify plic logic 2022-03-31 13:46:24 -07:00
David Harris
2ed1c9f14f Added SystemVerilog flag to fma.do so that fma16 compiles properly 2022-03-31 17:00:38 +00:00
Ross Thompson
fb0eec0f76 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:39:41 -05:00
Ross Thompson
0942429b7f Forced to go back to hard coded preload. 2022-03-31 11:39:37 -05:00
Ross Thompson
a6d090a7c0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:38:55 -05:00
Ross Thompson
dc48d84dd6 Modified clint to support all byte write sizes. 2022-03-31 11:31:52 -05:00
David Harris
93d6b2fb62 Added synthesis script for fma16 2022-03-31 00:51:33 +00:00
David Harris
f917ed7ed0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 23:06:36 +00:00
bbracker
54b9745a75 big interrupts refactor 2022-03-30 13:22:41 -07:00
Ross Thompson
b2a77da96b Changed sram1p1rw to have the same type of bytewrite enables as bram. 2022-03-30 11:38:25 -05:00
David Harris
44f94173bf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:26:27 +00:00
David Harris
1f10a96aa2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:13:42 +00:00
Ross Thompson
3ac736e2d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-30 11:09:44 -05:00
Ross Thompson
370a075fa1 Partial cleanup of memories. 2022-03-30 11:09:21 -05:00
Ross Thompson
1993069986 Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload. 2022-03-30 11:04:15 -05:00
Ross Thompson
fc2b4453ec rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory. 2022-03-29 23:48:19 -05:00
Ross Thompson
de2672231d Partial fix to allow byte write enables with fpga and still get a preload to work. 2022-03-29 19:12:29 -05:00
Kip Macsai-Goren
b252122d62 fixed arch bge test signature output location after update 2022-03-29 20:45:18 +00:00
David Harris
057ee56d7e Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv 2022-03-29 19:16:41 +00:00
David Harris
049c55769a fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
Kip Macsai-Goren
ad106e7130 made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes 2022-03-29 02:26:42 +00:00
Kip Macsai-Goren
c32f5e9cee fixed signature location of the new periph with no compressed instructions 2022-03-29 02:15:17 +00:00
bbracker
46ffa4b079 fix typo that Madeleine found 2022-03-28 15:39:29 -07:00
Kip Macsai-Goren
dc9635b757 fixed double multiplication on vectored interrupts 2022-03-28 19:12:31 +00:00
Kip Macsai-Goren
2e68ab7bb4 added test config that doesn't use compressed instructions for privileged tests 2022-03-28 19:12:31 +00:00
Skylar Litz
29d1f64588 add AtemptedInstructionCount signal 2022-03-26 21:28:57 +00:00
Skylar Litz
bb8587e06f update to match new filesystem organization 2022-03-26 21:28:32 +00:00
Kip Macsai-Goren
8cde06b886 added basic trap tests that do not pass regression yet. updated signature adresses 2022-03-25 22:57:41 +00:00
Ross Thompson
7099259ff7 I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit. 2022-03-25 13:10:31 -05:00
Ross Thompson
7a824eaae1 Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB. 2022-03-24 23:47:28 -05:00
bbracker
b08066381a fix multiple-context PLIC checkpoint generation 2022-03-25 01:02:22 +00:00
bbracker
150a7b234b tabs vs spaces disagreement 2022-03-24 17:11:41 -07:00
bbracker
9f60256f22 1st attempt at multiple channel PLIC 2022-03-24 17:08:10 -07:00
Ross Thompson
58668812c1 Moved WriteDataM register into LSU. 2022-03-23 14:17:59 -05:00
Ross Thompson
07b7dbc922 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-23 14:10:38 -05:00
Katherine Parry
abdbc31d14 fixed typo in unpack.sv 2022-03-23 18:26:59 +00:00
Ross Thompson
f1787670d4 Cleanup in testbench-linux.sv. 2022-03-22 22:34:38 -05:00
Ross Thompson
6c9750c725 reverted temporary change to configs. 2022-03-22 22:31:34 -05:00
Katherine Parry
ead88fba55 fixed lint error in fpudivsqrtrecur.sv 2022-03-23 03:24:41 +00:00
Ross Thompson
6ab14d7302 Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing. 2022-03-22 22:04:06 -05:00
Ross Thompson
600a97982f Reverted change to configuration which caused issue with lint. 2022-03-22 21:44:08 -05:00
Ross Thompson
c5be2cb1d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-22 21:28:50 -05:00
Ross Thompson
7fc128ba7c added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP. 2022-03-22 21:28:34 -05:00
Katherine Parry
c3c764a171 unpack.sv cleanup 2022-03-23 01:53:37 +00:00
Ross Thompson
80d376877a Added spoof of uart addresses +0x2 and +0x6. 2022-03-22 16:52:27 -05:00
Ross Thompson
cec7625d91 Added comment about needed fix to misaligned fault. 2022-03-22 16:52:07 -05:00
Katherine Parry
2042374102 FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
Ross Thompson
d347de8c49 dtim writes are supressed on non cacheable operation. 2022-03-12 00:46:11 -06:00
Ross Thompson
d8947fa616 cleanup of ram.sv 2022-03-11 18:09:22 -06:00
Ross Thompson
d68446cf92 Added new asserts to testbench. 2022-03-11 15:41:53 -06:00
Ross Thompson
e802deb4d6 Can now support the following memory and bus configurations. 
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
 2022-03-11 15:18:56 -06:00
Ross Thompson
3dbf6790e1 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Ross Thompson
81a2fbb6d2 mild cleanup. 2022-03-11 13:05:47 -06:00
Ross Thompson
11e5aad38a Moved subcachelineread inside the cache. There is some ugliness to still resolve. 2022-03-11 12:44:04 -06:00
Ross Thompson
a12016e69b Moved subcacheline read inside the cache. 2022-03-11 11:03:36 -06:00
Ross Thompson
326ecda060 removed unused parameter. 2022-03-11 10:43:54 -06:00
Ross Thompson
04dd2f0eb5 atomic cleanup. 2022-03-10 18:56:37 -06:00
Ross Thompson
a598760445 Name changes. 2022-03-10 18:50:03 -06:00
Ross Thompson
bdfca503fa Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
5c16b65a16 simplified uncore's name for HWDATA. 2022-03-10 18:17:44 -06:00
Ross Thompson
543e10ab32 Moved subwordwrite to lsu directory. 2022-03-10 18:15:25 -06:00
Ross Thompson
54abd944e2 Simplified byte write enable logic. 2022-03-10 18:13:35 -06:00
Ross Thompson
50789f9ddd Byte write enables are passing all configs now. 2022-03-10 17:26:32 -06:00
Ross Thompson
f7df3a0666 Progress on the path to getting all configs working with byte write enables. 2022-03-10 17:02:52 -06:00
Ross Thompson
83133f8c47 Partially working byte write enables. Works for cache, but not dtim or bus only. 2022-03-10 16:11:39 -06:00
Ross Thompson
d5f524a15e Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
David Harris
b1340653cf bit write update 2022-03-09 19:09:20 +00:00
David Harris
004853c312 Refactored SRAM bit write enable 2022-03-09 17:49:28 +00:00
David Harris
ba9320d822 Updated testbench to read expected flags 2022-03-09 13:58:17 +00:00
Ross Thompson
2a8a1cd191 Minor cleanup to interlockfsm. 2022-03-08 23:38:58 -06:00
Ross Thompson
ac9528b450 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-08 18:05:35 -06:00
Ross Thompson
ed32801cc1 Comments. 2022-03-08 18:05:25 -06:00
Ross Thompson
534fd70f76 Marked signals for name changes. 2022-03-08 17:41:02 -06:00
David Harris
5d0b9bab6e Added more test cases and rounding modes to fma test generator 2022-03-08 23:29:29 +00:00
David Harris
582b943380 fixed setup.sh merge conflict 2022-03-08 23:21:06 +00:00
David Harris
cfa82efccc fma16_testgen.c test cases 2022-03-08 23:18:18 +00:00
Ross Thompson
acd60218b8 Removed unused signal. 2022-03-08 16:58:26 -06:00
Ross Thompson
cc21414051 Added parameter to spillsupport. 2022-03-08 16:38:48 -06:00
Ross Thompson
60e6c1ffa7 Moved cacheable signal into cache. 2022-03-08 16:34:02 -06:00
bbracker
51e68819c4 fix up PLIC and UART checkpointing 2022-03-07 23:48:47 -08:00
bbracker
c2ac18b5de change testbench-linux.sv to use new shared location of disassembly files 2022-03-07 20:04:08 -08:00
David Harris
d2282d5e87 Checked in fma16_template.v 2022-03-06 13:29:35 +00:00
David Harris
9fd861a9ee removed more old 64priv tests 2022-03-04 03:57:19 +00:00
bbracker
51f1a411dd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:12:00 +00:00
bbracker
1c5697874f comment out nonfunctioning CSR-PERMISSIONS-M test 2022-03-04 00:11:55 +00:00
David Harris
63e9d846e4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:07:34 +00:00
David Harris
48705457d5 LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
bbracker
efb5d1dbc0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:06:27 +00:00
bbracker
443dd40ea8 remove imperas32p tests 2022-03-04 00:06:18 +00:00
David Harris
545f569f78 Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas 2022-03-03 15:38:08 +00:00
David Harris
080fef6436 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-02 23:47:16 +00:00
David Harris
8fbdbba81a fma file fixes 2022-03-02 23:47:01 +00:00
bbracker
e28ca531e0 fix peripheral test and add it to regression 2022-03-02 23:44:39 +00:00
bbracker
be2f668867 but apparently QEMU doesn't show UXL in SSTATUS 2022-03-02 22:44:19 +00:00
bbracker
01e0f2f0d2 update SXL UXL bits in MSTATUS to match new QEMU trace 2022-03-02 22:15:57 +00:00
bbracker
c1290d493f add CSRs to waveview 2022-03-02 18:31:10 +00:00
bbracker
d7b8c9d877 add rv32a tests to regression 2022-03-02 17:54:55 +00:00
bbracker
6c422cd357 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-02 17:46:40 +00:00
David Harris
3bea7bb431 removed imperas-riscv-tests 2022-03-02 17:28:20 +00:00
bbracker
5f5cc514b8 fix buildroot checkpointing and add it back to regression 2022-03-02 16:00:19 +00:00
bbracker
4f22a55dd4 add LRSC test and add wally64a to regression 2022-03-02 07:09:37 +00:00
David Harris
1661983345 FMA project ready to start 2022-03-01 20:58:08 +00:00
bbracker
41b3912abc buildroot graphical sim bugfix 2022-03-01 03:24:23 +00:00
bbracker
04ace8c154 switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv 2022-03-01 03:11:43 +00:00
bbracker
d620fb4442 deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test 2022-03-01 00:37:46 +00:00
David Harris
f314e60dc8 Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath 2022-02-28 20:50:51 +00:00
David Harris
f0a7ae2bba adrdecs comments 2022-02-28 20:33:41 +00:00
David Harris
e108eb5195 Modified address decoder for native access to CLINT 2022-02-28 19:13:14 +00:00
David Harris
3519a20ccf hptw cleanup for synthesis 2022-02-28 05:54:34 +00:00
David Harris
bb14dba9be Created softfloat_demo showcasing how to do math with SoftFloat 2022-02-27 18:17:21 +00:00
David Harris
046259cff8 Moved regression work directories to regression/wkdir to reduce clutter 2022-02-27 17:35:09 +00:00
David Harris
c7b5d32a72 Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior 2022-02-27 17:23:33 +00:00
David Harris
c6561d1e8b Moved FMA back into source tree to facilitate synthesis 2022-02-27 15:41:41 +00:00
David Harris
eb0bbacd43 Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue 2022-02-27 15:12:10 +00:00
David Harris
274ecf13ad Moved fma directory 2022-02-27 14:20:15 +00:00
David Harris
5a5142c14f fma simulation infrastructure 2022-02-27 04:36:43 +00:00
David Harris
d917cc1379 fma passing multiply vectors 2022-02-27 04:36:01 +00:00
David Harris
8a55935456 simplified fma Makefile 2022-02-26 19:55:42 +00:00
David Harris
1852eccaab Made softfloat.a a symlink 2022-02-26 19:53:04 +00:00
David Harris
87d1a8a1ac Added start of fma 2022-02-26 19:51:19 +00:00
David Harris
eda60a7691 Moved Softfloat / TestFloat 2022-02-26 19:17:32 +00:00
Ross Thompson
97d64201f7 Fixed bug with DAPageFault being wrong when HPTW writes not supported. 2022-02-23 10:54:34 -06:00
Ross Thompson
53f13d4cbc More spillsupport more structual. 2022-02-23 10:27:14 -06:00
Ross Thompson
c23f6c7d90 Fixed bug with spill support and Instruction DA Page Faults. 2022-02-23 10:16:12 -06:00
Ross Thompson
62e1a97287 Added generates to pcnextf muxes for privileged and caches. 2022-02-22 22:45:00 -06:00
Ross Thompson
d331b9f29d Fixed "bug" with wally-pipelined.do 2022-02-22 22:19:25 -06:00
Ross Thompson
6a52f95cc8 Minor busdp cleanup. 2022-02-22 17:28:26 -06:00
Ross Thompson
59a2c09c5e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-22 14:45:53 -06:00
Ross Thompson
90be3d4360 Clarified interlockfsm. 2022-02-22 11:31:28 -06:00
bbracker
b8fd06576c fix lint bugs in PLIC and UART 2022-02-22 05:04:18 +00:00
bbracker
a6047697c3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-22 04:27:50 +00:00
bbracker
6caa97bb26 change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests 2022-02-22 03:46:08 +00:00
bbracker
e7934c585a change RX side of UART to aslo be LSB-first 2022-02-22 03:34:08 +00:00
Ross Thompson
3a29504279 Added some clearity to lsuvirtmem.sv. 2022-02-21 17:20:58 -06:00
Ross Thompson
ca59778c5a Annotated IFU for mux changes. 2022-02-21 17:20:34 -06:00
Ross Thompson
2f711fb642 Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW. 2022-02-21 16:54:38 -06:00
Ross Thompson
0c65ea96d8 Cleaned up names in lsuvirtmem. 2022-02-21 16:44:30 -06:00
Ross Thompson
a6e83a2ca2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-21 12:46:22 -06:00
Ross Thompson
56fc6d0d7c Minor cleanup of lsu. 2022-02-21 12:46:06 -06:00
ushakya22
67780305ae Moved order of reading a, b, and result from test vectors file so that result 
matches up with inputs a and b
 2022-02-21 17:28:11 +00:00
ushakya22
88060a74f5 - created new testbench file instead of having it at the bottom of the srt file 
- uses unpacker to parse 64 bit floating point numbers
- updated testbench to read from new testvectors generated by exptestbench

Notes:
MEM_WIDTH updated to be 64*3
Input numbers and output result is 64 bit number
MEM_SIZE set to 60000
 2022-02-21 16:24:50 +00:00
ushakya22
d1089163a9 - Created exponent divsion module 
- top module includes exponent module now

Notes:
- may be a better implementation of the exponent module rather than
having what I believe are two adders currently
 2022-02-21 16:13:30 +00:00
ushakya22
c6bd51a707 Changed Makefile to compile exptestgen instead of testgen 2022-02-21 16:08:45 +00:00
ushakya22
08d997d68b reverted srt_standford back to original file pre modifications by Udeema 2022-02-21 16:08:09 +00:00
ushakya22
1495f6ac70 verilator lint for srt 2022-02-21 16:05:43 +00:00
ushakya22
5b83ad0929 Created test vector generation file for exponent and mantissa division 2022-02-21 16:04:41 +00:00
Ross Thompson
f48b12b089 Moved mux into lsuvirtmem. 2022-02-21 09:31:29 -06:00
Ross Thompson
cbf4395457 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-21 09:06:09 -06:00
Kip Macsai-Goren
d1578d8356 added scratch register tests for 64 and 32 bits 2022-02-21 07:03:12 +00:00
Kip Macsai-Goren
5bdb612567 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-21 00:34:54 +00:00
Ross Thompson
ae06785b9f Minor changes to LSU. 2022-02-19 14:38:17 -06:00
David Harris
20a5798f43 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-18 23:08:47 +00:00
David Harris
6a0ffff05d Removed problematic warning about reaching default state in HPTW 2022-02-18 23:08:40 +00:00
Kip Macsai-Goren
4113d64b19 added 32 bit pma tests to regression even though they've been working fo a while 2022-02-18 19:43:24 +00:00
Kip Macsai-Goren
c3523dfa15 Added misa test for both 32 and 64 bits 2022-02-18 19:41:50 +00:00
Ross Thompson
6cd9d84e7f New config option to enable hptw writes to PTE in memory to update Access and Dirty bits. 2022-02-17 17:19:41 -06:00
Ross Thompson
ad237b3ce5 Accidentally cleared dirty bit when setting access bit in hptw. 2022-02-17 16:20:20 -06:00
Ross Thompson
cbac34943c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-17 14:49:37 -06:00
Ross Thompson
0eec096474 Rough implementation passing regression test with hptw atomic writes to memory. 2022-02-17 14:46:11 -06:00
David Harris
f3c7025ade Started make allsynth to try many experiments 2022-02-17 17:57:02 +00:00
Ross Thompson
2fc7dc3e57 Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB. 2022-02-17 10:04:18 -06:00
Ross Thompson
62f5f1e622 Broken state. address translation not working after changes to hptw to support atomic updates to PT. 2022-02-16 23:37:36 -06:00
Ross Thompson
eafd52e2bc Added additional suppresses to vsim command incase buildroot files are missing. 2022-02-16 17:05:54 -06:00
Ross Thompson
c9e33208e3 Moved a few muxes around after sww changes. 2022-02-16 15:43:03 -06:00
Ross Thompson
71ed49bf2b cleanup of signal names. 2022-02-16 15:29:08 -06:00
Ross Thompson
6dc12b4968 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-16 15:22:35 -06:00
Ross Thompson
27042f028e Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path. 2022-02-16 15:22:19 -06:00
David Harris
c23db6a31e Cleaned warning on HPTW default state 2022-02-16 17:40:13 +00:00
David Harris
01fa5c94bd Register file comments about reset 2022-02-16 17:21:05 +00:00
Ross Thompson
c56c4db47f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-16 09:48:16 -06:00
Skylar Litz
0c69d3291d update bugfinder script to new file organization 2022-02-15 22:58:18 +00:00
Kip Macsai-Goren
6c1383e2a0 added CSR permission and minfor to 32 bit tests 2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
5df0a9531f merged test macros in with 32 bit tests 2022-02-15 20:19:14 +00:00
David Harris
aa990be959 removed csrn and all of its outputs because depricated 2022-02-15 19:59:29 +00:00
David Harris
d8170e9dd3 Mostly removed N_SUPPORTED 2022-02-15 19:50:44 +00:00
David Harris
ed8ac3d881 Just needed to recompile - all good. Now removed uretM because N-mode is depricated 2022-02-15 19:48:49 +00:00
David Harris
5ef8f6bc7e Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change. 2022-02-15 19:20:41 +00:00
Kip Macsai-Goren
9266bc382e light cleanup for privileged tests 2022-02-15 17:06:16 +00:00
Ross Thompson
fcbb577f31 Cache mods to be consistant with diagrams. 2022-02-14 12:40:51 -06:00
David Harris
143eb0ae65 srt fixes 2022-02-14 18:40:27 +00:00
David Harris
3598e05998 srt batch files 2022-02-14 18:37:46 +00:00
ushakya22
3e2e9bc6a0 bring branch back into main 
Merge branch 'srt_division_with_unpacker' into main
 2022-02-14 18:25:34 +00:00
ushakya22
df561f8550 work in progress exponent handling 2022-02-14 18:24:29 +00:00
David Harris
caa4d83e57 t push 
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
 2022-02-14 01:22:22 +00:00
Ross Thompson
86e117ea77 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-13 18:21:15 -06:00
Ross Thompson
6e1a0af5d0 Eliminated more ports in cacheway. 2022-02-13 15:53:46 -06:00
Ross Thompson
a440bc2ac5 More cache cleanup. 2022-02-13 15:47:27 -06:00
Ross Thompson
1e7e59bdbd Changed names of signals in cache. 2022-02-13 15:06:18 -06:00
Ross Thompson
f87a6f2c63 More cache cleanup. 2022-02-13 12:38:39 -06:00
ushakya22
a996a5e16c Added unpacker into testbench for srt 2022-02-12 22:05:18 +00:00
David Harris
f5678e25db Synthesis cleanup 2022-02-12 06:25:12 +00:00
David Harris
b537df2651 Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0 2022-02-12 05:50:34 +00:00
Ross Thompson
f5c4bca47e Formating improvements to cache. 2022-02-11 23:10:58 -06:00
Ross Thompson
6fa9490d0b More cache simplifications. 2022-02-11 22:54:05 -06:00
Ross Thompson
ae2011eb07 Reduced seladr to 1 bit as second bit is same as selflush. 2022-02-11 22:41:36 -06:00
Ross Thompson
cb3d71a63d Reduced complexity of the address selection during flush. 2022-02-11 22:27:27 -06:00
Ross Thompson
a0ee2f3d99 Removed redundant signals from cache. 2022-02-11 22:23:47 -06:00
Ross Thompson
aa04778d0b Cache fsm simplifications. 2022-02-11 15:16:45 -06:00
Ross Thompson
e6c8cfd49b Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY. 2022-02-11 15:09:00 -06:00
Ross Thompson
83adacbee3 Simplified cache fsm. 2022-02-11 14:54:57 -06:00
Ross Thompson
c8e6884926 Fixed bug. 
It was possible for DTLBMissM to prevent a dcache flush.
 2022-02-11 14:00:01 -06:00
Ross Thompson
b1cba4be2b Updates to linux wave. 2022-02-11 13:28:18 -06:00
Ross Thompson
9145a96b53 Updated linux wave. 2022-02-11 13:15:42 -06:00
Ross Thompson
3f4ae91468 linux wave cleanup. 2022-02-11 10:48:45 -06:00
Ross Thompson
20456097cd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-11 10:47:21 -06:00
Ross Thompson
2f2a4f4500 Fixed subtle and infrequenct bug. 
Loading buildroot at 483M instructions started with a spill + ITLBMiss.  The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation.  However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation.  Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
 2022-02-11 10:46:06 -06:00
David Harris
15fb7fee60 Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
Ross Thompson
fc6dc52618 Fixed bugs in ifu spills and missing reset on bus data register. 2022-02-10 18:11:57 -06:00
Ross Thompson
9ad4523b9d Updated wave files to reflect recent changes. 2022-02-10 17:52:19 -06:00
Ross Thompson
f23817bf69 Replacement policy cleanup. 2022-02-10 11:42:40 -06:00
Ross Thompson
411997010b Replacement policy cleanup. 2022-02-10 11:40:10 -06:00
Ross Thompson
382d5fab0f Cleanup. 2022-02-10 11:27:15 -06:00
Ross Thompson
3a0af5d9e9 Cleanup + critical path optimizations. 2022-02-10 11:11:16 -06:00
Ross Thompson
fc68c2f09a Cache name clarifications. 2022-02-10 10:50:17 -06:00
Ross Thompson
e00d404154 More cache cleanup. 2022-02-10 10:43:37 -06:00
Ross Thompson
65803ebe98 structural muxes. 2022-02-09 19:36:21 -06:00
Ross Thompson
2a989e6d05 More cache cleanup. 2022-02-09 19:29:15 -06:00
Ross Thompson
3b8ad3f7c7 Cleaned up comments. 2022-02-09 19:21:35 -06:00
Ross Thompson
911ee36b22 Removed all possilbe paths to PreSelAdr from TrapM. 2022-02-09 19:20:10 -06:00
Ross Thompson
327a05c9d8 Added commented out commands to generate saif file from vsim. 2022-02-09 18:40:45 -06:00
Ross Thompson
01126535db Annotated the final changes required to move sram address off the critial path. 2022-02-08 18:17:31 -06:00
Ross Thompson
7133e790ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 17:52:15 -06:00
Ross Thompson
498388c636 Cache cleanup write enables. 2022-02-08 17:52:09 -06:00
Ross Thompson
8a49ec90d0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 15:43:18 -06:00
Ross Thompson
e0a605e95d Cleanup IFU. 2022-02-08 14:54:53 -06:00
Ross Thompson
d1d014bf1d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:47:15 -06:00
Ross Thompson
13561c67bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:22:19 -06:00
Ross Thompson
cecbb3362d rv32e works for now. Still need to optimize. 2022-02-08 14:21:55 -06:00
Ross Thompson
39149c618f Moved some muxes back into the bp. 2022-02-08 14:17:44 -06:00
David Harris
3e16730226 RAM simplification 2022-02-08 20:15:23 +00:00
Ross Thompson
d5d9bb9d4d Temporary commit which gets the no branch predictor implementation working. 2022-02-08 14:13:55 -06:00
David Harris
c07584bb70 rv32e config update 2022-02-08 17:59:50 +00:00
Ross Thompson
c2377eaaf4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 11:36:30 -06:00
Ross Thompson
3cd067ac6a Finished merge. 2022-02-08 11:36:24 -06:00
David Harris
9ad3f26365 Restored E tests to makefrag 2022-02-08 16:41:11 +00:00
Ross Thompson
492c1473f3 Preparing to make a major change to the cache's write enables. 2022-02-08 09:47:01 -06:00
David Harris
e5097e67d4 Fixed TIM tests; rv32e test still failing 2022-02-08 15:24:37 +00:00
David Harris
e9a519a228 Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail 2022-02-08 12:40:02 +00:00
David Harris
096242a6d8 Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
David Harris
72c2166223 Lab 3 file cleanup 2022-02-08 10:26:37 +00:00
Ross Thompson
190d619940 cachefsm cleanup. 2022-02-07 22:09:56 -06:00
Ross Thompson
ca459a5915 Removed VDWriteEnable. 2022-02-07 21:59:18 -06:00
Ross Thompson
494802b2e1 more partial cleanup of fsm and write enables. 2022-02-07 17:41:56 -06:00
Ross Thompson
23a60d9875 Progress towards simplifying the cache's write enables. 2022-02-07 17:23:09 -06:00
Ross Thompson
fcd43ea004 more cleanup. 2022-02-07 13:29:19 -06:00
Ross Thompson
e72d54ea98 More cachefsm cleanup. 2022-02-07 13:19:37 -06:00
Ross Thompson
a6a7779ec0 More cachefsm cleanup. 2022-02-07 12:30:27 -06:00
Ross Thompson
7f732eb571 More cachefsm cleanup. 2022-02-07 11:16:20 -06:00
Ross Thompson
be67c4d559 More cachefsm cleanup. 2022-02-07 11:12:28 -06:00
Ross Thompson
f1781c6bc8 More cachefsm cleanup. 2022-02-07 10:54:22 -06:00
Ross Thompson
b89ce18473 Cache cleanup. 2022-02-07 10:43:58 -06:00
Ross Thompson
6f4a321d31 More cachfsm cleanup. 2022-02-07 10:33:50 -06:00
David Harris
60c3cdad3a Reverted cache change 2022-02-07 14:47:20 +00:00
David Harris
d0c40cca7a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-07 14:43:31 +00:00
David Harris
c21eb67a07 Cache syntax cleanup 2022-02-07 14:43:24 +00:00
Ross Thompson
8bcaadda6b More cachefsm cleanup. 2022-02-06 21:50:44 -06:00
Ross Thompson
347e9228f8 started cachefsm cleanup. 2022-02-06 21:39:38 -06:00
Kip Macsai-Goren
38b75e85a0 added new tests to make and testbench 2022-02-06 19:47:22 +00:00
David Harris
0feb624bab Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
bbracker
27dd363a85 remove sporadic tabs from tests.vh so that it is now only spaces 2022-02-05 23:07:38 +00:00
bbracker
fc2e3d1fbf remove rv32e from regression because it is broken; goes with previous commit 2022-02-05 23:05:21 +00:00
Ross Thompson
308cc34d6f Added config to allow using the save/restore or replay implementation to handle sram clocked read delay. 2022-02-04 23:49:07 -06:00
David Harris
0dd8c719ad Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit 2022-02-05 05:35:51 +00:00
David Harris
f7d6939d9b Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts 2022-02-05 05:28:40 +00:00
David Harris
581fbb7d13 Modified wally-pipelined-batch.do to handle buildroot 2022-02-05 05:07:07 +00:00
Ross Thompson
1766c0f5ba Removed unused ports from caches and buses. 2022-02-04 22:52:51 -06:00
Ross Thompson
dce4f8a0e5 Cleanup. 2022-02-04 22:40:51 -06:00
Ross Thompson
53551ab533 Moved the hwdata mux back into the busdp. 2022-02-04 22:39:13 -06:00
Ross Thompson
34cf77797a Merged together the two sub cache line read muxes. 
One mux was used for loads and the other for eviction.
 2022-02-04 22:30:04 -06:00
David Harris
23868a33bc Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests. 2022-02-05 04:16:18 +00:00
Ross Thompson
c846368537 Moved the sub cache line read logic to lsu/ifu. 2022-02-04 20:42:53 -06:00
Ross Thompson
f6f0539e10 Got separate module for the sub cache line read. 2022-02-04 20:23:09 -06:00
Ross Thompson
ceb2cc30b9 Second optimization of save/restore. 2022-02-04 14:35:12 -06:00
Ross Thompson
498c2b589a Optimization of cache save/restore. 2022-02-04 14:21:04 -06:00
Ross Thompson
83fdedcec6 Working first cut of the cache changes moving the replay to a save/restore. 
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
 2022-02-04 13:31:32 -06:00
David Harris
16b5fee795 RV32e tests 2022-02-04 14:30:36 +00:00
David Harris
14c1d86953 rv32e 2022-02-04 01:56:30 +00:00
David Harris
1c049f1f67 renamed configs 2022-02-03 23:36:41 +00:00
David Harris
c3122ce214 sram1rw cleanup 2022-02-03 18:03:22 +00:00
David Harris
0e1d784b60 sram1rw cleanup 2022-02-03 17:50:23 +00:00
David Harris
eb8dd5e7d7 cachereplacementpolicy cleanup 2022-02-03 17:19:14 +00:00
David Harris
5f7326368e cachereplacementpolicy cleanup 2022-02-03 17:18:48 +00:00
David Harris
9b6a4d1d52 cacheway cleanup 2022-02-03 16:52:22 +00:00
David Harris
7a8cc5ef21 cacheway cleanup 2022-02-03 16:33:01 +00:00
David Harris
0fbc32204c cacheway cleanup 2022-02-03 16:07:55 +00:00
David Harris
c22f7eb11c cacheway cleanup 2022-02-03 16:00:57 +00:00
David Harris
e92461159d cache cleanup 2022-02-03 15:36:11 +00:00
Ross Thompson
4a5aa43716 Merge branch 'makefiles' into main 2022-02-03 08:33:50 -06:00
Ross Thompson
55382be055 Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the 
regression directory.  Makefile calls the submakefiles for generating elf files.
The second makefile-memfiles generates the memfiles, addr, and label files.
 2022-02-03 08:32:48 -06:00
Ross Thompson
9da3223ce6 Manged to get all the tests compiled and converted to memfiles using new makefiles. 2022-02-03 00:00:15 -06:00
Ross Thompson
41978d59e4 Quick patch to regression-wally to "fix" rv32ic. 2022-02-02 19:24:24 -06:00
Ross Thompson
789cf13be6 broken makefiles. 2022-02-02 19:15:11 -06:00
Ross Thompson
ac19cd48a4 Broken makefiles. 2022-02-02 19:14:42 -06:00
David Harris
9e0055cbb9 More config file cleanup; 32ic tests broken 2022-02-03 01:08:34 +00:00
David Harris
bdf1a8ba73 changed DMEM and IMEM configurations to support BUS/TIM/CACHE 2022-02-03 00:41:09 +00:00
David Harris
172a02551b Removed Busybear and Buildroot Configuration 2022-02-02 20:32:22 +00:00
David Harris
c12407ba6a Removed Busybear dependencies 2022-02-02 20:28:21 +00:00
Ross Thompson
f3c2e426b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-02 11:41:54 -06:00
Ross Thompson
2f7cf2bc7f Fixed testbench so coremark stops. 2022-02-02 11:37:48 -06:00
David Harris
761dae72fe Config file & wally-riscv-arch-test cleanup 2022-02-02 16:35:52 +00:00
Ross Thompson
88a408b3e6 Added helpful signals to wavefile. 
Makefile for tests now creates the function address to name mapping files.
The function name and test name are included in the wave file.
 2022-02-02 10:15:54 -06:00
Ross Thompson
ae36931bb2 Added correct stop condition for coremark. 2022-02-02 09:53:51 -06:00
Ross Thompson
2d8b0aa650 Modified makefiles to generate function address to name mappings for modelsim. 2022-02-01 18:25:03 -06:00
Ross Thompson
058b368a22 Improved function_radix to not printout warnings when no valid function is found. 2022-02-01 18:03:09 -06:00
Ross Thompson
138b17a399 Setup the main regression test to be able to handle coremark. 2022-02-01 17:00:11 -06:00
Ross Thompson
910d16b642 More cleanup of IFU. 2022-02-01 14:32:27 -06:00
Ross Thompson
a9b4f9b1e7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-01 10:50:38 -06:00
Ross Thompson
99bb281944 Updated fpga's bootloader to reflect the changes to the gpio address change. 2022-02-01 10:43:24 -06:00
Ross Thompson
dce9ee12b4 IFU and LSU now share the same busdp module. 2022-01-31 16:25:41 -06:00
Ross Thompson
a04aa283cb partial ifu cleanup. 2022-01-31 16:08:53 -06:00
Ross Thompson
b05abc1795 cleanup. 2022-01-31 13:29:04 -06:00
Ross Thompson
c1311ca56a Fixed modelsim warning with linux simulation. 2022-01-31 12:57:02 -06:00
Ross Thompson
d2ab17e1af Repaired linux-wave.do 2022-01-31 12:54:18 -06:00
Ross Thompson
3475e142a5 Repaired wavefile and fixed modelsim warning. 2022-01-31 12:34:17 -06:00
Ross Thompson
1476a79ea2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-31 12:17:37 -06:00
Ross Thompson
fa8914a830 Cleanup busdp. 2022-01-31 12:17:07 -06:00
Ross Thompson
7c3d6bbdb4 Moved lsu virtual memory logic into separate module. 2022-01-31 11:56:03 -06:00
Ross Thompson
e35a8299ec Encapsulated dtim. 2022-01-31 11:23:55 -06:00
Ross Thompson
dbe40856a2 Removed unused signals in the LSU. 2022-01-31 10:35:35 -06:00
Ross Thompson
bfbc31d184 Moved atomic logic to own module. 2022-01-31 10:28:12 -06:00
Ross Thompson
ef770fd183 Encapsulated the bus data path into a separate module. 2022-01-31 10:15:48 -06:00
Kip Macsai-Goren
1077cf08b0 added machine info test that uses new test library 2022-01-31 05:54:43 +00:00
David Harris
2d112698b7 Replaced || and && with | and & 2022-01-31 01:07:35 +00:00
Ross Thompson
d52c5b0393 LSU and IFU cleanup. 2022-01-28 15:26:06 -06:00
Ross Thompson
de0bef4f5b Updated wave.do to match the ifu/lsu changes. 2022-01-28 14:37:15 -06:00
Ross Thompson
147d71fd46 Clean up of mmu instances in IFU and LSU. 2022-01-28 14:02:05 -06:00
Ross Thompson
4a8d0cb981 Moved spills to own module. 2022-01-28 13:40:35 -06:00
Ross Thompson
7fedc6b878 Cleaned up the InstrMisalignedFault. 2022-01-28 13:19:24 -06:00
Ross Thompson
1bb8d36308 Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
Ross Thompson
d7d7c1cb7d Relocated the misalignment faults. 2022-01-27 16:03:00 -06:00
David Harris
87aa0724a2 IFU cleanup 2022-01-27 17:18:55 +00:00
David Harris
218ff3e25d IFU cleanup 2022-01-27 16:41:57 +00:00
David Harris
1c22077841 Optimized out second adder from IFU for PC+2 2022-01-27 16:06:24 +00:00
David Harris
62e5c7fd13 Comments in LSU code about restructuring 2022-01-27 15:53:59 +00:00
Ross Thompson
9a9dfcae40 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-27 08:45:33 -06:00
Ross Thompson
d38ab9d2d7 Increased number of concurrent tests. 2022-01-27 08:45:25 -06:00
David Harris
975c0e72c8 Set up rv32emc config 2022-01-27 14:37:58 +00:00
Ross Thompson
75c33bc6c9 BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush. 2022-01-27 07:59:59 -06:00
Ross Thompson
b961b104e0 Added colors to regression script to make it easy to pick out success from fail. 2022-01-26 22:40:32 -06:00
Ross Thompson
c3a78553be Removed mux in PCNextF logic. Minor IFU improvements. 2022-01-26 22:33:26 -06:00
Ross Thompson
23c4ba2777 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. 
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
 2022-01-26 18:23:39 -06:00
Ross Thompson
2c982dca03 IFU simplifications. 2022-01-26 13:54:59 -06:00
David Harris
c6adb7b6b1 Updated configs to fix GPIO address to match FU540 2022-01-26 18:16:34 +00:00
David Harris
c60bb68bff Testgen working for Lab 2 2022-01-26 18:01:51 +00:00
Ross Thompson
728e46a794 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-25 19:21:04 -06:00
David Harris
22c84dcd80 simpleram simplification 2022-01-25 19:46:13 +00:00
David Harris
8bf73d0eb3 simpleram simplification 2022-01-25 19:40:07 +00:00
David Harris
f07123ff0f simpleram simplification 2022-01-25 18:26:31 +00:00