mirror of
https://github.com/openhwgroup/cvw
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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commit
0630e2a9a2
@ -2,7 +2,7 @@
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// srt.sv
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//
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// Written: David_Harris@hmc.edu 13 January 2022
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// Modified: cturek@hmc.edu June 2022
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// Modified: cturek@hmc.edu July 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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@ -72,7 +72,7 @@ module testbench;
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// Equip Int test or Sqrt test
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assign Int = 1'b0;
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assign Sqrt = 1'b1;
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assign Sqrt = 1'b0;
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// Divider
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srt srt(.clk, .Start(req),
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@ -101,7 +101,7 @@ module testbench;
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begin
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testnum = 0;
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errors = 0;
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$readmemh ("sqrttestvectors", Tests);
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$readmemh ("testvectors", Tests);
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Vec = Tests[testnum];
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a = Vec[`mema];
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{asign, aExp, afrac} = a;
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