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https://github.com/openhwgroup/cvw
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Modified uncore to use AHB bridge to GPIO
This commit is contained in:
David Harris
parent
c8ac05ba7b
commit
5f5ad77d4a
@ -81,6 +81,24 @@ module uncore (
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logic UARTIntr,GPIOIntr;
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logic SDCIntM;
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logic PCLK, PRESETn, PWRITE, PENABLE;
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// logic PSEL, PREADY;
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logic [1:0] PSEL, PREADY;
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logic [31:0] PADDR;
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logic [`XLEN-1:0] PWDATA;
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logic [`XLEN/8-1:0] PSTRB;
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logic [1:0][`XLEN-1:0] PRDATA;
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// logic [`XLEN-1:0][8:0] PRDATA;
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logic [`XLEN-1:0] HREADBRIDGE;
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logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
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// *** to do:
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// combinational loop related to HREADY, HREADYOUT through PENABLE
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// hook up and test GPIO on AHB
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// hook up HWSTRB and remove subword write decoders
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// add other peripherals on AHB
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// HTRANS encoding
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// Determine which region of physical memory (if any) is being accessed
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// Use a trimmed down portion of the PMA checker - only the address decoders
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// Set access types to all 1 as don't cares because the MMU has already done access checking
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@ -89,98 +107,109 @@ module uncore (
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// unswizzle HSEL signals
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assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0];
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// generate
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// on-chip RAM
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if (`RAM_SUPPORTED) begin : ram
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ram #(
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.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
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.HCLK, .HRESETn,
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.HSELRam, .HADDR,
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.HWRITE, .HREADY, .HSIZED,
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.HTRANS, .HWDATA, .HREADRam,
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.HRESPRam, .HREADYRam);
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end
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// AHB -> APB bridge
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ahbapbbridge #(2) ahbapbbridge
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(.HCLK, .HRESETn, .HSEL({1'b0, HSELGPIO}), .HADDR, .HWDATA, .HWRITE, .HTRANS, .HREADY, .HWSTRB('1),
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.HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE),
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.PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA);
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assign PREADY[1] = 0; // *** replace these with connections to other peripherals
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assign PRDATA[1] = 0;
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assign HSELBRIDGE = HSELGPIO; // if any of the bridge signals are selected
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// This system is showing a combinatonal loop related to HREADY and HREADYBRIDGE and HREADYGPIO
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// on-chip RAM
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if (`RAM_SUPPORTED) begin : ram
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ram #(
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.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
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.HCLK, .HRESETn,
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.HSELRam, .HADDR,
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.HWRITE, .HREADY, .HSIZED,
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.HTRANS, .HWDATA, .HREADRam,
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.HRESPRam, .HREADYRam);
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end
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if (`BOOTROM_SUPPORTED) begin : bootrom
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ram_orig #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE))
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bootrom(
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.HCLK, .HRESETn,
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.HSELRam(HSELBootRom), .HADDR,
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.HWRITE, .HREADY, .HTRANS, .HSIZED,
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.HWDATA,
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.HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom));
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end
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if (`BOOTROM_SUPPORTED) begin : bootrom
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ram_orig #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE))
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bootrom(
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.HCLK, .HRESETn,
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.HSELRam(HSELBootRom), .HADDR,
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.HWRITE, .HREADY, .HTRANS, .HSIZED,
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.HWDATA,
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.HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom));
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end
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// memory-mapped I/O peripherals
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if (`CLINT_SUPPORTED == 1) begin : clint
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clint clint(
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.HCLK, .HRESETn, .TIMECLK,
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.HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE,
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.HWDATA, .HREADY, .HTRANS, .HSIZED,
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.HREADCLINT,
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.HRESPCLINT, .HREADYCLINT,
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.MTIME(MTIME_CLINT),
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.MTimerInt, .MSwInt);
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// memory-mapped I/O peripherals
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if (`CLINT_SUPPORTED == 1) begin : clint
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clint clint(
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.HCLK, .HRESETn, .TIMECLK,
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.HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE,
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.HWDATA, .HREADY, .HTRANS, .HSIZED,
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.HREADCLINT,
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.HRESPCLINT, .HREADYCLINT,
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.MTIME(MTIME_CLINT),
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.MTimerInt, .MSwInt);
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end else begin : clint
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assign MTIME_CLINT = 0;
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assign MTimerInt = 0; assign MSwInt = 0;
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end
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if (`PLIC_SUPPORTED == 1) begin : plic
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plic plic(
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.HCLK, .HRESETn,
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.HSELPLIC, .HADDR(HADDR[27:0]),
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.HWRITE, .HREADY, .HTRANS, .HWDATA,
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.UARTIntr, .GPIOIntr,
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.HREADPLIC, .HRESPPLIC, .HREADYPLIC,
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.MExtInt, .SExtInt);
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end else begin : plic
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assign MExtInt = 0;
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assign SExtInt = 0;
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end
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if (`GPIO_SUPPORTED == 1) begin : gpio
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gpio gpio(
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.HCLK, .HRESETn, .HSELGPIO,
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.HADDR(HADDR[7:0]),
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.HWDATA,
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.HWRITE, .HREADY,
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.HTRANS,
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.HREADGPIO,
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.HRESPGPIO, .HREADYGPIO,
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.GPIOPinsIn,
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.GPIOPinsOut, .GPIOPinsEn,
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.GPIOIntr);
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end else begin : gpio
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assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0;
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end
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if (`UART_SUPPORTED == 1) begin : uart
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uart uart(
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.HCLK, .HRESETn,
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.HSELUART,
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.HADDR(HADDR[2:0]),
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.HWRITE, .HWDATA,
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.HREADUART, .HRESPUART, .HREADYUART,
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.SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface
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.SOUT(UARTSout), .RTSb(), .DTRb(), // to E1A driver to RS232 interface
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.OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb()); // to CPU
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end else begin : uart
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assign UARTSout = 0; assign UARTIntr = 0;
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end
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if (`SDC_SUPPORTED == 1) begin : sdc
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SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS,
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.HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC,
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// sdc interface
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.SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK,
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// interrupt to PLIC
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.SDCIntM
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);
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end else begin : sdc
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assign SDCCLK = 0;
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assign SDCCmdOut = 0;
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assign SDCCmdOE = 0;
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end
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// endgenerate
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end else begin : clint
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assign MTIME_CLINT = 0;
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assign MTimerInt = 0; assign MSwInt = 0;
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end
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if (`PLIC_SUPPORTED == 1) begin : plic
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plic plic(
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.HCLK, .HRESETn,
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.HSELPLIC, .HADDR(HADDR[27:0]),
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.HWRITE, .HREADY, .HTRANS, .HWDATA,
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.UARTIntr, .GPIOIntr,
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.HREADPLIC, .HRESPPLIC, .HREADYPLIC,
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.MExtInt, .SExtInt);
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end else begin : plic
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assign MExtInt = 0;
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assign SExtInt = 0;
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end
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if (`GPIO_SUPPORTED == 1) begin : gpio
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/* gpio gpio(
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.HCLK, .HRESETn, .HSELGPIO,
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.HADDR(HADDR[7:0]),
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.HWDATA,
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.HWRITE, .HREADY,
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.HTRANS,
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.HREADGPIO,
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.HRESPGPIO, .HREADYGPIO,
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.GPIOPinsIn,
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.GPIOPinsOut, .GPIOPinsEn,
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.GPIOIntr); */
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gpio_apb gpio(
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.PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
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.PRDATA(PRDATA[0]), .PREADY(PREADY[0]),
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.iof0(), .iof1(), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .GPIOIntr);
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end else begin : gpio
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assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0;
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end
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if (`UART_SUPPORTED == 1) begin : uart
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uart uart(
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.HCLK, .HRESETn,
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.HSELUART,
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.HADDR(HADDR[2:0]),
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.HWRITE, .HWDATA,
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.HREADUART, .HRESPUART, .HREADYUART,
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.SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface
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.SOUT(UARTSout), .RTSb(), .DTRb(), // to E1A driver to RS232 interface
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.OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb()); // to CPU
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end else begin : uart
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assign UARTSout = 0; assign UARTIntr = 0;
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end
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if (`SDC_SUPPORTED == 1) begin : sdc
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SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS,
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.HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC,
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// sdc interface
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.SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK,
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// interrupt to PLIC
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.SDCIntM
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);
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end else begin : sdc
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assign SDCCLK = 0;
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assign SDCCmdOut = 0;
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assign SDCCmdOE = 0;
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end
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// mux could also include external memory
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// AHB Read Multiplexer
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@ -188,7 +217,8 @@ module uncore (
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({`XLEN{HSELEXTD}} & HRDATAEXT) |
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({`XLEN{HSELCLINTD}} & HREADCLINT) |
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({`XLEN{HSELPLICD}} & HREADPLIC) |
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({`XLEN{HSELGPIOD}} & HREADGPIO) |
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// ({`XLEN{HSELGPIOD}} & HREADGPIO) |
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({`XLEN{HSELBRIDGED}} & HREADBRIDGE) |
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({`XLEN{HSELBootRomD}} & HREADBootRom) |
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({`XLEN{HSELUARTD}} & HREADUART) |
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({`XLEN{HSELSDCD}} & HREADSDC);
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@ -197,7 +227,8 @@ module uncore (
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HSELEXTD & HRESPEXT |
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HSELCLINTD & HRESPCLINT |
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HSELPLICD & HRESPPLIC |
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HSELGPIOD & HRESPGPIO |
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// HSELGPIOD & HRESPGPIO |
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HSELBRIDGE & HRESPBRIDGE |
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HSELBootRomD & HRESPBootRom |
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HSELUARTD & HRESPUART |
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HSELSDC & HRESPSDC;
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@ -206,7 +237,8 @@ module uncore (
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HSELEXTD & HREADYEXT |
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HSELCLINTD & HREADYCLINT |
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HSELPLICD & HREADYPLIC |
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HSELGPIOD & HREADYGPIO |
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// HSELGPIOD & HREADYGPIO |
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HSELBRIDGED & HREADYBRIDGE |
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HSELBootRomD & HREADYBootRom |
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HSELUARTD & HREADYUART |
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HSELSDCD & HREADYSDC |
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@ -214,5 +246,6 @@ module uncore (
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// Address Decoder Delay (figure 4-2 in spec)
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flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELNoneD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD});
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flopr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HSELBRIDGE, HSELBRIDGED);
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endmodule
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