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Don't use this commit yet. Untested.

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This commit is contained in:
Ross Thompson 2022-07-24 15:40:52 -05:00
parent 719b00e338
commit 40e7cda84a
2 changed files with 6 additions and 3 deletions
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4
pipelined/src/cache/cache.sv vendored
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@ -42,8 +42,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits.
input logic [`PA_BITS-1:0] PAdr, // physical address
input logic [(`XLEN-1)/8:0] ByteMask,
input logic [WORDLEN-1:0] FinalWriteData,
input logic FStore2,
input logic [WORDLEN-1:0] FinalWriteData,
input logic FStore2,
output logic CacheCommitted,
output logic CacheStall,
// to performance counters to cpu

5
pipelined/src/lsu/subwordwrite.sv
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@ -39,7 +39,10 @@ module subwordwrite (
);
// Compute byte masks
swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));
//swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));
// *** fix me.
swbytemaskword #(.WORDLEN(`XLEN))
swbytemaskword (.Size(LSUFunct3M[2:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));
// Replicate data for subword writes
if (`XLEN == 64) begin:sww