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fixed errors and warnings in rv32e

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This commit is contained in:
Katherine Parry 2022-04-07 17:21:20 +00:00
parent 1e5e2704f7
commit c307cff503
3 changed files with 10 additions and 10 deletions
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2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f
Subproject commit be67c99bd461742aa1c100bcc0732657faae2230

16
pipelined/src/fpu/fma.sv
View File

@ -193,7 +193,7 @@ module expadd(
endcase
end
end else begin
end else if (`FPSIZES == 4) begin
always_comb begin
case (FmtE)
2'h3: Denorm = 1;
@ -619,7 +619,7 @@ module normalize(
endcase
end
end else begin
end else if (`FPSIZES == 4) begin
always_comb begin
case (FmtM)
2'h3: SumExpTmp = SumExpTmpTmp;
@ -664,7 +664,7 @@ module normalize(
endcase
end
end else begin
end else if (`FPSIZES == 4) begin
logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL;
assign Sum0LEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp;
assign Sum0GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF )-(`NE+2)'(2));
@ -719,7 +719,7 @@ module normalize(
(|CorrSumShifted[3*`NF+2-`NF1:2*`NF+3]&((FmtM==`FMT1)|(FmtM==`FMT2))) |
(|CorrSumShifted[3*`NF+2-`NF2:3*`NF+3-`NF1]&(FmtM==`FMT2));
end else begin
end else if (`FPSIZES == 4) begin
assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) |
(|CorrSumShifted[3*`NF+2-`D_NF:2*`NF+3]&((FmtM==1)|(FmtM==0)|(FmtM==2))) |
(|CorrSumShifted[3*`NF+2-`S_NF:3*`NF+3-`D_NF]&((FmtM==0)|(FmtM==2))) |
@ -876,7 +876,7 @@ module fmaround(
endcase
end
end else begin
end else if (`FPSIZES == 4) begin
always_comb begin
case (FmtM)
2'h3: begin
@ -995,7 +995,7 @@ module fmaround(
endcase
end
end else begin
end else if (`FPSIZES == 4) begin
always_comb begin
case (FmtM)
2'h3: RoundAdd = Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1};
@ -1063,7 +1063,7 @@ module fmaflags(
endcase
end
end else begin
end else if (`FPSIZES == 4) begin
always_comb begin
case (FmtM)
2'h3: GtMaxExp = &FullResultExp[`NE-1:0] | FullResultExp[`NE];
@ -1223,7 +1223,7 @@ module resultselect(
endcase
end
end else begin
end else if (`FPSIZES == 4) begin
always_comb begin
case (FmtM)
2'h3: begin

2
pipelined/src/fpu/unpack.sv
View File

@ -261,7 +261,7 @@ module unpack (
endcase
end
end else begin // if all precsisons are supported - quad, double, single, and half
end else if (`FPSIZES == 4) begin // if all precsisons are supported - quad, double, single, and half
// quad | double | single | half
//-------------------------------------------------------------------