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https://github.com/openhwgroup/cvw
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Implemented on-the-fly conversion for unsigned numbers
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@ -85,14 +85,14 @@ module srt #(parameter Nf=52) (
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// Partial Product Generation
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csa csa(WS, WC, Dsel, qp, WSA, WCA);
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otfc2 otfc2(clk, Start, qp, qz, qm, QuotOTFC);
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expcalc expcalc(.XExp, .YExp, .calcExp);
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signcalc signcalc(.XSign, .YSign, .calcSign);
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srtpostproc postproc(rp, rm, Quot);
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otfc otfc(qp, qz, qm, Quot, QuotOTFC);
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endmodule
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module srtpostproc #(parameter N=52) (
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@ -216,13 +216,46 @@ endmodule
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// otfc //
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//////////
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module otfc #(parameter N=52) (
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module otfc2 #(parameter N=52) (
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input logic clk,
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input logic Start,
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input logic qp, qz, qm,
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input logic [N-1:0] Quot,
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output logic [N-1:0] QuotOTFC
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output logic [N-1:0] r
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);
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assign QuotOTFC = Quot;
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// The on-the-fly converter transfers the quotient
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// bits to the quotient as they come.
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//
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// This code follows the psuedocode presented in the
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// floating point chapter of the book. Right now,
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// it is written for Radix-2 division.
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//
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// QM is Q-1. It allows us to write negative bits
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// without using a costly CPA.
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logic [N+2:0] Q, QM, QNext, QMNext;
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// QR and QMR are the shifted versions of Q and QM.
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// They are treated as [N-1:r] size signals, and
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// discard the r most significant bits of Q and QM.
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logic [N+1:0] QR, QMR;
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flopr #(N+3) Qreg(clk, Start, QNext, Q);
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flopr #(N+3) QMreg(clk, Start, QMNext, QM);
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always_comb begin
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QR = Q[N+1:0];
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QMR = QM[N+1:0]; // Shift Q and QM
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if (qp) begin
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QNext = {QR, 1'b1};
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QMNext = {QR, 1'b0};
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end else if (qz) begin
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QNext = {QR, 1'b0};
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QMNext = {QMR, 1'b1};
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end else begin // If qp and qz are not true, then qm is
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QNext = {QMR, 1'b1};
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QMNext = {QMR, 1'b0};
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end
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end
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assign r = Q[54] ? Q[53:2] : Q[52:1];
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endmodule
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@ -121,8 +121,8 @@ module testbench;
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begin
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errors = errors+1;
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$display("OTFC is %h, should be %h\n", rOTFC, r);
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$display("failed/n");
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$stop;
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$display("failed\n");
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// $stop;
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end
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if (afrac === 52'hxxxxxxxxxxxxx)
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begin
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