mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
This commit is contained in:
Madeleine Masser-Frye
commit
2383ca4f53
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@ -35,16 +35,15 @@
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 1
|
||||
`define IEEE754 0
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
//16 - quad 3 - double 5 - single
|
||||
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
|
||||
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 0
|
||||
|
||||
/// Microarchitectural Features
|
||||
`define UARCH_PIPELINED 1
|
||||
@ -52,9 +51,11 @@
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define DMEM `MEM_CACHE
|
||||
`define IMEM `MEM_CACHE
|
||||
`define DBUS 1
|
||||
`define IBUS 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
@ -82,13 +83,13 @@
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
@ -130,13 +131,12 @@
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
|
||||
`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/shared/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
142
pipelined/config/rv64fpquad/wally-config.vh
Normal file
142
pipelined/config/rv64fpquad/wally-config.vh
Normal file
@ -0,0 +1,142 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 1
|
||||
|
||||
/// Microarchitectural Features
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define DMEM `MEM_CACHE
|
||||
`define IMEM `MEM_CACHE
|
||||
`define DBUS 1
|
||||
`define IBUS 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 256
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
`define BOOTROM_RANGE 56'h00000FFF
|
||||
`define RAM_SUPPORTED 1'b1
|
||||
`define RAM_BASE 56'h80000000
|
||||
`define RAM_RANGE 56'h7FFFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 56'h80000000
|
||||
`define EXT_MEM_RANGE 56'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 56'h02000000
|
||||
`define CLINT_RANGE 56'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 56'h10060000
|
||||
`define GPIO_RANGE 56'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 56'h10000000
|
||||
`define UART_RANGE 56'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 56'h0C000000
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/shared/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
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File diff suppressed because it is too large
Load Diff
@ -76,7 +76,8 @@
|
||||
`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)
|
||||
|
||||
// Floating point constants needed for FPU paramerterization
|
||||
`define FPSIZES (`Q_SUPPORTED+`D_SUPPORTED+`F_SUPPORTED+`ZFH_SUPPORTED)
|
||||
`define FPSIZES ((3)'(`Q_SUPPORTED)+(3)'(`D_SUPPORTED)+(3)'(`F_SUPPORTED)+(3)'(`ZFH_SUPPORTED))
|
||||
`define FMTBITS (((`FPSIZES==3'b011)|(`FPSIZES==3'b100)) ? 2 : 1)
|
||||
`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN)
|
||||
`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE)
|
||||
`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF)
|
||||
|
||||
@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/
|
||||
verilator=`which verilator`
|
||||
|
||||
basepath=$(dirname $0)/..
|
||||
for config in rv32e rv64gc rv32gc rv32ic ; do
|
||||
for config in rv64fp rv32e rv64gc rv32gc rv32ic; do
|
||||
echo "$config linting..."
|
||||
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then
|
||||
echo "Exiting after $config lint due to errors or warnings"
|
||||
|
||||
@ -1 +0,0 @@
|
||||
vsim -do wally-fp64.do
|
||||
@ -1,3 +0,0 @@
|
||||
vsim -c <<!
|
||||
do wally-fp64-batch.do rv64gc imperas64d
|
||||
!
|
||||
@ -3,9 +3,10 @@
|
||||
# cvtfp - test floating-point conversion unit (fcvtfp)
|
||||
# cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
|
||||
# add - test addition
|
||||
# fma - test fma
|
||||
# sub - test subtraction
|
||||
# div - test division
|
||||
# sqrt - test square ro
|
||||
# all - test everything
|
||||
|
||||
vsim -do "do fp.do rv64fp cmp"
|
||||
vsim -do "do testfloat.do rv64fpquad cmp"
|
||||
@ -7,4 +7,4 @@
|
||||
# sqrt - test square root
|
||||
# all - test everything
|
||||
|
||||
vsim -c -do "do fp.do rv64fp cvtfp"
|
||||
vsim -c -do "do testfloat.do rv64fpquad all"
|
||||
@ -1,2 +1,2 @@
|
||||
vsim -do "do wally-pipelined.do rv64gc imperas64d"
|
||||
vsim -do "do wally-pipelined.do rv32e imperas64d"
|
||||
|
||||
|
||||
@ -1,50 +0,0 @@
|
||||
# wally-pipelined-batch.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# Usage: do wally-pipelined-batch.do <config> <testcases>
|
||||
# Example: do wally-pipelined-batch.do rv32ic imperas-32i
|
||||
|
||||
# Use this wally-pipelined-batch.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined-batch.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-pipelined-batch.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work_${1}_${2}] {
|
||||
vdel -lib work_${1}_${2} -all
|
||||
}
|
||||
vlib work_${1}_${2}
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined-batch.do ../config/rv32ic rv32ic
|
||||
vlog -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-f64.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt
|
||||
# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
|
||||
#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
|
||||
#vsim -coverage -lib work_$2 workopt_$2
|
||||
|
||||
run -all
|
||||
#coverage report -file wally-pipelined-coverage.txt
|
||||
# These aren't doing anything helpful
|
||||
#coverage report -memory
|
||||
#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2
|
||||
quit
|
||||
@ -1,54 +0,0 @@
|
||||
# wally-pipelined.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
|
||||
|
||||
# Use this wally-pipelined.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-pipelined.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined.do ../config/rv32ic
|
||||
#switch $argc {
|
||||
# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
#}
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vlog +incdir+../config/rv64gc +incdir+../config/shared ../testbench/testbench-f64.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
|
||||
vopt +acc work.testbench -G TEST=imperas64d -o workopt
|
||||
vsim workopt
|
||||
|
||||
view wave
|
||||
-- display input and output signals as hexidecimal values
|
||||
do ./wave-dos/generic.do
|
||||
|
||||
-- Run the Simulation
|
||||
#run 3600
|
||||
run -all
|
||||
#quit
|
||||
#noview ../testbench/testbench-imperas.sv
|
||||
noview ../testbench/testbench.sv
|
||||
view wave
|
||||
@ -35,7 +35,7 @@ vlib wkdir/work_${1}_${2}
|
||||
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G DEBUG_TRACE=1 -o testbenchopt
|
||||
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt
|
||||
vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084
|
||||
|
||||
run -all
|
||||
|
||||
@ -34,7 +34,7 @@ vlib work
|
||||
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G DEBUG_TRACE=1 -o testbenchopt
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
|
||||
|
||||
#-- Run the Simulation
|
||||
@ -48,11 +48,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
} elseif {$2 eq "buildroot-no-trace"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
<<<<<<< HEAD
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -G DEBUG_TRACE=0 -o testbenchopt
|
||||
=======
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -o testbenchopt
|
||||
>>>>>>> parent of 9eb374b6... Changed NO_IE_MTIME_CHECKPOINT so it uses the new parameter name
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
|
||||
|
||||
#-- Run the Simulation
|
||||
|
||||
@ -1,23 +0,0 @@
|
||||
# Makefile
|
||||
|
||||
CC = gcc
|
||||
CFLAGS = -O3
|
||||
LIBS = -lm
|
||||
LFLAGS = -L.
|
||||
# Link against the riscv-isa-sim version of SoftFloat rather than
|
||||
# the regular version to get RISC-V NaN behavior
|
||||
IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat
|
||||
LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
|
||||
#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
|
||||
#LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
|
||||
SRCS = $(wildcard *.c)
|
||||
|
||||
PROGS = $(patsubst %.c,%,$(SRCS))
|
||||
|
||||
all: $(PROGS)
|
||||
|
||||
%: %.c
|
||||
$(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
|
||||
|
||||
clean:
|
||||
rm -f $(PROGS)
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,23 +0,0 @@
|
||||
# fma.do
|
||||
#
|
||||
# run with vsim -do "do fma.do"
|
||||
# add -c before -do for batch simulation
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
vlib worklib
|
||||
|
||||
vlog -lint -sv -work worklib fma16.v testbench.v
|
||||
vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
|
||||
vsim -lib worklib testbenchopt
|
||||
|
||||
add wave sim:/testbench_fma16/clk
|
||||
add wave sim:/testbench_fma16/reset
|
||||
add wave sim:/testbench_fma16/x
|
||||
add wave sim:/testbench_fma16/y
|
||||
add wave sim:/testbench_fma16/z
|
||||
add wave sim:/testbench_fma16/result
|
||||
add wave sim:/testbench_fma16/rexpected
|
||||
|
||||
run -all
|
||||
@ -1,268 +0,0 @@
|
||||
// fma16.sv
|
||||
// David_Harris@hmc.edu 26 February 2022
|
||||
// 16-bit floating-point multiply-accumulate
|
||||
|
||||
// Operation: general purpose multiply, add, fma, with optional negation
|
||||
// If mul=1, p = x * y. Else p = x.
|
||||
// If add=1, result = p + z. Else result = p.
|
||||
// If negr or negz = 1, negate result or z to handle negations and subtractions
|
||||
// fadd: mul = 0, add = 1, negr = negz = 0
|
||||
// fsub: mul = 0, add = 1, negr = 0, negz = 1
|
||||
// fmul: mul = 1, add = 0, negr = 0, negz = 0
|
||||
// fmadd: mul = 1, add = 1, negr = 0, negz = 0
|
||||
// fmsub: mul = 1, add = 1, negr = 0, negz = 1
|
||||
// fnmadd: mul = 1, add = 1, negr = 1, negz = 0
|
||||
// fnmsub: mul = 1, add = 1, negr = 1, negz = 1
|
||||
|
||||
`define FFLEN 16
|
||||
`define Nf 10
|
||||
`define Ne 5
|
||||
`define BIAS 15
|
||||
`define EMIN (-(2**(`Ne-1)-1))
|
||||
`define EMAX (2**(`Ne-1)-1)
|
||||
|
||||
`define NaN 16'h7E00
|
||||
`define INF 15'h7C00
|
||||
|
||||
// rounding modes *** update
|
||||
`define RZ 3'b00
|
||||
`define RNE 3'b01
|
||||
`define RM 3'b10
|
||||
`define RP 3'b11
|
||||
|
||||
module fma16(
|
||||
input logic [`FFLEN-1:0] x, y, z,
|
||||
input logic mul, add, negr, negz,
|
||||
input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn
|
||||
output logic [`FFLEN-1:0] result);
|
||||
|
||||
logic [`Nf:0] xm, ym, zm; // U1.Nf
|
||||
logic [`Ne-1:0] xe, ye, ze; // B_Ne
|
||||
logic xs, ys, zs;
|
||||
logic zs1; // sign before optional negation
|
||||
logic [2*`Nf+1:0] pm; // U2.2Nf
|
||||
logic [`Ne:0] pe; // B_Ne+1
|
||||
logic ps; // sign of product
|
||||
logic [22:0] rm;
|
||||
logic [`Ne+1:0] re;
|
||||
logic rs;
|
||||
logic xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan;
|
||||
logic [`Ne+1:0] re2;
|
||||
|
||||
unpack16 unpack(x, y, z, xm, ym, zm, xe, ye, ze, xs, ys, zs1, xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan); // unpack inputs
|
||||
//signadj16 signadj(negr, negz, xs, ys, zs1, ps, zs); // handle negations
|
||||
mult16 mult16(mul, xm, ym, xe, ye, xs, ys, pm, pe, ps); // p = x * y
|
||||
add16 add16(add, pm, zm, pe, ze, ps, zs, negz, rm, re, re2, rs); // r = z + p
|
||||
postproc16 post(roundmode, xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan, rm, zm, re, ze, rs, zs, ps, re2, result); // normalize, round, pack
|
||||
endmodule
|
||||
|
||||
module mult16(
|
||||
input logic mul,
|
||||
input logic [`Nf:0] xm, ym,
|
||||
input logic [`Ne-1:0] xe, ye,
|
||||
input logic xs, ys,
|
||||
output logic [2*`Nf+1:0] pm,
|
||||
output logic [`Ne:0] pe,
|
||||
output logic ps);
|
||||
|
||||
// only multiply if mul = 1
|
||||
assign pm = mul ? xm * ym : {1'b0, xm, 10'b0}; // multiply mantiassas
|
||||
assign pe = mul ? xe + ye - `BIAS : {1'b0, xe}; // add exponents, account for bias
|
||||
assign ps = xs ^ ys; // negative if X xor Y are negative
|
||||
endmodule
|
||||
|
||||
module add16(
|
||||
input logic add,
|
||||
input logic [2*`Nf+1:0] pm, // U2.2Nf
|
||||
input logic [`Nf:0] zm, // U1.Nf
|
||||
input logic [`Ne:0] pe, // B_Ne+1
|
||||
input logic [`Ne-1:0] ze, // B_Ne
|
||||
input logic ps, zs,
|
||||
input logic negz,
|
||||
output logic [22:0] rm,
|
||||
output logic [`Ne+1:0] re, // B_Ne+2
|
||||
output logic [`Ne+1:0] re2,
|
||||
output logic rs);
|
||||
|
||||
logic [`Nf*3+7:0] paligned, zaligned, zalignedaddsub, r, r2, rnormed, rnormed2; // U(Nf+6).(2Nf+2) aligned significands
|
||||
logic signed [`Ne:0] ExpDiff; // Q(Ne+2).0
|
||||
logic [`Ne:0] AlignCnt; // U(Ne+3) bits to right shift Z for alignment *** check size.
|
||||
logic [`Nf-1:0] prezsticky;
|
||||
logic zsticky;
|
||||
logic effectivesub;
|
||||
logic rs0;
|
||||
logic [`Ne:0] leadingzeros, NormCnt; // *** should paramterize size
|
||||
logic [`Ne:0] re1;
|
||||
|
||||
// Alignment shift
|
||||
assign paligned = {{(`Nf+4){1'b0}}, pm, 2'b00}; // constant shift to prepend leading and trailing 0s.
|
||||
assign ExpDiff = pe - {1'b0, ze}; // Compute exponent difference as signed number
|
||||
always_comb // AlignCount mux; see Muller page 254
|
||||
if (ExpDiff <= (-2*`Nf - 1)) begin AlignCnt = 3*`Nf + 7; re = {1'b0, pe}; end
|
||||
else if (ExpDiff <= 2) begin AlignCnt = `Nf + 4 - ExpDiff; re = {1'b0, pe}; end
|
||||
else if (ExpDiff <= `Nf+3) begin AlignCnt = `Nf + 4 - ExpDiff; re = {2'b0, ze}; end
|
||||
else begin AlignCnt = 0; re = {2'b0, ze}; end
|
||||
// Shift Zm right by AlignCnt. Produce 3Nf+8 bits of Zaligned in U(Nf+6).(2Nf+2) and Nf bits becoming sticky
|
||||
assign {zaligned, prezsticky} = {zm, {(3*`Nf+7){1'b0}}} >> AlignCnt; //Right shift
|
||||
assign zsticky = |prezsticky; // Sticky bit if any of the discarded bits were 1
|
||||
|
||||
// Effective subtraction
|
||||
assign effectivesub = ps ^ zs ^ negz; // subtract |z| from |p|
|
||||
assign zalignedaddsub = effectivesub ? ~zaligned : zaligned; // invert zaligned for subtraction
|
||||
|
||||
// Adder
|
||||
assign r = paligned + zalignedaddsub + {{`Nf*3+7{1'b0}}, effectivesub}; // add aligned significands
|
||||
assign rs0 = r[`Nf*3+7]; // sign of the initial result
|
||||
assign r2 = rs0 ? ~r+1 : r; // invert sum if negative; could optimize with end-around carry?
|
||||
|
||||
// Sign Logic
|
||||
assign rs = ps ^ rs0; // flip the sign if necessary
|
||||
|
||||
// Leading zero counter
|
||||
lzc lzc(r2, leadingzeros); // count number of leading zeros in 2Nf+5 lower digits of r2
|
||||
assign re1 = pe +2 - leadingzeros; // *** declare, # of bits
|
||||
|
||||
// Normalization shift
|
||||
always_comb // NormCount mux
|
||||
if (ExpDiff < 3) begin
|
||||
if (re1 >= `EMIN) begin NormCnt = `Nf + 3 + leadingzeros; re2 = {1'b0, re1}; end
|
||||
else begin NormCnt = `Nf + 5 + pe - `EMIN; re2 = `EMIN; end
|
||||
end else begin NormCnt = AlignCnt; re = {2'b00, ze}; end
|
||||
assign rnormed = r2 << NormCnt; // *** update sticky
|
||||
/* temporarily comment out to start synth
|
||||
|
||||
// One-bit secondary normalization
|
||||
if (ExpDiff <= 2) begin rnormed2 = rnormed; re2 = re; end // no secondary normalization
|
||||
else begin // *** handle sticky
|
||||
if (rnormed[***]) begin rnormed2 = rnormed >> 1; re2 = re+1; end
|
||||
else if (rnormed[***-1]) begin rnormed2 = rnormed; re2 = re; end
|
||||
else begin rnormed2 = rnormed << 1; re2 = re-1; end
|
||||
end
|
||||
|
||||
// round
|
||||
assign l = rnormed2[***]; // least significant bit
|
||||
assign r = rnormed2[***-1]; // rounding bit
|
||||
assign s = ***; // sticky bit
|
||||
always_comb
|
||||
case (roundmode)
|
||||
RZ: roundup = 0;
|
||||
RP: roundup = ~rs & (r | s);
|
||||
RM: roundup = rs & (r | s);
|
||||
RNE: roundup = r & (s | l);
|
||||
default: roundup = 0;
|
||||
endcase
|
||||
assign {re3, rrounded} = {re2, rnormed2[***]} + roundup; // increment if necessary
|
||||
*/
|
||||
|
||||
// *** need to handle rounding to MAXNUM vs. INFINITY
|
||||
|
||||
// add or pass product through
|
||||
/* assign rm = add ? arm : {1'b0, pm};
|
||||
assign re = add ? are : {1'b0, pe};
|
||||
assign rs = add ? ars : ps; */
|
||||
endmodule
|
||||
|
||||
module lzc(
|
||||
input logic [`Nf*3+7:0] r2,
|
||||
output logic [`Ne:0] leadingzeros
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module postproc16(
|
||||
input logic [1:0] roundmode,
|
||||
input logic xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan,
|
||||
input logic [22:0] rm,
|
||||
input logic [`Nf:0] zm, // U1.Nf
|
||||
input logic [6:0] re,
|
||||
input logic [`Ne-1:0] ze, // B_Ne
|
||||
input logic rs, zs, ps,
|
||||
input logic [`Ne+1:0] re2,
|
||||
output logic [15:0] result);
|
||||
|
||||
logic [9:0] uf, uff;
|
||||
logic [6:0] ue;
|
||||
logic [6:0] ueb, uebiased;
|
||||
logic invalid;
|
||||
|
||||
// Special cases
|
||||
// *** not handling signaling NaN
|
||||
// *** also add overflow/underflow/inexact
|
||||
always_comb begin
|
||||
if (xnan | ynan | znan) begin result = `NaN; invalid = 0; end // propagate NANs
|
||||
else if ((xinf | yinf) & zinf & (ps ^ zs)) begin result = `NaN; invalid = 1; end // infinity - infinity
|
||||
else if (xzero & yinf | xinf & yzero) begin result = `NaN; invalid = 1; end // zero times infinity
|
||||
else if (xinf | yinf) begin result = {ps, `INF}; invalid = 0; end // X or Y
|
||||
else if (zinf) begin result = {zs, `INF}; invalid = 0; end // infinite Z
|
||||
else if (xzero | yzero) begin result = {zs, ze, zm[`Nf-1:0]}; invalid = 0; end
|
||||
else if (re2 >= `EMAX) begin result = {rs, `INF}; invalid = 0; end
|
||||
else begin result = {rs, re[`Ne-1:0], rm[`Nf-1:0]}; invalid = 0; end
|
||||
end
|
||||
|
||||
always_comb
|
||||
if (rm[21]) begin // normalization right shift by 1 and bump up exponent;
|
||||
ue = re + 7'b1;
|
||||
uf = rm[20:11];
|
||||
end else begin // no normalization shift needed
|
||||
ue = re;
|
||||
uf = rm[19:10];
|
||||
end
|
||||
|
||||
// overflow
|
||||
always_comb begin
|
||||
ueb = ue-7'd15;
|
||||
if (ue >= 7'd46) begin // overflow
|
||||
/* uebiased = 7'd30;
|
||||
uff = 10'h3ff; */
|
||||
end else begin
|
||||
uebiased = ue-7'd15;
|
||||
uff = uf;
|
||||
end
|
||||
end
|
||||
|
||||
assign result = {rs, uebiased[4:0], uff};
|
||||
|
||||
// add special case handling for zeros, NaN, Infinity
|
||||
endmodule
|
||||
|
||||
module signadj16(
|
||||
input logic negr, negz,
|
||||
input logic xs, ys, zs1,
|
||||
output logic ps, zs);
|
||||
|
||||
assign ps = xs ^ ys; // sign of product
|
||||
assign zs = zs1 ^ negz; // sign of addend
|
||||
endmodule
|
||||
|
||||
module unpack16(
|
||||
input logic [15:0] x, y, z,
|
||||
output logic [10:0] xm, ym, zm,
|
||||
output logic [4:0] xe, ye, ze,
|
||||
output logic xs, ys, zs,
|
||||
output logic xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan);
|
||||
|
||||
unpacknum16 upx(x, xm, xe, xs, xzero, xinf, xnan);
|
||||
unpacknum16 upy(y, ym, ye, ys, yzero, yinf, ynan);
|
||||
unpacknum16 upz(z, zm, ze, zs, zzero, zinf, znan);
|
||||
endmodule
|
||||
|
||||
module unpacknum16(
|
||||
input logic [15:0] num,
|
||||
output logic [10:0] m,
|
||||
output logic [4:0] e,
|
||||
output logic s,
|
||||
output logic zero, inf, nan);
|
||||
|
||||
logic [9:0] f; // fraction without leading 1
|
||||
logic [4:0] eb; // biased exponent
|
||||
|
||||
assign {s, eb, f} = num; // pull bit fields out of floating-point number
|
||||
assign m = {1'b1, f}; // prepend leading 1 to fraction
|
||||
assign e = eb; // leave bias in exponent ***
|
||||
assign zero = (e == 0 && f == 0);
|
||||
assign inf = (e == 31 && f == 0);
|
||||
assign nan = (e == 31 && f != 0);
|
||||
endmodule
|
||||
|
||||
|
||||
@ -1,24 +0,0 @@
|
||||
// fma16.sv
|
||||
// David_Harris@hmc.edu 26 February 2022
|
||||
// 16-bit floating-point multiply-accumulate
|
||||
|
||||
// Operation: general purpose multiply, add, fma, with optional negation
|
||||
// If mul=1, p = x * y. Else p = x.
|
||||
// If add=1, result = p + z. Else result = p.
|
||||
// If negr or negz = 1, negate result or z to handle negations and subtractions
|
||||
// fadd: mul = 0, add = 1, negr = negz = 0
|
||||
// fsub: mul = 0, add = 1, negr = 0, negz = 1
|
||||
// fmul: mul = 1, add = 0, negr = 0, negz = 0
|
||||
// fmadd: mul = 1, add = 1, negr = 0, negz = 0
|
||||
// fmsub: mul = 1, add = 1, negr = 0, negz = 1
|
||||
// fnmadd: mul = 1, add = 1, negr = 1, negz = 0
|
||||
// fnmsub: mul = 1, add = 1, negr = 1, negz = 1
|
||||
|
||||
module fma16(
|
||||
input logic [15:0] x, y, z,
|
||||
input logic mul, add, negr, negz,
|
||||
input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn
|
||||
output logic [15:0] result);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,240 +0,0 @@
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include "softfloat.h"
|
||||
#include "softfloat_types.h"
|
||||
|
||||
typedef union sp {
|
||||
float32_t v;
|
||||
float f;
|
||||
} sp;
|
||||
|
||||
// lists of tests, terminated with 0x8000
|
||||
uint16_t easyExponents[] = {15, 0x8000};
|
||||
uint16_t medExponents[] = {1, 14, 15, 16, 20, 30, 0x8000};
|
||||
uint16_t allExponents[] = {1, 15, 16, 30, 31, 0x8000};
|
||||
uint16_t easyFracts[] = {0, 0x200, 0x8000}; // 1.0 and 1.1
|
||||
uint16_t medFracts[] = {0, 0x200, 0x001, 0x3FF, 0x8000};
|
||||
uint16_t zeros[] = {0x0000, 0x8000};
|
||||
uint16_t infs[] = {0x7C00, 0xFC00};
|
||||
uint16_t nans[] = {0x7D00, 0x7D01};
|
||||
|
||||
void softfloatInit(void) {
|
||||
softfloat_roundingMode = softfloat_round_minMag;
|
||||
softfloat_exceptionFlags = 0;
|
||||
softfloat_detectTininess = softfloat_tininess_beforeRounding;
|
||||
}
|
||||
|
||||
float convFloat(float16_t f16) {
|
||||
float32_t f32;
|
||||
float res;
|
||||
sp r;
|
||||
|
||||
f32 = f16_to_f32(f16);
|
||||
r.v = f32;
|
||||
res = r.f;
|
||||
return res;
|
||||
}
|
||||
|
||||
void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add, int negp, int negz, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
|
||||
float16_t result;
|
||||
int op, flagVals;
|
||||
char calc[80], flags[80];
|
||||
float32_t x32, y32, z32, r32;
|
||||
float xf, yf, zf, rf;
|
||||
float16_t smallest;
|
||||
|
||||
if (!mul) y.v = 0x3C00; // force y to 1 to avoid multiply
|
||||
if (!add) z.v = 0x0000; // force z to 0 to avoid add
|
||||
if (negp) x.v ^= 0x8000; // flip sign of x to negate p
|
||||
if (negz) z.v ^= 0x8000; // flip sign of z to negate z
|
||||
op = roundingMode << 4 | mul<<3 | add<<2 | negp<<1 | negz;
|
||||
// printf("op = %02x rm %d mul %d add %d negp %d negz %d\n", op, roundingMode, mul, add, negp, negz);
|
||||
softfloat_exceptionFlags = 0; // clear exceptions
|
||||
result = f16_mulAdd(x, y, z);
|
||||
|
||||
sprintf(flags, "NV: %d OF: %d UF: %d NX: %d",
|
||||
(softfloat_exceptionFlags >> 4) % 2,
|
||||
(softfloat_exceptionFlags >> 2) % 2,
|
||||
(softfloat_exceptionFlags >> 1) % 2,
|
||||
(softfloat_exceptionFlags) % 2);
|
||||
// pack these four flags into one nibble, discarding DZ flag
|
||||
flagVals = softfloat_exceptionFlags & 0x7 | ((softfloat_exceptionFlags >> 1) & 0x8);
|
||||
|
||||
|
||||
// convert to floats for printing
|
||||
xf = convFloat(x);
|
||||
yf = convFloat(y);
|
||||
zf = convFloat(z);
|
||||
rf = convFloat(result);
|
||||
if (mul)
|
||||
if (add) sprintf(calc, "%f * %f + %f = %f", xf, yf, zf, rf);
|
||||
else sprintf(calc, "%f * %f = %f", xf, yf, rf);
|
||||
else sprintf(calc, "%f + %f = %f", xf, zf, rf);
|
||||
|
||||
// omit denorms, which aren't required for this project
|
||||
smallest.v = 0x0400;
|
||||
float16_t resultmag = result;
|
||||
resultmag.v &= 0x7FFF; // take absolute value
|
||||
if (f16_lt(resultmag, smallest) && (resultmag.v != 0x0000)) fprintf (fptr, "// skip denorm: ");
|
||||
if (resultmag.v == 0x0000 && !zeroAllowed) fprintf(fptr, "// skip zero: ");
|
||||
if ((resultmag.v == 0x7C00 || resultmag.v == 0x7BFF) && !infAllowed) fprintf(fptr, "// Skip inf: ");
|
||||
if (resultmag.v > 0x7C00 && !nanAllowed) fprintf(fptr, "// Skip NaN: ");
|
||||
fprintf(fptr, "%04x_%04x_%04x_%02x_%04x_%01x // %s %s\n", x.v, y.v, z.v, op, result.v, flagVals, calc, flags);
|
||||
}
|
||||
|
||||
void prepTests(uint16_t *e, uint16_t *f, char *testName, char *desc, float16_t *cases,
|
||||
FILE *fptr, int *numCases) {
|
||||
int i, j;
|
||||
|
||||
fprintf(fptr, desc); fprintf(fptr, "\n");
|
||||
*numCases=0;
|
||||
for (i=0; e[i] != 0x8000; i++)
|
||||
for (j=0; f[j] != 0x8000; j++) {
|
||||
cases[*numCases].v = f[j] | e[i]<<10;
|
||||
*numCases = *numCases + 1;
|
||||
}
|
||||
}
|
||||
|
||||
void genMulTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
|
||||
int i, j, k, numCases;
|
||||
float16_t x, y, z;
|
||||
float16_t cases[100000];
|
||||
FILE *fptr;
|
||||
char fn[80];
|
||||
|
||||
sprintf(fn, "work/%s.tv", testName);
|
||||
fptr = fopen(fn, "w");
|
||||
prepTests(e, f, testName, desc, cases, fptr, &numCases);
|
||||
z.v = 0x0000;
|
||||
for (i=0; i < numCases; i++) {
|
||||
x.v = cases[i].v;
|
||||
for (j=0; j<numCases; j++) {
|
||||
y.v = cases[j].v;
|
||||
for (k=0; k<=sgn; k++) {
|
||||
y.v ^= (k<<15);
|
||||
genCase(fptr, x, y, z, 1, 0, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed);
|
||||
}
|
||||
}
|
||||
}
|
||||
fclose(fptr);
|
||||
}
|
||||
|
||||
void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
|
||||
int i, j, k, numCases;
|
||||
float16_t x, y, z;
|
||||
float16_t cases[100000];
|
||||
FILE *fptr;
|
||||
char fn[80];
|
||||
|
||||
sprintf(fn, "work/%s.tv", testName);
|
||||
fptr = fopen(fn, "w");
|
||||
prepTests(e, f, testName, desc, cases, fptr, &numCases);
|
||||
y.v = 0x0000;
|
||||
for (i=0; i < numCases; i++) {
|
||||
x.v = cases[i].v;
|
||||
for (j=0; j<numCases; j++) {
|
||||
z.v = cases[j].v;
|
||||
for (k=0; k<=sgn; k++) {
|
||||
z.v ^= (k<<15);
|
||||
genCase(fptr, x, y, z, 0, 1, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed);
|
||||
}
|
||||
}
|
||||
}
|
||||
fclose(fptr);
|
||||
}
|
||||
|
||||
|
||||
void genFMATests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
|
||||
int i, j, k, l, numCases;
|
||||
float16_t x, y, z;
|
||||
float16_t cases[100000];
|
||||
FILE *fptr;
|
||||
char fn[80];
|
||||
|
||||
sprintf(fn, "work/%s.tv", testName);
|
||||
fptr = fopen(fn, "w");
|
||||
prepTests(e, f, testName, desc, cases, fptr, &numCases);
|
||||
for (i=0; i < numCases; i++) {
|
||||
x.v = cases[i].v;
|
||||
for (j=0; j<numCases; j++) {
|
||||
y.v = cases[j].v;
|
||||
for (k=0; k<numCases; k++) {
|
||||
z.v = cases[k].v;
|
||||
for (l=0; l<=sgn; l++) {
|
||||
z.v ^= (l<<15);
|
||||
genCase(fptr, x, y, z, 1, 1, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
fclose(fptr);
|
||||
}
|
||||
|
||||
void genSpecialTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
|
||||
int i, j, k, sx, sy, sz, numCases;
|
||||
float16_t x, y, z;
|
||||
float16_t cases[100000];
|
||||
FILE *fptr;
|
||||
char fn[80];
|
||||
|
||||
sprintf(fn, "work/%s.tv", testName);
|
||||
fptr = fopen(fn, "w");
|
||||
prepTests(e, f, testName, desc, cases, fptr, &numCases);
|
||||
cases[numCases].v = 0x0000; // add +0 case
|
||||
cases[numCases+1].v = 0x8000; // add -0 case
|
||||
numCases += 2;
|
||||
for (i=0; i < numCases; i++) {
|
||||
x.v = cases[i].v;
|
||||
for (j=0; j<numCases; j++) {
|
||||
y.v = cases[j].v;
|
||||
for (k=0; k<numCases; k++) {
|
||||
z.v = cases[k].v;
|
||||
for (sx=0; sx<=sgn; sx++) {
|
||||
x.v ^= (sx<<15);
|
||||
for (sy=0; sy<=sgn; sy++) {
|
||||
y.v ^= (sy<<15);
|
||||
for (sz=0; sz<=sgn; sz++) {
|
||||
z.v ^= (sz<<15);
|
||||
genCase(fptr, x, y, z, 1, 1, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
fclose(fptr);
|
||||
}
|
||||
|
||||
|
||||
int main()
|
||||
{
|
||||
softfloatInit(); // configure softfloat modes
|
||||
|
||||
// Test cases: multiplication
|
||||
genMulTests(easyExponents, easyFracts, 0, "fmul_0", "// Multiply with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0, 0);
|
||||
genMulTests(medExponents, medFracts, 0, "fmul_1", "// Multiply with various exponents and unsigned fractions, RZ", 0, 0, 0, 0);
|
||||
genMulTests(medExponents, medFracts, 1, "fmul_2", "// Multiply with various exponents and signed fractions, RZ", 0, 0, 0, 0);
|
||||
|
||||
// Test cases: addition
|
||||
genAddTests(easyExponents, easyFracts, 0, "fadd_0", "// Add with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0, 0);
|
||||
genAddTests(medExponents, medFracts, 0, "fadd_1", "// Add with various exponents and unsigned fractions, RZ", 0, 0, 0, 0);
|
||||
genAddTests(medExponents, medFracts, 1, "fadd_2", "// Add with various exponents and signed fractions, RZ", 0, 0, 0, 0);
|
||||
|
||||
// Test cases: FMA
|
||||
genFMATests(easyExponents, easyFracts, 0, "fma_0", "// FMA with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0, 0);
|
||||
genFMATests(medExponents, medFracts, 0, "fma_1", "// FMA with various exponents and unsigned fractions, RZ", 0, 0, 0, 0);
|
||||
genFMATests(medExponents, medFracts, 1, "fma_2", "// FMA with various exponents and signed fractions, RZ", 0, 0, 0, 0);
|
||||
|
||||
// Test cases: Zero, Infinity, NaN
|
||||
genSpecialTests(allExponents, medFracts, 1, "fma_special_rz", "// FMA with special cases, RZ", 0, 1, 1, 1);
|
||||
|
||||
// Full test cases with other rounding modes
|
||||
softfloat_roundingMode = softfloat_round_near_even;
|
||||
genSpecialTests(allExponents, medFracts, 1, "fma_special_rne", "// FMA with special cases, RNE", 1, 1, 1, 1);
|
||||
softfloat_roundingMode = softfloat_round_min;
|
||||
genSpecialTests(allExponents, medFracts, 1, "fma_special_rm", "// FMA with special cases, RM", 2, 1, 1, 1);
|
||||
softfloat_roundingMode = softfloat_round_max;
|
||||
genSpecialTests(allExponents, medFracts, 1, "fma_special_rp", "// FMA with special cases, RP", 3, 1, 1, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,8 +0,0 @@
|
||||
#!/bin/bash
|
||||
# check for warnings in Verilog code
|
||||
# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
|
||||
export PATH=$PATH:/usr/local/bin/
|
||||
verilator=`which verilator`
|
||||
|
||||
basepath=$(dirname $0)/..
|
||||
$verilator --lint-only --top-module fma16 fma16.v
|
||||
@ -1,2 +0,0 @@
|
||||
vsim -do "do fma.do"
|
||||
|
||||
@ -1 +0,0 @@
|
||||
vsim -c -do "do fma.do"
|
||||
@ -1 +0,0 @@
|
||||
make -C ../../../synthDC synth DESIGN=fma16
|
||||
@ -1,52 +0,0 @@
|
||||
/* verilator lint_off STMTDLY */
|
||||
module testbench_fma16;
|
||||
reg clk, reset;
|
||||
reg [15:0] x, y, z, rexpected;
|
||||
wire [15:0] result;
|
||||
reg [7:0] ctrl;
|
||||
reg [3:0] flagsexpected;
|
||||
reg mul, add, negp, negz;
|
||||
reg [1:0] roundmode;
|
||||
reg [31:0] vectornum, errors;
|
||||
reg [75:0] testvectors[10000:0];
|
||||
|
||||
// instantiate device under test
|
||||
fma16 dut(x, y, z, mul, add, negp, negz, roundmode, result);
|
||||
|
||||
// generate clock
|
||||
always
|
||||
begin
|
||||
clk = 1; #5; clk = 0; #5;
|
||||
end
|
||||
|
||||
// at start of test, load vectors and pulse reset
|
||||
initial
|
||||
begin
|
||||
$readmemh("work/fmul_0.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
reset = 1; #22; reset = 0;
|
||||
end
|
||||
|
||||
// apply test vectors on rising edge of clk
|
||||
always @(posedge clk)
|
||||
begin
|
||||
#1; {x, y, z, ctrl, rexpected, flagsexpected} = testvectors[vectornum];
|
||||
{roundmode, mul, add, negp, negz} = ctrl[5:0];
|
||||
end
|
||||
|
||||
// check results on falling edge of clk
|
||||
always @(negedge clk)
|
||||
if (~reset) begin // skip during reset
|
||||
if (result !== rexpected) begin // check result // *** should also add tests on flags eventually
|
||||
$display("Error: inputs %h * %h + %h", x, y, z);
|
||||
$display(" result = %h (%h expected)", result, rexpected);
|
||||
errors = errors + 1;
|
||||
end
|
||||
vectornum = vectornum + 1;
|
||||
if (testvectors[vectornum] === 'x) begin
|
||||
$display("%d tests completed with %d errors",
|
||||
vectornum, errors);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,130 +0,0 @@
|
||||
#!/usr/bin/perl -w
|
||||
# torturegen.pl
|
||||
# David_Harris@hmc.edu 19 April 2022
|
||||
# Convert TestFloat cases into format for fma16 project torture test
|
||||
# Strip out cases involving denorms
|
||||
|
||||
use strict;
|
||||
|
||||
my @basenames = ("add", "mul", "mulAdd");
|
||||
my @roundingmodes = ("rz", "rd", "ru", "rne");
|
||||
my @names = ();
|
||||
foreach my $name (@basenames) {
|
||||
foreach my $mode (@roundingmodes) {
|
||||
push(@names, "f16_${name}_$mode.tv");
|
||||
}
|
||||
}
|
||||
|
||||
open(TORTURE, ">work/torture.tv") || die("Can't write torture.tv");
|
||||
my $datestring = localtime();
|
||||
print(TORTURE "// Torture tests generated $datestring by $0\n");
|
||||
foreach my $tv (@names) {
|
||||
open(TV, "work/$tv") || die("Can't read $tv");
|
||||
my $type = &getType($tv); # is it mul, add, mulAdd
|
||||
my $rm = &getRm($tv); # rounding mode
|
||||
# if ($rm != 0) { next; } # only do rz
|
||||
print (TORTURE "\n////////// Testcases from $tv of type $type rounding mode $rm\n");
|
||||
print ("\n////////// Testcases from $tv of type $type rounding mode $rm\n");
|
||||
my $linecount = 0;
|
||||
my $babyTorture = 0;
|
||||
while (<TV>) {
|
||||
my $line = $_;
|
||||
$linecount++;
|
||||
my $density = 10;
|
||||
if ($type eq "mulAdd") {$density = 500;}
|
||||
if ($babyTorture) {
|
||||
$density = 100;
|
||||
if ($type eq "mulAdd") {$density = 50000;}
|
||||
}
|
||||
if ((($linecount + $rm) % $density) != 0) { next }; # too many tests to use
|
||||
chomp($line); # strip off newline
|
||||
my @parts = split(/_/, $line);
|
||||
my ($x, $y, $z, $op, $w, $flags);
|
||||
$x = $parts[0];
|
||||
if ($type eq "add") { $y = "0000"; } else {$y = $parts[1]};
|
||||
if ($type eq "mul") { $z = "3CFF"; } elsif ($type eq "add") {$z = $parts[1]} else { $z = $parts[2]};
|
||||
$op = $rm << 4;
|
||||
if ($type eq "mul" || $type eq "mulAdd") { $op = $op + 8; }
|
||||
if ($type eq "add" || $type eq "mulAdd") { $op = $op + 4; }
|
||||
my $opname = sprintf("%02x", $op);
|
||||
if ($type eq "mulAdd") {$w = $parts[3];} else {$w = $parts[2]};
|
||||
if ($type eq "mulAdd") {$flags = $parts[4];} else {$flags = $parts[3]};
|
||||
$flags = substr($flags, -1); # take last character
|
||||
if (&fpval($w) eq "NaN") { $w = "7e00"; }
|
||||
my $vec = "${x}_${y}_${z}_${opname}_${w}_${flags}";
|
||||
my $skip = "";
|
||||
if (&isdenorm($x) || &isdenorm($y) || &isdenorm($z) || &isdenorm($w)) {
|
||||
$skip = "Skipped denorm";
|
||||
}
|
||||
my $summary = &summary($x, $y, $z, $w, $type);
|
||||
if ($skip ne "") {
|
||||
print TORTURE "// $skip $tv line $linecount $line $summary\n"
|
||||
}
|
||||
else { print TORTURE "$vec // $tv line $linecount $line $summary\n";}
|
||||
}
|
||||
close(TV);
|
||||
}
|
||||
close(TORTURE);
|
||||
|
||||
sub fpval {
|
||||
my $val = shift;
|
||||
$val = hex($val); # convert hex string to number
|
||||
my $frac = $val & 0x3FF;
|
||||
my $exp = ($val >> 10) & 0x1F;
|
||||
my $sign = $val >> 15;
|
||||
|
||||
my $res;
|
||||
if ($exp == 31 && $frac != 0) { return "NaN"; }
|
||||
elsif ($exp == 31) { $res = "INF"; }
|
||||
elsif ($val == 0) { $res = 0; }
|
||||
elsif ($exp == 0) { $res = "Denorm"; }
|
||||
else { $res = sprintf("1.%011b x 2^%d", $frac, $exp-15); }
|
||||
|
||||
if ($sign == 1) { $res = "-$res"; }
|
||||
return $res;
|
||||
}
|
||||
|
||||
sub summary {
|
||||
my $x = shift; my $y = shift; my $z = shift; my $w = shift; my $type = shift;
|
||||
|
||||
my $xv = &fpval($x);
|
||||
my $yv = &fpval($y);
|
||||
my $zv = &fpval($z);
|
||||
my $wv = &fpval($w);
|
||||
|
||||
if ($type eq "add") { return "$xv + $zv = $wv"; }
|
||||
elsif ($type eq "mul") { return "$xv * $yv = $wv"; }
|
||||
else {return "$xv * $yv + $zv = $wv"; }
|
||||
}
|
||||
|
||||
sub getType {
|
||||
my $tv = shift;
|
||||
|
||||
if ($tv =~ /mulAdd/) { return("mulAdd"); }
|
||||
elsif ($tv =~ /mul/) { return "mul"; }
|
||||
else { return "add"; }
|
||||
}
|
||||
|
||||
sub getRm {
|
||||
my $tv = shift;
|
||||
|
||||
if ($tv =~ /rz/) { return 0; }
|
||||
elsif ($tv =~ /rne/) { return 1; }
|
||||
elsif ($tv =~ /rd/) {return 2; }
|
||||
elsif ($tv =~ /ru/) { return 3; }
|
||||
else { return "bad"; }
|
||||
}
|
||||
|
||||
sub isdenorm {
|
||||
my $fp = shift;
|
||||
my $val = hex($fp);
|
||||
my $expv = $val >> 10;
|
||||
$expv = $expv & 0x1F;
|
||||
my $denorm = 0;
|
||||
if ($expv == 0 && $val != 0) { $denorm = 1;}
|
||||
# my $e0 = ($expv == 0);
|
||||
# my $vn0 = ($val != 0);
|
||||
# my $denorm = 0; #($exp == 0 && $val != 0); # denorm exponent but not all zero
|
||||
# print("Num $fp Exp $expv Denorm $denorm Done\n");
|
||||
return $denorm;
|
||||
}
|
||||
@ -1,62 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /testbench_fma16/clk
|
||||
add wave -noupdate /testbench_fma16/reset
|
||||
add wave -noupdate /testbench_fma16/x
|
||||
add wave -noupdate /testbench_fma16/y
|
||||
add wave -noupdate /testbench_fma16/z
|
||||
add wave -noupdate /testbench_fma16/result
|
||||
add wave -noupdate /testbench_fma16/rexpected
|
||||
add wave -noupdate /testbench_fma16/dut/x
|
||||
add wave -noupdate /testbench_fma16/dut/y
|
||||
add wave -noupdate /testbench_fma16/dut/z
|
||||
add wave -noupdate /testbench_fma16/dut/mul
|
||||
add wave -noupdate /testbench_fma16/dut/add
|
||||
add wave -noupdate /testbench_fma16/dut/negr
|
||||
add wave -noupdate /testbench_fma16/dut/negz
|
||||
add wave -noupdate /testbench_fma16/dut/roundmode
|
||||
add wave -noupdate /testbench_fma16/dut/result
|
||||
add wave -noupdate /testbench_fma16/dut/XManE
|
||||
add wave -noupdate /testbench_fma16/dut/YManE
|
||||
add wave -noupdate /testbench_fma16/dut/ZManE
|
||||
add wave -noupdate /testbench_fma16/dut/XExpE
|
||||
add wave -noupdate /testbench_fma16/dut/YExpE
|
||||
add wave -noupdate /testbench_fma16/dut/ZExpE
|
||||
add wave -noupdate /testbench_fma16/dut/PExpE
|
||||
add wave -noupdate /testbench_fma16/dut/Ne
|
||||
add wave -noupdate /testbench_fma16/dut/upOneExt
|
||||
add wave -noupdate /testbench_fma16/dut/XSgnE
|
||||
add wave -noupdate /testbench_fma16/dut/YSgnE
|
||||
add wave -noupdate /testbench_fma16/dut/ZSgnE
|
||||
add wave -noupdate /testbench_fma16/dut/PSgnE
|
||||
add wave -noupdate /testbench_fma16/dut/ProdManE
|
||||
add wave -noupdate /testbench_fma16/dut/NfracS
|
||||
add wave -noupdate /testbench_fma16/dut/ProdManAl
|
||||
add wave -noupdate /testbench_fma16/dut/ZManExt
|
||||
add wave -noupdate /testbench_fma16/dut/ZManAl
|
||||
add wave -noupdate /testbench_fma16/dut/Nfrac
|
||||
add wave -noupdate /testbench_fma16/dut/res
|
||||
add wave -noupdate -radix decimal /testbench_fma16/dut/AlignCnt
|
||||
add wave -noupdate /testbench_fma16/dut/NSamt
|
||||
add wave -noupdate /testbench_fma16/dut/ZExpGreater
|
||||
add wave -noupdate /testbench_fma16/dut/ACLess
|
||||
add wave -noupdate /testbench_fma16/dut/upOne
|
||||
add wave -noupdate /testbench_fma16/dut/KillProd
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {3746 ns} 1} {{Cursor 2} {4169 ns} 0}
|
||||
quietly wave cursor active 2
|
||||
configure wave -namecolwidth 237
|
||||
configure wave -valuecolwidth 64
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {4083 ns} {4235 ns}
|
||||
@ -8,7 +8,7 @@ module fclassify (
|
||||
input logic XDenormE, // is denormal
|
||||
input logic XZeroE, // is zero
|
||||
input logic XInfE, // is infinity
|
||||
output logic [63:0] ClassResE // classify result
|
||||
output logic [`XLEN-1:0] ClassResE // classify result
|
||||
);
|
||||
|
||||
logic PInf, PZero, PNorm, PDenorm;
|
||||
@ -37,6 +37,6 @@ module fclassify (
|
||||
// bit 7 - +Inf
|
||||
// bit 8 - signaling NaN
|
||||
// bit 9 - quiet NaN
|
||||
assign ClassResE = {{54{1'b0}}, XNaNE&~XSNaNE, XSNaNE, PInf, PNorm, PDenorm, PZero, NZero, NDenorm, NNorm, NInf};
|
||||
assign ClassResE = {{`XLEN-10{1'b0}}, XNaNE&~XSNaNE, XSNaNE, PInf, PNorm, PDenorm, PZero, NZero, NDenorm, NNorm, NInf};
|
||||
|
||||
endmodule
|
||||
|
||||
@ -10,7 +10,7 @@
|
||||
|
||||
|
||||
module fcmp (
|
||||
input logic [`FPSIZES/3:0] FmtE, // precision 1 = double 0 = single
|
||||
input logic [`FMTBITS-1:0] FmtE, // precision 1 = double 0 = single
|
||||
input logic [2:0] FOpCtrlE, // see above table
|
||||
input logic XSgnE, YSgnE, // input signs
|
||||
input logic [`NE-1:0] XExpE, YExpE, // input exponents
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fctrl (
|
||||
input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision
|
||||
@ -13,7 +14,7 @@ module fctrl (
|
||||
output logic [2:0] FOpCtrlD, // chooses which opperation to do - specifics shown at bottom of module and in each unit
|
||||
output logic [1:0] FResSelD, // select one of the results done in the memory stage
|
||||
output logic [1:0] FIntResSelD, // select the result that will be written to the integer register
|
||||
output logic FmtD, // precision - single-0 double-1
|
||||
output logic [`FMTBITS-1:0] FmtD, // precision - single-0 double-1
|
||||
output logic [2:0] FrmD, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
|
||||
output logic FWriteIntD // is the result written to the integer register
|
||||
);
|
||||
@ -72,14 +73,12 @@ module fctrl (
|
||||
2'b01: ControlsD = `FCTRLW'b1_0_11_100_11_00_0_0; // fcvt.s.wu wu->s
|
||||
2'b10: ControlsD = `FCTRLW'b1_0_11_111_11_00_0_0; // fcvt.s.l l->s
|
||||
2'b11: ControlsD = `FCTRLW'b1_0_11_110_11_00_0_0; // fcvt.s.lu lu->s
|
||||
default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction
|
||||
endcase
|
||||
7'b1100000: case(Rs2D[1:0])
|
||||
2'b00: ControlsD = `FCTRLW'b0_1_11_001_11_11_0_0; // fcvt.w.s s->w
|
||||
2'b01: ControlsD = `FCTRLW'b0_1_11_000_11_11_0_0; // fcvt.wu.s s->wu
|
||||
2'b10: ControlsD = `FCTRLW'b0_1_11_011_11_11_0_0; // fcvt.l.s s->l
|
||||
2'b11: ControlsD = `FCTRLW'b0_1_11_010_11_11_0_0; // fcvt.lu.s s->lu
|
||||
default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction
|
||||
endcase
|
||||
7'b1111000: ControlsD = `FCTRLW'b1_0_11_000_00_00_0_0; // fmv.w.x
|
||||
7'b0100000: ControlsD = `FCTRLW'b1_0_11_000_11_00_0_0; // fcvt.s.d
|
||||
@ -88,14 +87,12 @@ module fctrl (
|
||||
2'b01: ControlsD = `FCTRLW'b1_0_11_100_11_00_0_0; // fcvt.d.wu wu->d
|
||||
2'b10: ControlsD = `FCTRLW'b1_0_11_111_11_00_0_0; // fcvt.d.l l->d
|
||||
2'b11: ControlsD = `FCTRLW'b1_0_11_110_11_00_0_0; // fcvt.d.lu lu->d
|
||||
default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction
|
||||
endcase
|
||||
7'b1100001: case(Rs2D[1:0])
|
||||
2'b00: ControlsD = `FCTRLW'b0_1_11_001_11_11_0_0; // fcvt.w.d d->w
|
||||
2'b01: ControlsD = `FCTRLW'b0_1_11_000_11_11_0_0; // fcvt.wu.d d->wu
|
||||
2'b10: ControlsD = `FCTRLW'b0_1_11_011_11_11_0_0; // fcvt.l.d d->l
|
||||
2'b11: ControlsD = `FCTRLW'b0_1_11_010_11_11_0_0; // fcvt.lu.d d->lu
|
||||
default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction
|
||||
endcase
|
||||
7'b1111001: ControlsD = `FCTRLW'b1_0_11_001_00_00_0_0; // fmv.d.x
|
||||
7'b0100001: ControlsD = `FCTRLW'b1_0_11_001_11_00_0_0; // fcvt.d.s
|
||||
@ -119,8 +116,18 @@ module fctrl (
|
||||
// Precision
|
||||
// 0-single
|
||||
// 1-double
|
||||
assign FmtD = FResultSelD == 2'b00 ? Funct3D[0] : ((Funct7D[6:3] == 4'b0100)&OpD[4]) | OpD[6:1] == 6'b010000 ? ~Funct7D[0] : Funct7D[0];
|
||||
|
||||
if (`FPSIZES == 1)
|
||||
assign FmtD = 0;
|
||||
else if (`FPSIZES == 2)begin
|
||||
logic [1:0] FmtTmp;
|
||||
assign FmtTmp = (FResultSelD == 2'b00) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
|
||||
assign FmtD = `FMT == FmtTmp;
|
||||
end
|
||||
else if (`FPSIZES == 3|`FPSIZES == 4)
|
||||
assign FmtD = (FResultSelD == 2'b00) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
|
||||
|
||||
// assign FmtD = FResultSelD == 2'b00 ? Funct3D[0] : ((Funct7D[6:3] == 4'b0100)&OpD[4]) | OpD[6:1] == 6'b010000 ? ~Funct7D[0] : Funct7D[0];
|
||||
// FResultSel:
|
||||
// 000 - ReadRes - load
|
||||
// 001 - FMARes - FMA and multiply
|
||||
|
||||
@ -16,7 +16,7 @@ module fcvt (
|
||||
input logic XNaNE, // is the input a NaN
|
||||
input logic XSNaNE, // is the input a signaling NaN
|
||||
input logic [2:0] FrmE, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
|
||||
input logic [`FPSIZES/3:0] FmtE, // the input's precision (11=quad 01=double 00=single 10=half)
|
||||
input logic [`FMTBITS-1:0] FmtE, // the input's precision (11=quad 01=double 00=single 10=half)
|
||||
output logic [`FLEN-1:0] CvtResE, // the fp conversion result
|
||||
output logic [`XLEN-1:0] CvtIntResE, // the int conversion result
|
||||
output logic [4:0] CvtFlgE // the conversion's flags
|
||||
@ -37,7 +37,7 @@ module fcvt (
|
||||
// (FI) fp -> int coversion signals
|
||||
|
||||
|
||||
logic [`FPSIZES/3:0] OutFmt; // format of the output
|
||||
logic [`FMTBITS-1:0] OutFmt; // format of the output
|
||||
logic [`XLEN-1:0] PosInt; // the positive integer input
|
||||
logic [`XLEN-1:0] TrimInt; // integer trimmed to the correct size
|
||||
logic [`LGLEN-1:0] LzcIn; // input to the Leading Zero Counter (priority encoder)
|
||||
|
||||
@ -34,7 +34,7 @@ module fma(
|
||||
input logic reset,
|
||||
input logic FlushM, // flush the memory stage
|
||||
input logic StallM, // stall memory stage
|
||||
input logic [`FPSIZES/3:0] FmtE, FmtM, // precision 1 = double 0 = single
|
||||
input logic [`FMTBITS-1:0] FmtE, FmtM, // precision 1 = double 0 = single
|
||||
input logic [2:0] FOpCtrlE, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
|
||||
input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
|
||||
input logic XSgnE, YSgnE, ZSgnE, // input signs - execute stage
|
||||
@ -102,7 +102,7 @@ module fma1(
|
||||
input logic [`NF:0] XManE, YManE, ZManE, // fractions in U(0.NF) format
|
||||
input logic XZeroE, YZeroE, ZZeroE, // is the input zero
|
||||
input logic [2:0] FOpCtrlE, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
|
||||
input logic [`FPSIZES/3:0] FmtE, // precision 1 = double 0 = single
|
||||
input logic [`FMTBITS-1:0] FmtE, // precision 1 = double 0 = single
|
||||
output logic [`NE+1:0] ProdExpE, // X exponent + Y exponent - bias in B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
|
||||
output logic AddendStickyE, // sticky bit that is calculated during alignment
|
||||
output logic KillProdE, // set the product to zero before addition if the product is too small to matter
|
||||
@ -161,7 +161,7 @@ endmodule
|
||||
|
||||
|
||||
module expadd(
|
||||
input logic [`FPSIZES/3:0] FmtE, // precision
|
||||
input logic [`FMTBITS-1:0] FmtE, // precision
|
||||
input logic [`NE-1:0] XExpE, YExpE, // input exponents
|
||||
input logic XZeroE, YZeroE, // are the inputs zero
|
||||
output logic [`NE+1:0] ProdExpE // product's exponent B^(1023)NE+2
|
||||
@ -378,7 +378,7 @@ module fma2(
|
||||
input logic [`NE-1:0] ZExpM, // input exponents
|
||||
input logic [`NF:0] XManM, YManM, ZManM, // input mantissas
|
||||
input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
|
||||
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single
|
||||
input logic [`FMTBITS-1:0] FmtM, // precision 1 = double 0 = single
|
||||
input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias
|
||||
input logic AddendStickyM, // sticky bit that is calculated during alignment
|
||||
input logic KillProdM, // set the product to zero before addition if the product is too small to matter
|
||||
@ -517,7 +517,7 @@ module normalize(
|
||||
input logic [`NE-1:0] ZExpM, // exponent of Z
|
||||
input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias
|
||||
input logic [$clog2(3*`NF+7)-1:0] NormCntM, // normalization shift count
|
||||
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single
|
||||
input logic [`FMTBITS-1:0] FmtM, // precision 1 = double 0 = single
|
||||
input logic KillProdM, // is the product set to zero
|
||||
input logic ZDenormM,
|
||||
input logic AddendStickyM, // the sticky bit caclulated from the aligned addend
|
||||
@ -681,7 +681,7 @@ module normalize(
|
||||
endmodule
|
||||
|
||||
module fmaround(
|
||||
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single
|
||||
input logic [`FMTBITS-1:0] FmtM, // precision 1 = double 0 = single
|
||||
input logic [2:0] FrmM, // rounding mode
|
||||
input logic UfSticky, // sticky bit for underlow calculation
|
||||
input logic [`NF+1:0] NormSum, // normalized sum
|
||||
@ -920,7 +920,7 @@ module fmaflags(
|
||||
input logic [`NE+1:0] SumExp, // exponent of the normalized sum
|
||||
input logic ZSgnEffM, PSgnM, // the product and modified Z signs
|
||||
input logic Round, Guard, UfLSBNormSum, Sticky, UfPlus1, // bits used to determine rounding
|
||||
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single
|
||||
input logic [`FMTBITS-1:0] FmtM, // precision 1 = double 0 = single
|
||||
output logic Invalid, Overflow, Underflow, // flags used to select the result
|
||||
output logic [4:0] FMAFlgM // FMA flags
|
||||
);
|
||||
@ -996,7 +996,7 @@ module resultselect(
|
||||
input logic [`NE-1:0] ZExpM, // input exponents
|
||||
input logic [`NF:0] XManM, YManM, ZManM, // input mantissas
|
||||
input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
|
||||
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single
|
||||
input logic [`FMTBITS-1:0] FmtM, // precision 1 = double 0 = single
|
||||
input logic AddendStickyM, // sticky bit that is calculated during alignment
|
||||
input logic KillProdM, // set the product to zero before addition if the product is too small to matter
|
||||
input logic XInfM, YInfM, ZInfM, // inputs are infinity
|
||||
|
||||
@ -65,7 +65,7 @@ module fpu (
|
||||
// control signals
|
||||
logic FRegWriteD, FRegWriteE, FRegWriteW; // FP register write enable
|
||||
logic [2:0] FrmD, FrmE, FrmM; // FP rounding mode
|
||||
logic FmtD, FmtE, FmtM, FmtW; // FP precision 0-single 1-double
|
||||
logic [`FMTBITS-1:0] FmtD, FmtE, FmtM, FmtW; // FP precision 0-single 1-double
|
||||
logic FDivStartD, FDivStartE; // Start division or squareroot
|
||||
logic FWriteIntD; // Write to integer register
|
||||
logic [1:0] FForwardXE, FForwardYE, FForwardZE; // forwarding mux control signals
|
||||
@ -77,19 +77,19 @@ module fpu (
|
||||
logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input
|
||||
|
||||
// regfile signals
|
||||
logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
|
||||
logic [63:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
|
||||
logic [63:0] FSrcXE; // Input 1 to the various units (after forwarding)
|
||||
logic [63:0] FPreSrcYE, FSrcYE; // Input 2 to the various units (after forwarding)
|
||||
logic [63:0] FPreSrcZE, FSrcZE; // Input 3 to the various units (after forwarding)
|
||||
logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
|
||||
logic [`FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
|
||||
logic [`FLEN-1:0] FSrcXE; // Input 1 to the various units (after forwarding)
|
||||
logic [`FLEN-1:0] FPreSrcYE, FSrcYE; // Input 2 to the various units (after forwarding)
|
||||
logic [`FLEN-1:0] FPreSrcZE, FSrcZE; // Input 3 to the various units (after forwarding)
|
||||
|
||||
// unpacking signals
|
||||
logic XSgnE, YSgnE, ZSgnE; // input's sign - execute stage
|
||||
logic XSgnM, YSgnM; // input's sign - memory stage
|
||||
logic [10:0] XExpE, YExpE, ZExpE; // input's exponent - execute stage
|
||||
logic [10:0] ZExpM; // input's exponent - memory stage
|
||||
logic [52:0] XManE, YManE, ZManE; // input's fraction - execute stage
|
||||
logic [52:0] XManM, YManM, ZManM; // input's fraction - memory stage
|
||||
logic [`NE-1:0] XExpE, YExpE, ZExpE; // input's exponent - execute stage
|
||||
logic [`NE-1:0] ZExpM; // input's exponent - memory stage
|
||||
logic [`NF:0] XManE, YManE, ZManE; // input's fraction - execute stage
|
||||
logic [`NF:0] XManM, YManM, ZManM; // input's fraction - memory stage
|
||||
logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
|
||||
logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
|
||||
logic XNaNQ, YNaNQ; // is the input a NaN - divide
|
||||
@ -107,28 +107,29 @@ module fpu (
|
||||
logic FOpCtrlQ;
|
||||
|
||||
// result and flag signals
|
||||
logic [63:0] FDivResM, FDivResW; // divide/squareroot result
|
||||
logic [`FLEN-1:0] FDivResM, FDivResW; // divide/squareroot result
|
||||
logic [4:0] FDivFlgM; // divide/squareroot flags
|
||||
logic [63:0] FMAResM, FMAResW; // FMA/multiply result
|
||||
logic [`FLEN-1:0] FMAResM, FMAResW; // FMA/multiply result
|
||||
logic [4:0] FMAFlgM; // FMA/multiply result
|
||||
logic [63:0] ReadResW; // read result (load instruction)
|
||||
logic [63:0] CvtResE; // FP <-> int convert result
|
||||
logic [`FLEN-1:0] ReadResW; // read result (load instruction)
|
||||
logic [`FLEN-1:0] CvtResE; // FP <-> int convert result
|
||||
logic [`XLEN-1:0] CvtIntResE; // FP <-> int convert result
|
||||
logic [4:0] CvtFlgE; // FP <-> int convert flags //*** trim this
|
||||
logic [63:0] ClassResE; // classify result
|
||||
logic [63:0] CmpResE; // compare result
|
||||
logic [`XLEN-1:0] ClassResE; // classify result
|
||||
logic [`FLEN-1:0] CmpResE; // compare result
|
||||
logic CmpNVE; // compare invalid flag (Not Valid)
|
||||
logic [63:0] SgnResE; // sign injection result
|
||||
logic [63:0] FResE, FResM, FResW; // selected result that is ready in the memory stage
|
||||
logic [`FLEN-1:0] SgnResE; // sign injection result
|
||||
logic [`FLEN-1:0] FResE, FResM, FResW; // selected result that is ready in the memory stage
|
||||
logic [4:0] FFlgE, FFlgM; // selected flag that is ready in the memory stage
|
||||
logic [`XLEN-1:0] FIntResE;
|
||||
logic [63:0] FPUResultW; // final FP result being written to the FP register
|
||||
logic [`FLEN-1:0] FPUResultW; // final FP result being written to the FP register
|
||||
// other signals
|
||||
logic FDivSqrtDoneE; // is divide done
|
||||
logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit
|
||||
logic [`FLEN-1:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit
|
||||
logic load_preload; // enable for FF on fpdivsqrt
|
||||
logic [63:0] AlignedSrcAE; // align SrcA to the floating point format
|
||||
logic [63:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed
|
||||
logic [`FLEN-1:0] AlignedSrcAE; // align SrcA to the floating point format
|
||||
logic [`FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed
|
||||
logic [`FLEN-1:0] BoxedOneE; // Zero value for Z for multiplication, with NaN boxing if needed
|
||||
|
||||
// DECODE STAGE
|
||||
|
||||
@ -144,12 +145,12 @@ module fpu (
|
||||
.rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));
|
||||
|
||||
// D/E pipeline registers
|
||||
flopenrc #(64) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
|
||||
flopenrc #(64) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
|
||||
flopenrc #(64) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
|
||||
flopenrc #(`FLEN) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
|
||||
flopenrc #(`FLEN) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
|
||||
flopenrc #(`FLEN) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
|
||||
flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]},
|
||||
{Adr1E, Adr2E, Adr3E});
|
||||
flopenrc #(16) DECtrlReg3(clk, reset, FlushE, ~StallE,
|
||||
flopenrc #(16+int'(`FMTBITS-1)) DECtrlReg3(clk, reset, FlushE, ~StallE,
|
||||
{FRegWriteD, FResultSelD, FResSelD, FIntResSelD, FrmD, FmtD, FOpCtrlD, FWriteIntD, FDivStartD},
|
||||
{FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE, FDivStartE});
|
||||
|
||||
@ -160,17 +161,39 @@ module fpu (
|
||||
.FStallD, .FForwardXE, .FForwardYE, .FForwardZE);
|
||||
|
||||
// forwarding muxs
|
||||
mux3 #(64) fxemux (FRD1E, FPUResultW, FResM, FForwardXE, FSrcXE);
|
||||
mux3 #(64) fyemux (FRD2E, FPUResultW, FResM, FForwardYE, FPreSrcYE);
|
||||
mux3 #(64) fzemux (FRD3E, FPUResultW, FResM, FForwardZE, FPreSrcZE);
|
||||
mux3 #(64) fyaddmux (FPreSrcYE, {{32{1'b1}}, 2'b0, {7{1'b1}}, 23'b0},
|
||||
{2'b0, {10{1'b1}}, 52'b0},
|
||||
{FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01), ~FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01)},
|
||||
FSrcYE); // Force Z to be 0 for multiply instructions
|
||||
mux3 #(`FLEN) fxemux (FRD1E, FPUResultW, FResM, FForwardXE, FSrcXE);
|
||||
mux3 #(`FLEN) fyemux (FRD2E, FPUResultW, FResM, FForwardYE, FPreSrcYE);
|
||||
mux3 #(`FLEN) fzemux (FRD3E, FPUResultW, FResM, FForwardZE, FPreSrcZE);
|
||||
|
||||
|
||||
generate
|
||||
if(`FPSIZES == 1) assign BoxedOneE = {2'b0, {`NE-1{1'b1}}, (`NF)'(0)};
|
||||
else if(`FPSIZES == 2)
|
||||
mux2 #(`FLEN) fonemux ({{`FLEN-`LEN1{1'b1}}, 2'b0, {`NE1-1{1'b1}}, (`NF1)'(0)}, {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
|
||||
else if(`FPSIZES == 3 | `FPSIZES == 4)
|
||||
mux4 #(`FLEN) fonemux ({{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)},
|
||||
{{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)},
|
||||
{{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)},
|
||||
{2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
|
||||
endgenerate
|
||||
|
||||
|
||||
mux2 #(`FLEN) fyaddmux (FPreSrcYE, BoxedOneE, FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01), FSrcYE); // Force Z to be 0 for multiply instructions
|
||||
|
||||
// Force Z to be 0 for multiply instructions
|
||||
mux2 #(64) fmulzeromux (64'hFFFFFFFF00000000, 64'b0, FmtE, BoxedZeroE); // NaN boxing for 32-bit zero
|
||||
mux3 #(64) fzmulmux (FPreSrcZE, BoxedZeroE, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE);
|
||||
|
||||
generate
|
||||
if(`FPSIZES == 1) assign BoxedZeroE = 0;
|
||||
else if(`FPSIZES == 2)
|
||||
mux2 #(`FLEN) fmulzeromux ({{`FLEN-`LEN1{1'b1}}, {`FLEN-`LEN1{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
|
||||
else if(`FPSIZES == 3 | `FPSIZES == 4)
|
||||
mux4 #(`FLEN) fmulzeromux ({{`FLEN-`S_LEN{1'b1}}, (`FLEN-`S_LEN)'(0)},
|
||||
{{`FLEN-`D_LEN{1'b1}}, (`FLEN-`D_LEN)'(0)},
|
||||
{{`FLEN-`H_LEN{1'b1}}, (`FLEN-`H_LEN)'(0)},
|
||||
(`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
|
||||
endgenerate
|
||||
|
||||
mux3 #(`FLEN) fzmulmux (FPreSrcZE, BoxedZeroE, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE);
|
||||
|
||||
// unpack unit
|
||||
// - splits FP inputs into their various parts
|
||||
// - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity)
|
||||
@ -195,13 +218,13 @@ module fpu (
|
||||
.FMAFlgM, .FMAResM);
|
||||
|
||||
// fpdivsqrt using Goldschmidt's iteration
|
||||
flopenrc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E),
|
||||
flopenrc #(`FLEN) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E),
|
||||
.clear(FDivSqrtDoneE), .en(load_preload),
|
||||
.reset(reset), .clk(clk));
|
||||
flopenrc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
|
||||
flopenrc #(`FLEN) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
|
||||
.clear(FDivSqrtDoneE), .en(load_preload),
|
||||
.reset(reset), .clk(clk));
|
||||
flopenrc #(8) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE, FOpCtrlE[0]}),
|
||||
flopenrc #(8+int'(`FMTBITS-1)) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE, FOpCtrlE[0]}),
|
||||
.q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ, FOpCtrlQ}),
|
||||
.clear(FDivSqrtDoneE), .en(load_preload),
|
||||
.reset(reset), .clk(clk));
|
||||
@ -223,15 +246,23 @@ module fpu (
|
||||
// - if there are any unsused bits the most significant bits are filled with 1s
|
||||
assign FWriteDataE = FSrcYE[`XLEN-1:0];
|
||||
|
||||
// Align SrcA to MSB when single precicion
|
||||
mux2 #(64) SrcAMux({{32{1'b1}}, ForwardedSrcAE[31:0]}, {{64-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
|
||||
|
||||
// NaN Block SrcA
|
||||
generate
|
||||
if(`FPSIZES == 1) assign AlignedSrcAE = {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE};
|
||||
else if(`FPSIZES == 2)
|
||||
mux2 #(`FLEN) SrcAMux ({{`FLEN-`LEN1{1'b1}}, ForwardedSrcAE[`LEN1-1:0]}, {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
|
||||
else if(`FPSIZES == 3 | `FPSIZES == 4)
|
||||
mux4 #(`FLEN) SrcAMux ({{`FLEN-`S_LEN{1'b1}}, ForwardedSrcAE[`S_LEN-1:0]},
|
||||
{{`FLEN-`D_LEN{1'b1}}, ForwardedSrcAE[`D_LEN-1:0]},
|
||||
{{`FLEN-`H_LEN{1'b1}}, ForwardedSrcAE[`H_LEN-1:0]},
|
||||
{{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // NaN boxing zeroes
|
||||
endgenerate
|
||||
// select a result that may be written to the FP register
|
||||
mux4 #(64) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, FResSelE, FResE);
|
||||
mux4 #(`FLEN) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, FResSelE, FResE);
|
||||
mux4 #(5) FFlgMux(5'b0, 5'b0, {CmpNVE, 4'b0}, CvtFlgE, FResSelE, FFlgE);
|
||||
|
||||
// select the result that may be written to the integer register - to IEU
|
||||
mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE[`XLEN-1:0],
|
||||
mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE,
|
||||
CvtIntResE, FIntResSelE, FIntResE);
|
||||
// *** DH 5/25/22: CvtRes will move to mem stage. Premux in execute to save area, then make sure stalls are ok
|
||||
// *** make sure the fpu matches the chapter diagram
|
||||
@ -239,16 +270,16 @@ module fpu (
|
||||
// E/M pipe registers
|
||||
|
||||
// flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FSrcXE, FSrcXM);
|
||||
flopenrc #(54) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XManE}, {XSgnM,XManM});
|
||||
flopenrc #(54) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YManE}, {YSgnM,YManM});
|
||||
flopenrc #(64) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM});
|
||||
flopenrc #(`NF+2) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XManE}, {XSgnM,XManM});
|
||||
flopenrc #(`NF+2) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YManE}, {YSgnM,YManM});
|
||||
flopenrc #(`FLEN) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM});
|
||||
flopenrc #(12) EMFpReg5 (clk, reset, FlushM, ~StallM,
|
||||
{XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
|
||||
{XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});
|
||||
flopenrc #(64) EMRegCmpRes (clk, reset, FlushM, ~StallM, FResE, FResM);
|
||||
flopenrc #(`FLEN) EMRegCmpRes (clk, reset, FlushM, ~StallM, FResE, FResM);
|
||||
flopenrc #(5) EMRegCmpFlg (clk, reset, FlushM, ~StallM, FFlgE, FFlgM);
|
||||
flopenrc #(`XLEN) EMRegSgnRes (clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
|
||||
flopenrc #(7) EMCtrlReg (clk, reset, FlushM, ~StallM,
|
||||
flopenrc #(7+int'(`FMTBITS-1)) EMCtrlReg (clk, reset, FlushM, ~StallM,
|
||||
{FRegWriteE, FResultSelE, FrmE, FmtE},
|
||||
{FRegWriteM, FResultSelM, FrmM, FmtM});
|
||||
|
||||
@ -258,10 +289,10 @@ module fpu (
|
||||
mux4 #(5) FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelM, SetFflagsM);
|
||||
|
||||
// M/W pipe registers
|
||||
flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW);
|
||||
flopenrc #(64) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW);
|
||||
flopenrc #(64) MWRegClass(clk, reset, FlushW, ~StallW, FResM, FResW);
|
||||
flopenrc #(4) MWCtrlReg(clk, reset, FlushW, ~StallW,
|
||||
flopenrc #(`FLEN) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW);
|
||||
flopenrc #(`FLEN) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW);
|
||||
flopenrc #(`FLEN) MWRegClass(clk, reset, FlushW, ~StallW, FResM, FResW);
|
||||
flopenrc #(4+int'(`FMTBITS-1)) MWCtrlReg(clk, reset, FlushW, ~StallW,
|
||||
{FRegWriteM, FResultSelM, FmtM},
|
||||
{FRegWriteW, FResultSelW, FmtW});
|
||||
|
||||
@ -270,8 +301,17 @@ module fpu (
|
||||
// put ReadData into NaN-blocking format
|
||||
// - if there are any unsused bits the most significant bits are filled with 1s
|
||||
// - for load instruction
|
||||
mux2 #(64) ReadResMux ({{32{1'b1}}, ReadDataW[31:0]}, {{64-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW);
|
||||
generate
|
||||
if(`FPSIZES == 1) assign ReadResW = {{`FLEN-`XLEN{1'b1}}, ReadDataW};
|
||||
else if(`FPSIZES == 2)
|
||||
mux2 #(`FLEN) SrcAMux ({{`FLEN-`LEN1{1'b1}}, ReadDataW[`LEN1-1:0]}, {{`FLEN-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW);
|
||||
else if(`FPSIZES == 3 | `FPSIZES == 4)
|
||||
mux4 #(`FLEN) SrcAMux ({{`FLEN-`S_LEN{1'b1}}, ReadDataW[`S_LEN-1:0]},
|
||||
{{`FLEN-`D_LEN{1'b1}}, ReadDataW[`D_LEN-1:0]},
|
||||
{{`FLEN-`H_LEN{1'b1}}, ReadDataW[`H_LEN-1:0]},
|
||||
{{`FLEN-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW); // NaN boxing zeroes
|
||||
endgenerate
|
||||
|
||||
// select the result to be written to the FP register
|
||||
mux4 #(64) FPUResultMux (ReadResW, FMAResW, FDivResW, FResW, FResultSelW, FPUResultW);
|
||||
mux4 #(`FLEN) FPUResultMux (ReadResW, FMAResW, FDivResW, FResW, FResultSelW, FPUResultW);
|
||||
endmodule // fpu
|
||||
|
||||
@ -33,10 +33,10 @@ module fregfile (
|
||||
input logic clk, reset,
|
||||
input logic we4,
|
||||
input logic [4:0] a1, a2, a3, a4,
|
||||
input logic [63:0] wd4,
|
||||
output logic [63:0] rd1, rd2, rd3);
|
||||
input logic [`FLEN-1:0] wd4,
|
||||
output logic [`FLEN-1:0] rd1, rd2, rd3);
|
||||
|
||||
logic [63:0] rf[31:0];
|
||||
logic [`FLEN-1:0] rf[31:0];
|
||||
integer i;
|
||||
|
||||
// three ported register file
|
||||
|
||||
@ -26,13 +26,14 @@
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
||||
// OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fsgninj (
|
||||
input logic XSgnE, YSgnE, // X and Y sign bits
|
||||
input logic [63:0] FSrcXE, // X
|
||||
input logic FmtE, // precision 1 = double 0 = single
|
||||
input logic [`FLEN-1:0] FSrcXE, // X
|
||||
input logic [`FMTBITS-1:0] FmtE, // precision 1 = double 0 = single
|
||||
input logic [1:0] SgnOpCodeE, // operation control
|
||||
output logic [63:0] SgnResE // result
|
||||
output logic [`FLEN-1:0] SgnResE // result
|
||||
);
|
||||
|
||||
logic ResSgn;
|
||||
@ -50,7 +51,30 @@ module fsgninj (
|
||||
// format final result based on precision
|
||||
// - uses NaN-blocking format
|
||||
// - if there are any unsused bits the most significant bits are filled with 1s
|
||||
assign SgnResE = FmtE ? {ResSgn, FSrcXE[62:0]} : {FSrcXE[63:32], ResSgn, FSrcXE[30:0]};
|
||||
|
||||
if (`FPSIZES == 1)
|
||||
assign SgnResE = {ResSgn, FSrcXE[`FLEN-2:0]};
|
||||
|
||||
else if (`FPSIZES == 2)
|
||||
assign SgnResE = FmtE ? {ResSgn, FSrcXE[`FLEN-2:0]} : {{`FLEN-`LEN1{1'b1}}, ResSgn, FSrcXE[`LEN1-2:0]};
|
||||
|
||||
else if (`FPSIZES == 3)
|
||||
always_comb
|
||||
case (FmtE)
|
||||
`FMT: SgnResE = {ResSgn, FSrcXE[`FLEN-2:0]};
|
||||
`FMT1: SgnResE = {{`FLEN-`LEN1{1'b1}}, ResSgn, FSrcXE[`LEN1-2:0]};
|
||||
`FMT2: SgnResE = {{`FLEN-`LEN2{1'b1}}, ResSgn, FSrcXE[`LEN2-2:0]};
|
||||
default: SgnResE = 0;
|
||||
endcase
|
||||
|
||||
else if (`FPSIZES == 4)
|
||||
always_comb
|
||||
case (FmtE)
|
||||
2'h3: SgnResE = {ResSgn, FSrcXE[`Q_LEN-2:0]};
|
||||
2'h1: SgnResE = {{`Q_LEN-`D_LEN{1'b1}}, ResSgn, FSrcXE[`D_LEN-2:0]};
|
||||
2'h0: SgnResE = {{`Q_LEN-`S_LEN{1'b1}}, ResSgn, FSrcXE[`S_LEN-2:0]};
|
||||
2'h2: SgnResE = {{`Q_LEN-`H_LEN{1'b1}}, ResSgn, FSrcXE[`H_LEN-2:0]};
|
||||
endcase
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module unpack (
|
||||
input logic [`FLEN-1:0] X, Y, Z, // inputs from register file
|
||||
input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half
|
||||
input logic [$signed(`FLEN)-$signed(1):0] X, Y, Z, // inputs from register file
|
||||
input logic [$signed(`FMTBITS)-$signed(1):0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half
|
||||
output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ
|
||||
output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision)
|
||||
output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision)
|
||||
output logic [$signed(`NE)-$signed(1):0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision)
|
||||
output logic [$signed(`NF):0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision)
|
||||
output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN
|
||||
output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN
|
||||
output logic XDenormE, ZDenormE, // is XYZ denormalized
|
||||
@ -14,7 +14,7 @@ module unpack (
|
||||
output logic XExpMaxE // does X have the maximum exponent (NaN or Inf)
|
||||
);
|
||||
|
||||
logic [`NF-1:0] XFracE, YFracE, ZFracE; //Fraction of XYZ
|
||||
logic [$signed(`NF)-$signed(1):0] XFracE, YFracE, ZFracE; //Fraction of XYZ
|
||||
logic XExpNonZero, YExpNonZero, ZExpNonZero; // is the exponent of XYZ non-zero
|
||||
logic XFracZero, YFracZero, ZFracZero; // is the fraction zero
|
||||
logic YExpMaxE, ZExpMaxE; // is the exponent all 1s
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
|
||||
module unpackinput (
|
||||
input logic [`FLEN-1:0] In, // inputs from register file
|
||||
input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half
|
||||
input logic [`FMTBITS-1:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half
|
||||
output logic Sgn, // sign bits of XYZ
|
||||
output logic [`NE-1:0] Exp, // exponents of XYZ (converted to largest supported precision)
|
||||
output logic [`NF:0] Man, // mantissas of XYZ (converted to largest supported precision)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
//leading zero counter i.e. priority encoder
|
||||
module lzc #(parameter WIDTH=1) (
|
||||
module lzc #(parameter WIDTH = 1) (
|
||||
input logic [WIDTH-1:0] num,
|
||||
output logic [$clog2(WIDTH+1)-1:0] ZeroCnt
|
||||
);
|
||||
|
||||
@ -32,13 +32,13 @@
|
||||
|
||||
module hazard(
|
||||
// Detect hazards
|
||||
(* mark_debug = "true" *) input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
|
||||
(* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFencePendingDEM, RetM, TrapM,
|
||||
(* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
|
||||
(* mark_debug = "true" *) input logic LSUStallM, IFUStallF,
|
||||
(* mark_debug = "true" *) input logic FPUStallD, FStallD,
|
||||
(* mark_debug = "true" *) input logic DivBusyE,FDivBusyE,
|
||||
(* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM,
|
||||
(* mark_debug = "true" *) input logic InvalidateICacheM, wfiM, IntPendingM,
|
||||
(* mark_debug = "true" *) input logic wfiM, IntPendingM,
|
||||
// Stall & flush outputs
|
||||
(* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW,
|
||||
(* mark_debug = "true" *) output logic FlushF, FlushD, FlushE, FlushM, FlushW
|
||||
@ -47,7 +47,6 @@ module hazard(
|
||||
logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
|
||||
logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW;
|
||||
|
||||
|
||||
// stalls and flushes
|
||||
// loads: stall for one cycle if the subsequent instruction depends on the load
|
||||
// branches and jumps: flush the next two instructions if the branch is taken in EXE
|
||||
@ -62,7 +61,7 @@ module hazard(
|
||||
|
||||
// *** can stalls be pushed into earlier stages (e.g. no stall after Decode?)
|
||||
|
||||
assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE);
|
||||
assign StallFCause = CSRWriteFencePendingDEM & ~(TrapM | RetM | BPPredWrongE);
|
||||
// stall in decode if instruction is a load/mul/csr dependent on previous
|
||||
assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE);
|
||||
assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?)
|
||||
@ -82,10 +81,10 @@ module hazard(
|
||||
assign FirstUnstalledW = ~StallW & StallM;
|
||||
|
||||
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
|
||||
assign FlushF = BPPredWrongE | InvalidateICacheM;
|
||||
assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE | InvalidateICacheM; // *** does RetM only need to flush if the privilege changes?
|
||||
assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE | InvalidateICacheM; // *** why is BPPredWrongE here, but not needed in simple processor
|
||||
assign FlushM = FirstUnstalledM | TrapM | RetM | InvalidateICacheM;
|
||||
assign FlushF = BPPredWrongE;
|
||||
assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE;
|
||||
assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; // *** why is BPPredWrongE here, but not needed in simple processor
|
||||
assign FlushM = FirstUnstalledM | TrapM | RetM;
|
||||
// on Trap the memory stage should be flushed going into the W stage,
|
||||
// except if the instruction causing the Trap is an ecall or ebreak.
|
||||
assign FlushW = FirstUnstalledW | (TrapM & ~(BreakpointFaultM | EcallFaultM));
|
||||
|
||||
@ -67,7 +67,7 @@ module controller(
|
||||
output logic RegWriteW, // for datapath and Hazard Unit
|
||||
output logic [2:0] ResultSrcW,
|
||||
// Stall during CSRs
|
||||
output logic CSRWritePendingDEM,
|
||||
output logic CSRWriteFencePendingDEM,
|
||||
output logic StoreStallD
|
||||
);
|
||||
|
||||
@ -107,6 +107,8 @@ module controller(
|
||||
logic IEURegWriteE;
|
||||
logic IllegalERegAdrD;
|
||||
logic [1:0] AtomicE;
|
||||
logic FencePendingD, FencePendingE, FencePendingM;
|
||||
|
||||
|
||||
// Extract fields
|
||||
assign OpD = InstrD[6:0];
|
||||
@ -174,10 +176,10 @@ module controller(
|
||||
assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
|
||||
ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD,
|
||||
PrivilegedD, FenceD, MDUD, AtomicD, unused} = IllegalIEUInstrFaultD ? `CTRLW'b0 : ControlsD;
|
||||
// *** move Privileged, CSRwrite?? Or move controller out of IEU into datapath and handle all instructions
|
||||
|
||||
assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
|
||||
assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros
|
||||
assign FencePendingD = PrivilegedD & (InstrD[31:25] == 7'b0001001) | FenceD; // possible sfence.vma or fence.i
|
||||
|
||||
// ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra
|
||||
assign sltD = (Funct3D == 3'b010);
|
||||
@ -204,9 +206,9 @@ module controller(
|
||||
flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
|
||||
|
||||
// Execute stage pipeline control register and logic
|
||||
flopenrc #(27) controlregE(clk, reset, FlushE, ~StallE,
|
||||
{RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, InstrValidD},
|
||||
{IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE});
|
||||
flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE,
|
||||
{RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FencePendingD, InstrValidD},
|
||||
{IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FencePendingE, InstrValidE});
|
||||
|
||||
// Branch Logic
|
||||
assign {eqE, ltE, ltuE} = FlagsE;
|
||||
@ -220,16 +222,17 @@ module controller(
|
||||
assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
|
||||
|
||||
// Memory stage pipeline control register
|
||||
flopenrc #(18) controlregM(clk, reset, FlushM, ~StallM,
|
||||
{RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE},
|
||||
{RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, InstrValidM});
|
||||
flopenrc #(19) controlregM(clk, reset, FlushM, ~StallM,
|
||||
{RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FencePendingE, InstrValidE},
|
||||
{RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FencePendingM, InstrValidM});
|
||||
|
||||
// Writeback stage pipeline control register
|
||||
flopenrc #(4) controlregW(clk, reset, FlushW, ~StallW,
|
||||
{RegWriteM, ResultSrcM},
|
||||
{RegWriteW, ResultSrcW});
|
||||
|
||||
assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM;
|
||||
// Stall pipeline at Fetch if a CSR Write or Fence is pending in the subsequent stages
|
||||
assign CSRWriteFencePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM | FencePendingD | FencePendingE | FencePendingM;
|
||||
|
||||
assign StoreStallD = MemRWE[0] & ((|MemRWD) | (|AtomicD));
|
||||
endmodule
|
||||
|
||||
@ -71,7 +71,7 @@ module ieu (
|
||||
output logic FPUStallD, LoadStallD, MDUStallD, CSRRdStallD,
|
||||
output logic PCSrcE,
|
||||
output logic CSRReadM, CSRWriteM, PrivilegedM,
|
||||
output logic CSRWritePendingDEM,
|
||||
output logic CSRWriteFencePendingDEM,
|
||||
output logic StoreStallD
|
||||
);
|
||||
|
||||
@ -99,7 +99,7 @@ module ieu (
|
||||
.Funct3E, .MDUE, .W64E, .JumpE, .StallM, .FlushM, .MemRWM,
|
||||
.CSRReadM, .CSRWriteM, .PrivilegedM, .SCE, .AtomicM, .Funct3M,
|
||||
.RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM,
|
||||
.StallW, .FlushW, .RegWriteW, .ResultSrcW, .CSRWritePendingDEM, .StoreStallD);
|
||||
.StallW, .FlushW, .RegWriteW, .ResultSrcW, .CSRWriteFencePendingDEM, .StoreStallD);
|
||||
|
||||
datapath dp(
|
||||
.clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
|
||||
|
||||
@ -72,7 +72,7 @@ module ifu (
|
||||
input logic [`XLEN-1:0] SATP_REGW,
|
||||
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
|
||||
input logic [1:0] STATUS_MPP,
|
||||
input logic ITLBWriteF, ITLBFlushF,
|
||||
input logic ITLBWriteF, sfencevmaM,
|
||||
output logic ITLBMissF, InstrDAPageFaultF,
|
||||
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
|
||||
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
|
||||
@ -137,6 +137,18 @@ module ifu (
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
if(`ZICSR_SUPPORTED == 1) begin : immu
|
||||
///////////////////////////////////////////
|
||||
// sfence.vma causes TLB flushes
|
||||
///////////////////////////////////////////
|
||||
// sets ITLBFlush to pulse for one cycle of the sfence.vma instruction
|
||||
// In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program.
|
||||
// But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and
|
||||
// the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush
|
||||
// after a cycle AND pulse it for another cycle on any further back-to-back sfences.
|
||||
logic StallMQ, TLBFlush;
|
||||
flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
|
||||
assign TLBFlush = sfencevmaM & ~StallMQ;
|
||||
|
||||
mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
|
||||
immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
||||
.PrivilegeModeW, .DisableTranslation(1'b0),
|
||||
@ -145,7 +157,7 @@ module ifu (
|
||||
.PTE(PTE),
|
||||
.PageTypeWriteVal(PageType),
|
||||
.TLBWrite(ITLBWriteF),
|
||||
.TLBFlush(ITLBFlushF),
|
||||
.TLBFlush,
|
||||
.PhysicalAddress(PCPF),
|
||||
.TLBMiss(ITLBMissF),
|
||||
.Cacheable(CacheableF), .Idempotent(), .AtomicAllowed(),
|
||||
|
||||
@ -55,7 +55,7 @@ module lsu (
|
||||
// cpu privilege
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
input logic BigEndianM,
|
||||
input logic DTLBFlushM,
|
||||
input logic sfencevmaM,
|
||||
// faults
|
||||
output logic LoadPageFaultM, StoreAmoPageFaultM,
|
||||
output logic LoadMisalignedFaultM, LoadAccessFaultM,
|
||||
@ -157,7 +157,7 @@ module lsu (
|
||||
.PTE,
|
||||
.PageTypeWriteVal(PageType),
|
||||
.TLBWrite(DTLBWriteM),
|
||||
.TLBFlush(DTLBFlushM),
|
||||
.TLBFlush(sfencevmaM),
|
||||
.PhysicalAddress(LSUPAdrM),
|
||||
.TLBMiss(DTLBMissM),
|
||||
.Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(),
|
||||
|
||||
@ -39,7 +39,7 @@ module privdec (
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
input logic STATUS_TSR, STATUS_TVM, STATUS_TW,
|
||||
input logic [1:0] STATUS_FS,
|
||||
output logic IllegalInstrFaultM, ITLBFlushF, DTLBFlushM,
|
||||
output logic IllegalInstrFaultM,
|
||||
output logic EcallFaultM, BreakpointFaultM,
|
||||
output logic sretM, mretM, wfiM, sfencevmaM);
|
||||
|
||||
@ -84,9 +84,9 @@ module privdec (
|
||||
// But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and
|
||||
// the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush
|
||||
// after a cycle AND pulse it for another cycle on any further back-to-back sfences.
|
||||
flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
|
||||
assign ITLBFlushF = sfencevmaM & ~StallMQ;
|
||||
assign DTLBFlushM = sfencevmaM;
|
||||
// flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
|
||||
// assign ITLBFlushF = sfencevmaM & ~StallMQ;
|
||||
// assign DTLBFlushM = sfencevmaM;
|
||||
|
||||
///////////////////////////////////////////
|
||||
// Fault on illegal instructions
|
||||
|
||||
@ -38,7 +38,7 @@ module privileged (
|
||||
output logic [`XLEN-1:0] CSRReadValW,
|
||||
output logic [`XLEN-1:0] PrivilegedNextPCM,
|
||||
output logic RetM, TrapM,
|
||||
output logic ITLBFlushF, DTLBFlushM,
|
||||
output logic sfencevmaM,
|
||||
input logic InstrValidM, CommittedM,
|
||||
input logic FRegWriteM, LoadStallD,
|
||||
input logic BPPredDirWrongM,
|
||||
@ -85,7 +85,7 @@ module privileged (
|
||||
logic [`XLEN-1:0] MEDELEG_REGW;
|
||||
logic [11:0] MIDELEG_REGW;
|
||||
|
||||
logic sretM, mretM, sfencevmaM;
|
||||
logic sretM, mretM;
|
||||
logic IllegalCSRAccessM;
|
||||
logic IllegalIEUInstrFaultM;
|
||||
logic IllegalFPUInstrM;
|
||||
@ -115,7 +115,7 @@ module privileged (
|
||||
privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]),
|
||||
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM,
|
||||
.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .STATUS_FS, .IllegalInstrFaultM,
|
||||
.ITLBFlushF, .DTLBFlushM, .EcallFaultM, .BreakpointFaultM,
|
||||
.EcallFaultM, .BreakpointFaultM,
|
||||
.sretM, .mretM, .wfiM, .sfencevmaM);
|
||||
|
||||
///////////////////////////////////////////
|
||||
|
||||
@ -82,7 +82,7 @@ module wallypipelinedcore (
|
||||
logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
|
||||
logic InvalidateICacheM, FlushDCacheM;
|
||||
logic PCSrcE;
|
||||
logic CSRWritePendingDEM;
|
||||
logic CSRWriteFencePendingDEM;
|
||||
logic DivBusyE;
|
||||
logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
|
||||
logic SquashSCW;
|
||||
@ -101,7 +101,6 @@ module wallypipelinedcore (
|
||||
|
||||
// memory management unit signals
|
||||
logic ITLBWriteF;
|
||||
logic ITLBFlushF, DTLBFlushM;
|
||||
logic ITLBMissF;
|
||||
logic [`XLEN-1:0] SATP_REGW;
|
||||
logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
|
||||
@ -109,7 +108,7 @@ module wallypipelinedcore (
|
||||
logic [1:0] PrivilegeModeW;
|
||||
logic [`XLEN-1:0] PTE;
|
||||
logic [1:0] PageType;
|
||||
logic wfiM, IntPendingM;
|
||||
logic sfencevmaM, wfiM, IntPendingM;
|
||||
logic SelHPTW;
|
||||
|
||||
// PMA checker signals
|
||||
@ -190,7 +189,7 @@ module wallypipelinedcore (
|
||||
// mmu management
|
||||
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
|
||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
|
||||
.STATUS_MPP, .ITLBWriteF, .ITLBFlushF,
|
||||
.STATUS_MPP, .ITLBWriteF, .sfencevmaM,
|
||||
.ITLBMissF,
|
||||
|
||||
// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
|
||||
@ -232,7 +231,7 @@ module wallypipelinedcore (
|
||||
.FPUStallD, .LoadStallD, .MDUStallD, .CSRRdStallD,
|
||||
.PCSrcE,
|
||||
.CSRReadM, .CSRWriteM, .PrivilegedM,
|
||||
.CSRWritePendingDEM, .StoreStallD
|
||||
.CSRWriteFencePendingDEM, .StoreStallD
|
||||
|
||||
); // integer execution unit: integer register file, datapath and controller
|
||||
|
||||
@ -262,7 +261,7 @@ module wallypipelinedcore (
|
||||
.STATUS_MPRV, // from csr
|
||||
.STATUS_MPP, // from csr
|
||||
|
||||
.DTLBFlushM, // connects to privilege
|
||||
.sfencevmaM, // connects to privilege
|
||||
.LoadPageFaultM, // connects to privilege
|
||||
.StoreAmoPageFaultM, // connects to privilege
|
||||
.LoadMisalignedFaultM, // connects to privilege
|
||||
@ -295,13 +294,13 @@ module wallypipelinedcore (
|
||||
|
||||
|
||||
hazard hzu(
|
||||
.BPPredWrongE, .CSRWritePendingDEM, .RetM, .TrapM,
|
||||
.BPPredWrongE, .CSRWriteFencePendingDEM, .RetM, .TrapM,
|
||||
.LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
|
||||
.LSUStallM, .IFUStallF,
|
||||
.FPUStallD, .FStallD,
|
||||
.DivBusyE, .FDivBusyE,
|
||||
.EcallFaultM, .BreakpointFaultM,
|
||||
.InvalidateICacheM, .wfiM, .IntPendingM,
|
||||
.wfiM, .IntPendingM,
|
||||
// Stall & flush outputs
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW,
|
||||
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW
|
||||
@ -315,7 +314,7 @@ module wallypipelinedcore (
|
||||
.CSRReadM, .CSRWriteM, .SrcAM, .PCM,
|
||||
.InstrM, .CSRReadValW, .PrivilegedNextPCM,
|
||||
.RetM, .TrapM,
|
||||
.ITLBFlushF, .DTLBFlushM,
|
||||
.sfencevmaM,
|
||||
.InstrValidM, .CommittedM,
|
||||
.FRegWriteM, .LoadStallD,
|
||||
.BPPredDirWrongM, .BTBPredPCWrongM,
|
||||
@ -344,8 +343,7 @@ module wallypipelinedcore (
|
||||
assign RetM = 0;
|
||||
assign TrapM = 0;
|
||||
assign wfiM = 0;
|
||||
assign ITLBFlushF = 0;
|
||||
assign DTLBFlushM = 0;
|
||||
assign sfencevmaM = 0;
|
||||
assign BigEndianM = 0;
|
||||
end
|
||||
if (`M_SUPPORTED) begin:mdu
|
||||
|
||||
@ -25,9 +25,11 @@ module testbenchfp;
|
||||
|
||||
logic clk=0;
|
||||
logic [31:0] TestNum=0; // index for the test
|
||||
logic [31:0] FmaTestNum=0; // index for the test
|
||||
logic [31:0] OpCtrlNum=0; // index for OpCtrl
|
||||
logic [31:0] errors=0; // how many errors
|
||||
logic [31:0] VectorNum=0; // index for test vector
|
||||
logic [31:0] FmaVectorNum=0; // index for test vector
|
||||
logic [31:0] FrmNum=0; // index for rounding mode
|
||||
logic [`FLEN*4+7:0] TestVectors[46464:0]; // list of test vectors
|
||||
logic [`FLEN*4+7:0] FmaRneVectors[6133248:0]; // list of fma rne test vectors
|
||||
@ -54,7 +56,7 @@ module testbenchfp;
|
||||
logic [4:0] FmaRneAnsFlg, FmaRzAnsFlg, FmaRuAnsFlg, FmaRdAnsFlg, FmaRnmAnsFlg; // flags read form testfloat
|
||||
logic [4:0] ResFlg; // Result flags
|
||||
logic [4:0] FmaRneResFlg, FmaRzResFlg, FmaRuResFlg, FmaRdResFlg, FmaRnmResFlg; // flags read form testfloat
|
||||
logic [`FPSIZES/3:0] ModFmt, FmaModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
|
||||
logic [`FMTBITS-1:0] ModFmt, FmaModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
|
||||
logic [`FLEN-1:0] FmaRes, DivRes, CmpRes, CvtRes; // Results from each unit
|
||||
logic [`XLEN-1:0] CvtIntRes; // Results from each unit
|
||||
logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
|
||||
@ -646,18 +648,20 @@ module testbenchfp;
|
||||
// Read the first test
|
||||
initial begin
|
||||
$display("\n\nRunning %s vectors", Tests[TestNum]);
|
||||
$display("Running FMA precision %d", FmaTestNum);
|
||||
$readmemh({`PATH, Tests[TestNum]}, TestVectors);
|
||||
$readmemh({`PATH, FmaRneTests[TestNum]}, FmaRneVectors);
|
||||
$readmemh({`PATH, FmaRuTests[TestNum]}, FmaRuVectors);
|
||||
$readmemh({`PATH, FmaRdTests[TestNum]}, FmaRdVectors);
|
||||
$readmemh({`PATH, FmaRzTests[TestNum]}, FmaRzVectors);
|
||||
$readmemh({`PATH, FmaRnmTests[TestNum]}, FmaRnmVectors);
|
||||
$readmemh({`PATH, FmaRneTests[FmaTestNum]}, FmaRneVectors);
|
||||
$readmemh({`PATH, FmaRuTests[FmaTestNum]}, FmaRuVectors);
|
||||
$readmemh({`PATH, FmaRdTests[FmaTestNum]}, FmaRdVectors);
|
||||
$readmemh({`PATH, FmaRzTests[FmaTestNum]}, FmaRzVectors);
|
||||
$readmemh({`PATH, FmaRnmTests[FmaTestNum]}, FmaRnmVectors);
|
||||
// set the test index to 0
|
||||
TestNum = 0;
|
||||
FmaTestNum = 0;
|
||||
end
|
||||
|
||||
// set a the signals for all tests
|
||||
always_comb FmaFmtVal = FmaFmt[TestNum];
|
||||
always_comb FmaFmtVal = FmaFmt[FmaTestNum];
|
||||
always_comb UnitVal = Unit[TestNum];
|
||||
always_comb FmtVal = Fmt[TestNum];
|
||||
always_comb OpCtrlVal = OpCtrl[OpCtrlNum];
|
||||
@ -669,14 +673,14 @@ module testbenchfp;
|
||||
// - 1 for the larger precision
|
||||
// - 0 for the smaller precision
|
||||
always_comb begin
|
||||
if(`FPSIZES/3 === 1) ModFmt = FmtVal;
|
||||
if(`FMTBITS == 2) ModFmt = FmtVal;
|
||||
else ModFmt = FmtVal === `FMT;
|
||||
if(`FPSIZES/3 === 1) FmaModFmt = FmaFmtVal;
|
||||
if(`FMTBITS == 2) FmaModFmt = FmaFmtVal;
|
||||
else FmaModFmt = FmaFmtVal === `FMT;
|
||||
end
|
||||
|
||||
// extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
|
||||
readfmavectors readfmarnevectors (.clk, .TestVector(FmaRneVectors[VectorNum]), .Ans(FmaRneAns), .AnsFlg(FmaRneAnsFlg),
|
||||
readfmavectors readfmarnevectors (.clk, .TestVector(FmaRneVectors[FmaVectorNum]), .Ans(FmaRneAns), .AnsFlg(FmaRneAnsFlg),
|
||||
.XSgnE(FmaRneXSgn), .YSgnE(FmaRneYSgn), .ZSgnE(FmaRneZSgn),
|
||||
.XExpE(FmaRneXExp), .YExpE(FmaRneYExp), .ZExpE(FmaRneZExp),
|
||||
.XManE(FmaRneXMan), .YManE(FmaRneYMan), .ZManE(FmaRneZMan),
|
||||
@ -686,7 +690,7 @@ module testbenchfp;
|
||||
.XZeroE(FmaRneXZero), .YZeroE(FmaRneYZero), .ZZeroE(FmaRneZZero),
|
||||
.XInfE(FmaRneXInf), .YInfE(FmaRneYInf), .ZInfE(FmaRneZInf), .FmaModFmt, .FmaFmt(FmaFmtVal),
|
||||
.X(FmaRneX), .Y(FmaRneY), .Z(FmaRneZ));
|
||||
readfmavectors readfmarzvectors (.clk, .TestVector(FmaRzVectors[VectorNum]), .Ans(FmaRzAns), .AnsFlg(FmaRzAnsFlg),
|
||||
readfmavectors readfmarzvectors (.clk, .TestVector(FmaRzVectors[FmaVectorNum]), .Ans(FmaRzAns), .AnsFlg(FmaRzAnsFlg),
|
||||
.XSgnE(FmaRzXSgn), .YSgnE(FmaRzYSgn), .ZSgnE(FmaRzZSgn), .FmaModFmt,
|
||||
.XExpE(FmaRzXExp), .YExpE(FmaRzYExp), .ZExpE(FmaRzZExp),
|
||||
.XManE(FmaRzXMan), .YManE(FmaRzYMan), .ZManE(FmaRzZMan),
|
||||
@ -696,7 +700,7 @@ module testbenchfp;
|
||||
.XZeroE(FmaRzXZero), .YZeroE(FmaRzYZero), .ZZeroE(FmaRzZZero),
|
||||
.XInfE(FmaRzXInf), .YInfE(FmaRzYInf), .ZInfE(FmaRzZInf), .FmaFmt(FmaFmtVal),
|
||||
.X(FmaRzX), .Y(FmaRzY), .Z(FmaRzZ));
|
||||
readfmavectors readfmaruvectors (.clk, .TestVector(FmaRuVectors[VectorNum]), .Ans(FmaRuAns), .AnsFlg(FmaRuAnsFlg),
|
||||
readfmavectors readfmaruvectors (.clk, .TestVector(FmaRuVectors[FmaVectorNum]), .Ans(FmaRuAns), .AnsFlg(FmaRuAnsFlg),
|
||||
.XSgnE(FmaRuXSgn), .YSgnE(FmaRuYSgn), .ZSgnE(FmaRuZSgn), .FmaModFmt,
|
||||
.XExpE(FmaRuXExp), .YExpE(FmaRuYExp), .ZExpE(FmaRuZExp),
|
||||
.XManE(FmaRuXMan), .YManE(FmaRuYMan), .ZManE(FmaRuZMan),
|
||||
@ -706,7 +710,7 @@ module testbenchfp;
|
||||
.XZeroE(FmaRuXZero), .YZeroE(FmaRuYZero), .ZZeroE(FmaRuZZero),
|
||||
.XInfE(FmaRuXInf), .YInfE(FmaRuYInf), .ZInfE(FmaRuZInf), .FmaFmt(FmaFmtVal),
|
||||
.X(FmaRuX), .Y(FmaRuY), .Z(FmaRuZ));
|
||||
readfmavectors readfmardvectors (.clk, .TestVector(FmaRdVectors[VectorNum]), .Ans(FmaRdAns), .AnsFlg(FmaRdAnsFlg),
|
||||
readfmavectors readfmardvectors (.clk, .TestVector(FmaRdVectors[FmaVectorNum]), .Ans(FmaRdAns), .AnsFlg(FmaRdAnsFlg),
|
||||
.XSgnE(FmaRdXSgn), .YSgnE(FmaRdYSgn), .ZSgnE(FmaRdZSgn), .FmaModFmt,
|
||||
.XExpE(FmaRdXExp), .YExpE(FmaRdYExp), .ZExpE(FmaRdZExp),
|
||||
.XManE(FmaRdXMan), .YManE(FmaRdYMan), .ZManE(FmaRdZMan),
|
||||
@ -716,7 +720,7 @@ module testbenchfp;
|
||||
.XZeroE(FmaRdXZero), .YZeroE(FmaRdYZero), .ZZeroE(FmaRdZZero),
|
||||
.XInfE(FmaRdXInf), .YInfE(FmaRdYInf), .ZInfE(FmaRdZInf), .FmaFmt(FmaFmtVal),
|
||||
.X(FmaRdX), .Y(FmaRdY), .Z(FmaRdZ));
|
||||
readfmavectors readfmarnmvectors (.clk, .TestVector(FmaRnmVectors[VectorNum]), .Ans(FmaRnmAns), .AnsFlg(FmaRnmAnsFlg),
|
||||
readfmavectors readfmarnmvectors (.clk, .TestVector(FmaRnmVectors[FmaVectorNum]), .Ans(FmaRnmAns), .AnsFlg(FmaRnmAnsFlg),
|
||||
.XSgnE(FmaRnmXSgn), .YSgnE(FmaRnmYSgn), .ZSgnE(FmaRnmZSgn), .FmaModFmt,
|
||||
.XExpE(FmaRnmXExp), .YExpE(FmaRnmYExp), .ZExpE(FmaRnmZExp),
|
||||
.XManE(FmaRnmXMan), .YManE(FmaRnmYMan), .ZManE(FmaRnmZMan),
|
||||
@ -1024,130 +1028,158 @@ end
|
||||
// - the sign of the NaN does not matter for the opperations being tested
|
||||
// - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
|
||||
case (FmaFmtVal)
|
||||
4'b11: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
4'b11: FmaRneNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(FmaRneAnsFlg[4]&(FmaRneRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(FmaRneXNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneX[`Q_LEN-2:`Q_NF],1'b1,FmaRneX[`Q_NF-2:0]})) |
|
||||
(FmaRneYNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneY[`Q_LEN-2:`Q_NF],1'b1,FmaRneY[`Q_NF-2:0]})) |
|
||||
(FmaRneZNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneZ[`Q_LEN-2:`Q_NF],1'b1,FmaRneZ[`Q_NF-2:0]})));
|
||||
4'b01: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
4'b01: FmaRneNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(FmaRneAnsFlg[4]&(FmaRneRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(FmaRneXNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneX[`D_LEN-2:`D_NF],1'b1,FmaRneX[`D_NF-2:0]})) |
|
||||
(FmaRneYNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneY[`D_LEN-2:`D_NF],1'b1,FmaRneY[`D_NF-2:0]})) |
|
||||
(FmaRneZNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneZ[`D_LEN-2:`D_NF],1'b1,FmaRneZ[`D_NF-2:0]})));
|
||||
4'b00: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
4'b00: FmaRneNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(FmaRneAnsFlg[4]&(FmaRneRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(FmaRneXNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneX[`S_LEN-2:`S_NF],1'b1,FmaRneX[`S_NF-2:0]})) |
|
||||
(FmaRneYNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneY[`S_LEN-2:`S_NF],1'b1,FmaRneY[`S_NF-2:0]})) |
|
||||
(FmaRneZNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneZ[`S_LEN-2:`S_NF],1'b1,FmaRneZ[`S_NF-2:0]})));
|
||||
4'b10: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
4'b10: FmaRneNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(FmaRneAnsFlg[4]&(FmaRneRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(FmaRneXNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneX[`H_LEN-2:`H_NF],1'b1,FmaRneX[`H_NF-2:0]})) |
|
||||
(FmaRneYNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneY[`H_LEN-2:`H_NF],1'b1,FmaRneY[`H_NF-2:0]})) |
|
||||
(FmaRneZNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneZ[`H_LEN-2:`H_NF],1'b1,FmaRneZ[`H_NF-2:0]})));
|
||||
endcase
|
||||
case (FmaFmtVal)
|
||||
4'b11: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
4'b11: FmaRzNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(FmaRzAnsFlg[4]&(FmaRzRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(FmaRzXNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzX[`Q_LEN-2:`Q_NF],1'b1,FmaRzX[`Q_NF-2:0]})) |
|
||||
(FmaRzYNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzY[`Q_LEN-2:`Q_NF],1'b1,FmaRzY[`Q_NF-2:0]})) |
|
||||
(FmaRzZNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzZ[`Q_LEN-2:`Q_NF],1'b1,FmaRzZ[`Q_NF-2:0]})));
|
||||
4'b01: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
4'b01: FmaRzNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(FmaRzAnsFlg[4]&(FmaRzRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(FmaRzXNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzX[`D_LEN-2:`D_NF],1'b1,FmaRzX[`D_NF-2:0]})) |
|
||||
(FmaRzYNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzY[`D_LEN-2:`D_NF],1'b1,FmaRzY[`D_NF-2:0]})) |
|
||||
(FmaRzZNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzZ[`D_LEN-2:`D_NF],1'b1,FmaRzZ[`D_NF-2:0]})));
|
||||
4'b00: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
4'b00: FmaRzNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(FmaRzAnsFlg[4]&(FmaRzRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(FmaRzXNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzX[`S_LEN-2:`S_NF],1'b1,FmaRzX[`S_NF-2:0]})) |
|
||||
(FmaRzYNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzY[`S_LEN-2:`S_NF],1'b1,FmaRzY[`S_NF-2:0]})) |
|
||||
(FmaRzZNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzZ[`S_LEN-2:`S_NF],1'b1,FmaRzZ[`S_NF-2:0]})));
|
||||
4'b10: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
4'b10: FmaRzNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(FmaRzAnsFlg[4]&(FmaRzRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(FmaRzXNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzX[`H_LEN-2:`H_NF],1'b1,FmaRzX[`H_NF-2:0]})) |
|
||||
(FmaRzYNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzY[`H_LEN-2:`H_NF],1'b1,FmaRzY[`H_NF-2:0]})) |
|
||||
(FmaRzZNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzZ[`H_LEN-2:`H_NF],1'b1,FmaRzZ[`H_NF-2:0]})));
|
||||
endcase
|
||||
case (FmaFmtVal)
|
||||
4'b11: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
4'b11: FmaRuNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(FmaRuXNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuX[`Q_LEN-2:`Q_NF],1'b1,FmaRuX[`Q_NF-2:0]})) |
|
||||
(FmaRuYNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuY[`Q_LEN-2:`Q_NF],1'b1,FmaRuY[`Q_NF-2:0]})) |
|
||||
(FmaRuZNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuZ[`Q_LEN-2:`Q_NF],1'b1,FmaRuZ[`Q_NF-2:0]})));
|
||||
4'b01: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
4'b01: FmaRuNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(FmaRuAnsFlg[4]&(FmaRuRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF{1'b0}}})) |
|
||||
(FmaRuXNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuX[`D_LEN-2:`D_NF],1'b1,FmaRuX[`D_NF-2:0]})) |
|
||||
(FmaRuYNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuY[`D_LEN-2:`D_NF],1'b1,FmaRuY[`D_NF-2:0]})) |
|
||||
(FmaRuZNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuZ[`D_LEN-2:`D_NF],1'b1,FmaRuZ[`D_NF-2:0]})));
|
||||
4'b00: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
4'b00: FmaRuNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(FmaRuAnsFlg[4]&(FmaRuRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(FmaRuXNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuX[`S_LEN-2:`S_NF],1'b1,FmaRuX[`S_NF-2:0]})) |
|
||||
(FmaRuYNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuY[`S_LEN-2:`S_NF],1'b1,FmaRuY[`S_NF-2:0]})) |
|
||||
(FmaRuZNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuZ[`S_LEN-2:`S_NF],1'b1,FmaRuZ[`S_NF-2:0]})));
|
||||
4'b10: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
4'b10: FmaRuNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(FmaRuAnsFlg[4]&(FmaRuRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(FmaRuXNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuX[`H_LEN-2:`H_NF],1'b1,FmaRuX[`H_NF-2:0]})) |
|
||||
(FmaRuYNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuY[`H_LEN-2:`H_NF],1'b1,FmaRuY[`H_NF-2:0]})) |
|
||||
(FmaRuZNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuZ[`H_LEN-2:`H_NF],1'b1,FmaRuZ[`H_NF-2:0]})));
|
||||
endcase
|
||||
case (FmaFmtVal)
|
||||
4'b11: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
4'b11: FmaRdNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(FmaRdAnsFlg[4]&(FmaRdRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(FmaRdXNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdX[`Q_LEN-2:`Q_NF],1'b1,FmaRdX[`Q_NF-2:0]})) |
|
||||
(FmaRdYNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdY[`Q_LEN-2:`Q_NF],1'b1,FmaRdY[`Q_NF-2:0]})) |
|
||||
(FmaRdZNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdZ[`Q_LEN-2:`Q_NF],1'b1,FmaRdZ[`Q_NF-2:0]})));
|
||||
4'b01: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
4'b01: FmaRdNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(FmaRdAnsFlg[4]&(FmaRdRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(FmaRdXNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdX[`D_LEN-2:`D_NF],1'b1,FmaRdX[`D_NF-2:0]})) |
|
||||
(FmaRdYNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdY[`D_LEN-2:`D_NF],1'b1,FmaRdY[`D_NF-2:0]})) |
|
||||
(FmaRdZNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdZ[`D_LEN-2:`D_NF],1'b1,FmaRdZ[`D_NF-2:0]})));
|
||||
4'b00: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
4'b00: FmaRdNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(FmaRdAnsFlg[4]&(FmaRdRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(FmaRdXNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdX[`S_LEN-2:`S_NF],1'b1,FmaRdX[`S_NF-2:0]})) |
|
||||
(FmaRdYNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdY[`S_LEN-2:`S_NF],1'b1,FmaRdY[`S_NF-2:0]})) |
|
||||
(FmaRdZNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdZ[`S_LEN-2:`S_NF],1'b1,FmaRdZ[`S_NF-2:0]})));
|
||||
4'b10: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
4'b10: FmaRdNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(FmaRdAnsFlg[4]&(FmaRdRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(FmaRdXNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdX[`H_LEN-2:`H_NF],1'b1,FmaRdX[`H_NF-2:0]})) |
|
||||
(FmaRdYNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdY[`H_LEN-2:`H_NF],1'b1,FmaRdY[`H_NF-2:0]})) |
|
||||
(FmaRdZNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdZ[`H_LEN-2:`H_NF],1'b1,FmaRdZ[`H_NF-2:0]})));
|
||||
endcase
|
||||
case (FmaFmtVal)
|
||||
4'b11: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
4'b11: FmaRnmNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(FmaRnmAnsFlg[4]&(FmaRnmRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(FmaRnmXNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmX[`Q_LEN-2:`Q_NF],1'b1,FmaRnmX[`Q_NF-2:0]})) |
|
||||
(FmaRnmYNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmY[`Q_LEN-2:`Q_NF],1'b1,FmaRnmY[`Q_NF-2:0]})) |
|
||||
(FmaRnmZNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmZ[`Q_LEN-2:`Q_NF],1'b1,FmaRnmZ[`Q_NF-2:0]})));
|
||||
4'b01: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
4'b01: FmaRnmNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(FmaRnmAnsFlg[4]&(FmaRnmRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(FmaRnmXNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmX[`D_LEN-2:`D_NF],1'b1,FmaRnmX[`D_NF-2:0]})) |
|
||||
(FmaRnmYNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmY[`D_LEN-2:`D_NF],1'b1,FmaRnmY[`D_NF-2:0]})) |
|
||||
(FmaRnmZNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmZ[`D_LEN-2:`D_NF],1'b1,FmaRnmZ[`D_NF-2:0]})));
|
||||
4'b00: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
4'b00: FmaRnmNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(FmaRnmAnsFlg[4]&(FmaRnmRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(FmaRnmXNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmX[`S_LEN-2:`S_NF],1'b1,FmaRnmX[`S_NF-2:0]})) |
|
||||
(FmaRnmYNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmY[`S_LEN-2:`S_NF],1'b1,FmaRnmY[`S_NF-2:0]})) |
|
||||
(FmaRnmZNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmZ[`S_LEN-2:`S_NF],1'b1,FmaRnmZ[`S_NF-2:0]})));
|
||||
4'b10: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
4'b10: FmaRnmNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(FmaRnmAnsFlg[4]&(FmaRnmRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(FmaRnmXNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmX[`H_LEN-2:`H_NF],1'b1,FmaRnmX[`H_NF-2:0]})) |
|
||||
(FmaRnmYNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmY[`H_LEN-2:`H_NF],1'b1,FmaRnmY[`H_NF-2:0]})) |
|
||||
(FmaRnmZNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmZ[`H_LEN-2:`H_NF],1'b1,FmaRnmZ[`H_NF-2:0]})));
|
||||
endcase
|
||||
if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT)
|
||||
case (FmtVal)
|
||||
4'b11: NaNGood = ((AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
4'b11: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) |
|
||||
(YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})) |
|
||||
(ZNaN&(Res[`Q_LEN-2:0] === {Z[`Q_LEN-2:`Q_NF],1'b1,Z[`Q_NF-2:0]})));
|
||||
4'b01: NaNGood = ((AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
4'b01: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) |
|
||||
(YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) |
|
||||
(ZNaN&(Res[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]})));
|
||||
4'b00: NaNGood = ((AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
4'b00: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) |
|
||||
(YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) |
|
||||
(ZNaN&(Res[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]})));
|
||||
4'b10: NaNGood = ((AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
4'b10: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) |
|
||||
(YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) |
|
||||
(ZNaN&(Res[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]})));
|
||||
endcase
|
||||
else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format
|
||||
case (OpCtrlVal[1:0])
|
||||
2'b11: NaNGood = ((AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
2'b11: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
|
||||
(AnsNaN&(Res[`Q_LEN-2:0] === Ans[`Q_LEN-2:0])) |
|
||||
(XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) |
|
||||
(YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})));
|
||||
2'b01: NaNGood = ((AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
2'b01: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
|
||||
(AnsNaN&(Res[`D_LEN-2:0] === Ans[`D_LEN-2:0])) |
|
||||
(XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) |
|
||||
(YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})));
|
||||
2'b00: NaNGood = ((AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
2'b00: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
|
||||
(AnsNaN&(Res[`S_LEN-2:0] === Ans[`S_LEN-2:0])) |
|
||||
(XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) |
|
||||
(YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})));
|
||||
2'b10: NaNGood = ((AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
2'b10: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
|
||||
(AnsNaN&(Res[`H_LEN-2:0] === Ans[`H_LEN-2:0])) |
|
||||
(XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) |
|
||||
(YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})));
|
||||
@ -1182,7 +1214,7 @@ end
|
||||
else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&XSgn&(Res[`XLEN-1:0] === (`XLEN)'(0))) |
|
||||
(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~XSgn|XNaN)&OpCtrlVal[1]&(Res[`XLEN-1:0] === {1'b0, {`XLEN-1{1'b1}}})) |
|
||||
(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~XSgn|XNaN)&~OpCtrlVal[1]&(Res[`XLEN-1:0] === {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) |
|
||||
(Res === Ans | NaNGood | NaNGood === 1'bx)) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
|
||||
(~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&XSgn&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
|
||||
errors += 1;
|
||||
$display("There is an error in %s", Tests[TestNum]);
|
||||
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
|
||||
@ -1222,15 +1254,46 @@ end
|
||||
end
|
||||
|
||||
VectorNum += 1; // increment the vector
|
||||
FmaVectorNum += 1; // increment the vector
|
||||
|
||||
// check to see if there more vectors in this test
|
||||
// *** fix this so that fma and other run sepratly - re-add fma num
|
||||
if (TestVectors[VectorNum][0] === 1'bx &
|
||||
FmaRneVectors[VectorNum][0] === 1'bx &
|
||||
FmaRzVectors[VectorNum][0] === 1'bx &
|
||||
FmaRuVectors[VectorNum][0] === 1'bx &
|
||||
FmaRdVectors[VectorNum][0] === 1'bx &
|
||||
FmaRnmVectors[VectorNum][0] === 1'bx) begin // if reached the end of file
|
||||
if ((FmaRneVectors[FmaVectorNum][0] === 1'bx &
|
||||
FmaRzVectors[FmaVectorNum][0] === 1'bx &
|
||||
FmaRuVectors[FmaVectorNum][0] === 1'bx &
|
||||
FmaRdVectors[FmaVectorNum][0] === 1'bx &
|
||||
FmaRnmVectors[FmaVectorNum][0] === 1'bx & FmaRneTests[FmaTestNum] !== "" )) begin // if reached the end of file
|
||||
|
||||
// increment the test
|
||||
FmaTestNum += 1;
|
||||
|
||||
// clear the vectors
|
||||
for(int i=0; i<46465; i++) TestVectors[i] = {`FLEN*4+8{1'bx}};
|
||||
// read next files
|
||||
$readmemh({`PATH, FmaRneTests[FmaTestNum]}, FmaRneVectors);
|
||||
$readmemh({`PATH, FmaRuTests[FmaTestNum]}, FmaRuVectors);
|
||||
$readmemh({`PATH, FmaRdTests[FmaTestNum]}, FmaRdVectors);
|
||||
$readmemh({`PATH, FmaRzTests[FmaTestNum]}, FmaRzVectors);
|
||||
$readmemh({`PATH, FmaRnmTests[FmaTestNum]}, FmaRnmVectors);
|
||||
|
||||
// set the vector index back to 0
|
||||
FmaVectorNum = 0;
|
||||
|
||||
// if no more Tests - finish
|
||||
if(Tests[TestNum] === "" &
|
||||
FmaRneTests[FmaTestNum] === "" &
|
||||
FmaRzTests[FmaTestNum] === "" &
|
||||
FmaRuTests[FmaTestNum] === "" &
|
||||
FmaRdTests[FmaTestNum] === "" &
|
||||
FmaRnmTests[FmaTestNum] === "") begin
|
||||
$display("\nAll Tests completed with %d errors\n", errors);
|
||||
$stop;
|
||||
end
|
||||
|
||||
$display("Running FMA precision %d", FmaTestNum);
|
||||
end
|
||||
|
||||
if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the end of file
|
||||
|
||||
// increment the test
|
||||
TestNum += 1;
|
||||
@ -1239,11 +1302,11 @@ end
|
||||
for(int i=0; i<46465; i++) TestVectors[i] = {`FLEN*4+8{1'bx}};
|
||||
// read next files
|
||||
$readmemh({`PATH, Tests[TestNum]}, TestVectors);
|
||||
$readmemh({`PATH, FmaRneTests[TestNum]}, FmaRneVectors);
|
||||
$readmemh({`PATH, FmaRuTests[TestNum]}, FmaRuVectors);
|
||||
$readmemh({`PATH, FmaRdTests[TestNum]}, FmaRdVectors);
|
||||
$readmemh({`PATH, FmaRzTests[TestNum]}, FmaRzVectors);
|
||||
$readmemh({`PATH, FmaRnmTests[TestNum]}, FmaRnmVectors);
|
||||
$readmemh({`PATH, FmaRneTests[FmaTestNum]}, FmaRneVectors);
|
||||
$readmemh({`PATH, FmaRuTests[FmaTestNum]}, FmaRuVectors);
|
||||
$readmemh({`PATH, FmaRdTests[FmaTestNum]}, FmaRdVectors);
|
||||
$readmemh({`PATH, FmaRzTests[FmaTestNum]}, FmaRzVectors);
|
||||
$readmemh({`PATH, FmaRnmTests[FmaTestNum]}, FmaRnmVectors);
|
||||
|
||||
// set the vector index back to 0
|
||||
VectorNum = 0;
|
||||
@ -1255,11 +1318,11 @@ end
|
||||
|
||||
// if no more Tests - finish
|
||||
if(Tests[TestNum] === "" &
|
||||
FmaRneTests[TestNum] === "" &
|
||||
FmaRzTests[TestNum] === "" &
|
||||
FmaRuTests[TestNum] === "" &
|
||||
FmaRdTests[TestNum] === "" &
|
||||
FmaRnmTests[TestNum] === "") begin
|
||||
FmaRneTests[FmaTestNum] === "" &
|
||||
FmaRzTests[FmaTestNum] === "" &
|
||||
FmaRuTests[FmaTestNum] === "" &
|
||||
FmaRdTests[FmaTestNum] === "" &
|
||||
FmaRnmTests[FmaTestNum] === "") begin
|
||||
$display("\nAll Tests completed with %d errors\n", errors);
|
||||
$stop;
|
||||
end
|
||||
@ -1283,7 +1346,7 @@ endmodule
|
||||
|
||||
module readfmavectors (
|
||||
input logic clk,
|
||||
input logic [`FPSIZES/3:0] FmaModFmt, // the modified format
|
||||
input logic [`FMTBITS-1:0] FmaModFmt, // the modified format
|
||||
input logic [1:0] FmaFmt, // the format of the FMA inputs
|
||||
input logic [`FLEN*4+7:0] TestVector, // the test vector
|
||||
output logic [`FLEN-1:0] Ans, // the correct answer
|
||||
@ -1358,7 +1421,7 @@ endmodule
|
||||
module readvectors (
|
||||
input logic clk,
|
||||
input logic [`FLEN*4+7:0] TestVector,
|
||||
input logic [`FPSIZES/3:0] ModFmt,
|
||||
input logic [`FMTBITS-1:0] ModFmt,
|
||||
input logic [1:0] Fmt,
|
||||
input logic [2:0] Unit,
|
||||
input logic [31:0] VectorNum,
|
||||
|
||||
@ -27,6 +27,15 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
`define DEBUG_TRACE 0
|
||||
// Debug Levels
|
||||
// 0: don't check against QEMU
|
||||
// 1: print disagreements with QEMU, but only halt on PCW disagreements
|
||||
// 2: halt on any disagreement with QEMU except CSRs
|
||||
// 3: halt on all disagreements with QEMU
|
||||
// 4: print memory accesses whenever they happen
|
||||
// 5: print everything
|
||||
|
||||
module testbench;
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////// CONFIG ////////////////////////////////////
|
||||
@ -37,14 +46,7 @@ module testbench;
|
||||
parameter CHECKPOINT = 0;
|
||||
parameter RISCV_DIR = "/opt/riscv";
|
||||
parameter NO_SPOOFING = 0;
|
||||
parameter DEBUG_TRACE = 0;
|
||||
// Debug Levels
|
||||
// 0: don't check against QEMU
|
||||
// 1: print disagreements with QEMU, but only halt on PCW disagreements
|
||||
// 2: halt on any disagreement with QEMU except CSRs
|
||||
// 3: halt on all disagreements with QEMU
|
||||
// 4: print memory accesses whenever they happen
|
||||
// 5: print everything
|
||||
|
||||
|
||||
|
||||
|
||||
@ -350,6 +352,18 @@ module testbench;
|
||||
end \
|
||||
end
|
||||
|
||||
// Initializing all zeroes into the branch predictor memory.
|
||||
genvar adrindex;
|
||||
for(adrindex = 0; adrindex < 1024; adrindex++) begin
|
||||
initial begin
|
||||
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
|
||||
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
|
||||
#1;
|
||||
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
|
||||
release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
|
||||
end
|
||||
end
|
||||
|
||||
genvar i;
|
||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1);
|
||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,0);
|
||||
@ -403,8 +417,6 @@ module testbench;
|
||||
$sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR);
|
||||
if (CHECKPOINT!=0)
|
||||
$sformat(checkpointDir,"%s/linux-testvectors/checkpoint%0d/",RISCV_DIR,CHECKPOINT);
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); // *** initialize these using zeroes rather than reading from files, see testbench.sv
|
||||
$readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
|
||||
ProgramAddrMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.addr"};
|
||||
ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"};
|
||||
// initialize bootrom
|
||||
@ -480,7 +492,7 @@ module testbench;
|
||||
if (checkInstrM) begin \
|
||||
// read 1 line of the trace file \
|
||||
matchCount``STAGE = $fgets(line``STAGE, traceFile``STAGE); \
|
||||
if(DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \
|
||||
if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \
|
||||
// extract PC, Instr \
|
||||
matchCount``STAGE = $sscanf(line``STAGE, "%x %x %s", ExpectedPC``STAGE, ExpectedInstr``STAGE, text``STAGE); \
|
||||
if (`"STAGE`"=="M") begin \
|
||||
@ -564,14 +576,14 @@ module testbench;
|
||||
`define checkEQ(NAME, VAL, EXPECTED) \
|
||||
if(VAL != EXPECTED) begin \
|
||||
$display("%tns, %d instrs: %s %x differs from expected %x", $time, AttemptedInstructionCount, NAME, VAL, EXPECTED); \
|
||||
if ((NAME == "PCW") | (DEBUG_TRACE >= 2)) fault = 1; \
|
||||
if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \
|
||||
end
|
||||
|
||||
`define checkCSR(CSR) \
|
||||
begin \
|
||||
if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \
|
||||
$display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
|
||||
if(DEBUG_TRACE >= 3) fault = 1; \
|
||||
if(`DEBUG_TRACE >= 3) fault = 1; \
|
||||
end \
|
||||
end
|
||||
|
||||
@ -654,15 +666,15 @@ module testbench;
|
||||
// turn on waves
|
||||
if (AttemptedInstructionCount == INSTR_WAVEON) $stop;
|
||||
// end sim
|
||||
if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
|
||||
if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop;
|
||||
fault = 0;
|
||||
if (DEBUG_TRACE >= 1) begin
|
||||
if (`DEBUG_TRACE >= 1) begin
|
||||
`checkEQ("PCW",PCW,ExpectedPCW)
|
||||
//`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of
|
||||
// compressed to uncompressed conversion
|
||||
`checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW)
|
||||
#2; // delay 2 ns.
|
||||
if(DEBUG_TRACE >= 5) begin
|
||||
if(`DEBUG_TRACE >= 5) begin
|
||||
$display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW);
|
||||
$display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
|
||||
end
|
||||
@ -672,13 +684,13 @@ module testbench;
|
||||
`checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW)
|
||||
end
|
||||
if (MemOpW.substr(0,2) == "Mem") begin
|
||||
if(DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW);
|
||||
if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW);
|
||||
`checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW)
|
||||
if(MemOpW == "MemR" | MemOpW == "MemRW") begin
|
||||
if(DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW);
|
||||
if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW);
|
||||
`checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW)
|
||||
end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin
|
||||
if(DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
|
||||
if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
|
||||
`checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW)
|
||||
end
|
||||
end
|
||||
@ -718,7 +730,7 @@ module testbench;
|
||||
$display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount);
|
||||
$stop; $stop;
|
||||
end
|
||||
end // if (DEBUG_TRACE >= 1)
|
||||
end // if (`DEBUG_TRACE >= 1)
|
||||
end // if (checkInstrW)
|
||||
end // always @ (negedge clk)
|
||||
|
||||
|
||||
@ -87,7 +87,6 @@ logic [3:0] dummy;
|
||||
"arch64m": if (`M_SUPPORTED) tests = arch64m;
|
||||
"arch64d": if (`D_SUPPORTED) tests = arch64d;
|
||||
"imperas64i": tests = imperas64i;
|
||||
//"imperas64mmu": if (`VIRTMEM_SUPPORTED) tests = imperas64mmu;
|
||||
"imperas64f": if (`F_SUPPORTED) tests = imperas64f;
|
||||
"imperas64d": if (`D_SUPPORTED) tests = imperas64d;
|
||||
"imperas64m": if (`M_SUPPORTED) tests = imperas64m;
|
||||
@ -95,8 +94,8 @@ logic [3:0] dummy;
|
||||
"imperas64c": if (`C_SUPPORTED) tests = imperas64c;
|
||||
else tests = imperas64iNOc;
|
||||
"testsBP64": tests = testsBP64;
|
||||
"wally64i": tests = wally64i; // *** redo
|
||||
"wally64priv": tests = wally64priv;// *** redo
|
||||
"wally64i": tests = wally64i;
|
||||
"wally64priv": tests = wally64priv;
|
||||
"wally64periph": tests = wally64periph;
|
||||
"coremark": tests = coremark;
|
||||
endcase
|
||||
@ -110,15 +109,14 @@ logic [3:0] dummy;
|
||||
"arch32m": if (`M_SUPPORTED) tests = arch32m;
|
||||
"arch32f": if (`F_SUPPORTED) tests = arch32f;
|
||||
"imperas32i": tests = imperas32i;
|
||||
//"imperas32mmu": if (`VIRTMEM_SUPPORTED) tests = imperas32mmu;
|
||||
"imperas32f": if (`F_SUPPORTED) tests = imperas32f;
|
||||
"imperas32m": if (`M_SUPPORTED) tests = imperas32m;
|
||||
"wally32a": if (`A_SUPPORTED) tests = wally32a;
|
||||
"imperas32c": if (`C_SUPPORTED) tests = imperas32c;
|
||||
else tests = imperas32iNOc;
|
||||
"wally32i": tests = wally32i; // *** redo
|
||||
"wally32i": tests = wally32i;
|
||||
"wally32e": tests = wally32e;
|
||||
"wally32priv": tests = wally32priv; // *** redo
|
||||
"wally32priv": tests = wally32priv;
|
||||
"embench": tests = embench;
|
||||
endcase
|
||||
end
|
||||
|
||||
@ -30,7 +30,7 @@ eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
|
||||
eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
|
||||
|
||||
# Only for FMA class project; comment out when done
|
||||
eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
|
||||
# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
|
||||
|
||||
# Enables name mapping
|
||||
if { $saifpower == 1 } {
|
||||
@ -325,21 +325,15 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets -
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_fpu_timing.rep"]
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/*} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fma1 ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma1/*} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fma2 ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma2/*} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through FMAResM ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FMAResM} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through FDivResM ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FDivResM} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through FResE ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FResE} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fma/SumE ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/SumE} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fma/ProdExpE ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/ProdExpE} -nworst 1 }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fdivsqrt/*} -nworst 1 }
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through fcvt ////\n\n\n" }
|
||||
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fcvt/*} -nworst 1 }
|
||||
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mmu_timing.rep"]
|
||||
redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" }
|
||||
|
||||
@ -1,484 +0,0 @@
|
||||
#!/bin/sh
|
||||
BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
|
||||
OUTPUT="./vectors"
|
||||
echo "Editing ui32_to_f16 test vectors"
|
||||
sed -ie 's/$/_0_2_2/' $OUTPUT/ui32_to_f16_rne.tv
|
||||
sed -ie 's/$/_1_2_2/' $OUTPUT/ui32_to_f16_rz.tv
|
||||
sed -ie 's/$/_3_2_2/' $OUTPUT/ui32_to_f16_ru.tv
|
||||
sed -ie 's/$/_2_2_2/' $OUTPUT/ui32_to_f16_rd.tv
|
||||
sed -ie 's/$/_4_2_2/' $OUTPUT/ui32_to_f16_rnm.tv
|
||||
echo "Editing ui32_to_f32 test vectors"
|
||||
sed -ie 's/$/_0_0_2/' $OUTPUT/ui32_to_f32_rne.tv
|
||||
sed -ie 's/$/_1_0_2/' $OUTPUT/ui32_to_f32_rz.tv
|
||||
sed -ie 's/$/_3_0_2/' $OUTPUT/ui32_to_f32_ru.tv
|
||||
sed -ie 's/$/_2_0_2/' $OUTPUT/ui32_to_f32_rd.tv
|
||||
sed -ie 's/$/_4_0_2/' $OUTPUT/ui32_to_f32_rnm.tv
|
||||
echo "Editing ui32_to_f64 test vectors"
|
||||
sed -ie 's/$/_0_1_2/' $OUTPUT/ui32_to_f64_rne.tv
|
||||
sed -ie 's/$/_1_1_2/' $OUTPUT/ui32_to_f64_rz.tv
|
||||
sed -ie 's/$/_3_1_2/' $OUTPUT/ui32_to_f64_ru.tv
|
||||
sed -ie 's/$/_2_1_2/' $OUTPUT/ui32_to_f64_rd.tv
|
||||
sed -ie 's/$/_4_1_2/' $OUTPUT/ui32_to_f64_rnm.tv
|
||||
echo "Editing ui32_to_f128 test vectors"
|
||||
sed -ie 's/$/_0_3_2/' $OUTPUT/ui32_to_f128_rne.tv
|
||||
sed -ie 's/$/_1_3_2/' $OUTPUT/ui32_to_f128_rz.tv
|
||||
sed -ie 's/$/_3_3_2/' $OUTPUT/ui32_to_f128_ru.tv
|
||||
sed -ie 's/$/_2_3_2/' $OUTPUT/ui32_to_f128_rd.tv
|
||||
sed -ie 's/$/_4_3_2/' $OUTPUT/ui32_to_f128_rnm.tv
|
||||
echo "Editing ui64_to_f16 test vectors"
|
||||
sed -ie 's/$/_0_2_6/' $OUTPUT/ui64_to_f16_rne.tv
|
||||
sed -ie 's/$/_1_2_6/' $OUTPUT/ui64_to_f16_rz.tv
|
||||
sed -ie 's/$/_3_2_6/' $OUTPUT/ui64_to_f16_ru.tv
|
||||
sed -ie 's/$/_2_2_6/' $OUTPUT/ui64_to_f16_rd.tv
|
||||
sed -ie 's/$/_4_2_6/' $OUTPUT/ui64_to_f16_rnm.tv
|
||||
echo "Editing ui64_to_f32 test vectors"
|
||||
sed -ie 's/$/_0_0_6/' $OUTPUT/ui64_to_f32_rne.tv
|
||||
sed -ie 's/$/_1_0_6/' $OUTPUT/ui64_to_f32_rz.tv
|
||||
sed -ie 's/$/_3_0_6/' $OUTPUT/ui64_to_f32_ru.tv
|
||||
sed -ie 's/$/_2_0_6/' $OUTPUT/ui64_to_f32_rd.tv
|
||||
sed -ie 's/$/_4_0_6/' $OUTPUT/ui64_to_f32_rnm.tv
|
||||
echo "Editing ui64_to_f64 test vectors"
|
||||
sed -ie 's/$/_0_1_6/' $OUTPUT/ui64_to_f64_rne.tv
|
||||
sed -ie 's/$/_1_1_6/' $OUTPUT/ui64_to_f64_rz.tv
|
||||
sed -ie 's/$/_3_1_6/' $OUTPUT/ui64_to_f64_ru.tv
|
||||
sed -ie 's/$/_2_1_6/' $OUTPUT/ui64_to_f64_rd.tv
|
||||
sed -ie 's/$/_4_1_6/' $OUTPUT/ui64_to_f64_rnm.tv
|
||||
echo "Editing ui64_to_f128 test vectors"
|
||||
sed -ie 's/$/_0_3_6/' $OUTPUT/ui64_to_f128_rne.tv
|
||||
sed -ie 's/$/_1_3_6/' $OUTPUT/ui64_to_f128_rz.tv
|
||||
sed -ie 's/$/_3_3_6/' $OUTPUT/ui64_to_f128_ru.tv
|
||||
sed -ie 's/$/_2_3_6/' $OUTPUT/ui64_to_f128_rd.tv
|
||||
sed -ie 's/$/_4_3_6/' $OUTPUT/ui64_to_f128_rnm.tv
|
||||
echo "Editing i32_to_f16 test vectors"
|
||||
sed -ie 's/$/_0_2_0/' $OUTPUT/i32_to_f16_rne.tv
|
||||
sed -ie 's/$/_1_2_0/' $OUTPUT/i32_to_f16_rz.tv
|
||||
sed -ie 's/$/_3_2_0/' $OUTPUT/i32_to_f16_ru.tv
|
||||
sed -ie 's/$/_2_2_0/' $OUTPUT/i32_to_f16_rd.tv
|
||||
sed -ie 's/$/_4_2_0/' $OUTPUT/i32_to_f16_rnm.tv
|
||||
echo "Editing i32_to_f32 test vectors"
|
||||
sed -ie 's/$/_0_0_0/' $OUTPUT/i32_to_f32_rne.tv
|
||||
sed -ie 's/$/_1_0_0/' $OUTPUT/i32_to_f32_rz.tv
|
||||
sed -ie 's/$/_3_0_0/' $OUTPUT/i32_to_f32_ru.tv
|
||||
sed -ie 's/$/_2_0_0/' $OUTPUT/i32_to_f32_rd.tv
|
||||
sed -ie 's/$/_4_0_0/' $OUTPUT/i32_to_f32_rnm.tv
|
||||
echo "Editing i32_to_f64 test vectors"
|
||||
sed -ie 's/$/_0_1_0/' $OUTPUT/i32_to_f64_rne.tv
|
||||
sed -ie 's/$/_1_1_0/' $OUTPUT/i32_to_f64_rz.tv
|
||||
sed -ie 's/$/_3_1_0/' $OUTPUT/i32_to_f64_ru.tv
|
||||
sed -ie 's/$/_2_1_0/' $OUTPUT/i32_to_f64_rd.tv
|
||||
sed -ie 's/$/_4_1_0/' $OUTPUT/i32_to_f64_rnm.tv
|
||||
echo "Editing i32_to_f128 test vectors"
|
||||
sed -ie 's/$/_0_3_0/' $OUTPUT/i32_to_f128_rne.tv
|
||||
sed -ie 's/$/_1_3_0/' $OUTPUT/i32_to_f128_rz.tv
|
||||
sed -ie 's/$/_3_3_0/' $OUTPUT/i32_to_f128_ru.tv
|
||||
sed -ie 's/$/_2_3_0/' $OUTPUT/i32_to_f128_rd.tv
|
||||
sed -ie 's/$/_4_3_0/' $OUTPUT/i32_to_f128_rnm.tv
|
||||
echo "Editing i64_to_f16 test vectors"
|
||||
sed -ie 's/$/_0_2_4/' $OUTPUT/i64_to_f16_rne.tv
|
||||
sed -ie 's/$/_1_2_4/' $OUTPUT/i64_to_f16_rz.tv
|
||||
sed -ie 's/$/_3_2_4/' $OUTPUT/i64_to_f16_ru.tv
|
||||
sed -ie 's/$/_2_2_4/' $OUTPUT/i64_to_f16_rd.tv
|
||||
sed -ie 's/$/_4_2_4/' $OUTPUT/i64_to_f16_rnm.tv
|
||||
echo "Editing i64_to_f32 test vectors"
|
||||
sed -ie 's/$/_0_0_4/' $OUTPUT/i64_to_f32_rne.tv
|
||||
sed -ie 's/$/_1_0_4/' $OUTPUT/i64_to_f32_rz.tv
|
||||
sed -ie 's/$/_3_0_4/' $OUTPUT/i64_to_f32_ru.tv
|
||||
sed -ie 's/$/_2_0_4/' $OUTPUT/i64_to_f32_rd.tv
|
||||
sed -ie 's/$/_4_0_4/' $OUTPUT/i64_to_f32_rnm.tv
|
||||
echo "Editing i64_to_f64 test vectors"
|
||||
sed -ie 's/$/_0_1_4/' $OUTPUT/i64_to_f64_rne.tv
|
||||
sed -ie 's/$/_1_1_4/' $OUTPUT/i64_to_f64_rz.tv
|
||||
sed -ie 's/$/_3_1_4/' $OUTPUT/i64_to_f64_ru.tv
|
||||
sed -ie 's/$/_2_1_4/' $OUTPUT/i64_to_f64_rd.tv
|
||||
sed -ie 's/$/_4_1_4/' $OUTPUT/i64_to_f64_rnm.tv
|
||||
echo "Editing i64_to_f128 test vectors"
|
||||
sed -ie 's/$/_0_3_4/' $OUTPUT/i64_to_f128_rne.tv
|
||||
sed -ie 's/$/_1_3_4/' $OUTPUT/i64_to_f128_rz.tv
|
||||
sed -ie 's/$/_3_3_4/' $OUTPUT/i64_to_f128_ru.tv
|
||||
sed -ie 's/$/_2_3_4/' $OUTPUT/i64_to_f128_rd.tv
|
||||
sed -ie 's/$/_4_3_4/' $OUTPUT/i64_to_f128_rnm.tv
|
||||
echo "Editing f16_to_ui32 test vectors"
|
||||
sed -ie 's/$/_0_2_3/' $OUTPUT/f16_to_ui32_rne.tv
|
||||
sed -ie 's/$/_1_2_3/' $OUTPUT/f16_to_ui32_rz.tv
|
||||
sed -ie 's/$/_3_2_3/' $OUTPUT/f16_to_ui32_ru.tv
|
||||
sed -ie 's/$/_2_2_3/' $OUTPUT/f16_to_ui32_rd.tv
|
||||
sed -ie 's/$/_4_2_3/' $OUTPUT/f16_to_ui32_rnm.tv
|
||||
echo "Editing f32_to_ui32 test vectors"
|
||||
sed -ie 's/$/_0_0_3/' $OUTPUT/f32_to_ui32_rne.tv
|
||||
sed -ie 's/$/_1_0_3/' $OUTPUT/f32_to_ui32_rz.tv
|
||||
sed -ie 's/$/_3_0_3/' $OUTPUT/f32_to_ui32_ru.tv
|
||||
sed -ie 's/$/_2_0_3/' $OUTPUT/f32_to_ui32_rd.tv
|
||||
sed -ie 's/$/_4_0_3/' $OUTPUT/f32_to_ui32_rnm.tv
|
||||
echo "Editing f64_to_ui32 test vectors"
|
||||
sed -ie 's/$/_0_1_3/' $OUTPUT/f64_to_ui32_rne.tv
|
||||
sed -ie 's/$/_1_1_3/' $OUTPUT/f64_to_ui32_rz.tv
|
||||
sed -ie 's/$/_3_1_3/' $OUTPUT/f64_to_ui32_ru.tv
|
||||
sed -ie 's/$/_2_1_3/' $OUTPUT/f64_to_ui32_rd.tv
|
||||
sed -ie 's/$/_4_1_3/' $OUTPUT/f64_to_ui32_rnm.tv
|
||||
echo "Editing f128_to_ui32 test vectors"
|
||||
sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_ui32_rne.tv
|
||||
sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_ui32_rz.tv
|
||||
sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_ui32_ru.tv
|
||||
sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_ui32_rd.tv
|
||||
sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_ui32_rnm.tv
|
||||
echo "Editing f16_to_ui64 test vectors"
|
||||
sed -ie 's/$/_0_2_7/' $OUTPUT/f16_to_ui64_rne.tv
|
||||
sed -ie 's/$/_1_2_7/' $OUTPUT/f16_to_ui64_rz.tv
|
||||
sed -ie 's/$/_3_2_7/' $OUTPUT/f16_to_ui64_ru.tv
|
||||
sed -ie 's/$/_2_2_7/' $OUTPUT/f16_to_ui64_rd.tv
|
||||
sed -ie 's/$/_4_2_7/' $OUTPUT/f16_to_ui64_rnm.tv
|
||||
echo "Editing f32_to_ui64 test vectors"
|
||||
sed -ie 's/$/_0_0_7/' $OUTPUT/f32_to_ui64_rne.tv
|
||||
sed -ie 's/$/_1_0_7/' $OUTPUT/f32_to_ui64_rz.tv
|
||||
sed -ie 's/$/_3_0_7/' $OUTPUT/f32_to_ui64_ru.tv
|
||||
sed -ie 's/$/_2_0_7/' $OUTPUT/f32_to_ui64_rd.tv
|
||||
sed -ie 's/$/_4_0_7/' $OUTPUT/f32_to_ui64_rnm.tv
|
||||
echo "Editing f64_to_ui64 test vectors"
|
||||
sed -ie 's/$/_0_1_7/' $OUTPUT/f64_to_ui64_rne.tv
|
||||
sed -ie 's/$/_1_1_7/' $OUTPUT/f64_to_ui64_rz.tv
|
||||
sed -ie 's/$/_3_1_7/' $OUTPUT/f64_to_ui64_ru.tv
|
||||
sed -ie 's/$/_2_1_7/' $OUTPUT/f64_to_ui64_rd.tv
|
||||
sed -ie 's/$/_4_1_7/' $OUTPUT/f64_to_ui64_rnm.tv
|
||||
echo "Editing f128_to_ui64 test vectors"
|
||||
sed -ie 's/$/_0_3_7/' $OUTPUT/f128_to_ui64_rne.tv
|
||||
sed -ie 's/$/_1_3_7/' $OUTPUT/f128_to_ui64_rz.tv
|
||||
sed -ie 's/$/_3_3_7/' $OUTPUT/f128_to_ui64_ru.tv
|
||||
sed -ie 's/$/_2_3_7/' $OUTPUT/f128_to_ui64_rd.tv
|
||||
sed -ie 's/$/_4_3_7/' $OUTPUT/f128_to_ui64_rnm.tv
|
||||
echo "Editing f16_to_i32 test vectors"
|
||||
sed -ie 's/$/_0_2_1/' $OUTPUT/f16_to_i32_rne.tv
|
||||
sed -ie 's/$/_1_2_1/' $OUTPUT/f16_to_i32_rz.tv
|
||||
sed -ie 's/$/_3_2_1/' $OUTPUT/f16_to_i32_ru.tv
|
||||
sed -ie 's/$/_2_2_1/' $OUTPUT/f16_to_i32_rd.tv
|
||||
sed -ie 's/$/_4_2_1/' $OUTPUT/f16_to_i32_rnm.tv
|
||||
echo "Editing f32_to_i32 test vectors"
|
||||
sed -ie 's/$/_0_0_1/' $OUTPUT/f32_to_i32_rne.tv
|
||||
sed -ie 's/$/_1_0_1/' $OUTPUT/f32_to_i32_rz.tv
|
||||
sed -ie 's/$/_3_0_1/' $OUTPUT/f32_to_i32_ru.tv
|
||||
sed -ie 's/$/_2_0_1/' $OUTPUT/f32_to_i32_rd.tv
|
||||
sed -ie 's/$/_4_0_1/' $OUTPUT/f32_to_i32_rnm.tv
|
||||
echo "Editing f64_to_i32 test vectors"
|
||||
sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_i32_rne.tv
|
||||
sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_i32_rz.tv
|
||||
sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_i32_ru.tv
|
||||
sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_i32_rd.tv
|
||||
sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_i32_rnm.tv
|
||||
echo "Editing f128_to_i32 test vectors"
|
||||
sed -ie 's/$/_0_3_1/' $OUTPUT/f128_to_i32_rne.tv
|
||||
sed -ie 's/$/_1_3_1/' $OUTPUT/f128_to_i32_rz.tv
|
||||
sed -ie 's/$/_3_3_1/' $OUTPUT/f128_to_i32_ru.tv
|
||||
sed -ie 's/$/_2_3_1/' $OUTPUT/f128_to_i32_rd.tv
|
||||
sed -ie 's/$/_4_3_1/' $OUTPUT/f128_to_i32_rnm.tv
|
||||
echo "Editing f16_to_i64 test vectors"
|
||||
sed -ie 's/$/_0_2_5/' $OUTPUT/f16_to_i64_rne.tv
|
||||
sed -ie 's/$/_1_2_5/' $OUTPUT/f16_to_i64_rz.tv
|
||||
sed -ie 's/$/_3_2_5/' $OUTPUT/f16_to_i64_ru.tv
|
||||
sed -ie 's/$/_2_2_5/' $OUTPUT/f16_to_i64_rd.tv
|
||||
sed -ie 's/$/_4_2_5/' $OUTPUT/f16_to_i64_rnm.tv
|
||||
echo "Editing f32_to_i64 test vectors"
|
||||
sed -ie 's/$/_0_0_5/' $OUTPUT/f32_to_i64_rne.tv
|
||||
sed -ie 's/$/_1_0_5/' $OUTPUT/f32_to_i64_rz.tv
|
||||
sed -ie 's/$/_3_0_5/' $OUTPUT/f32_to_i64_ru.tv
|
||||
sed -ie 's/$/_2_0_5/' $OUTPUT/f32_to_i64_rd.tv
|
||||
sed -ie 's/$/_4_0_5/' $OUTPUT/f32_to_i64_rnm.tv
|
||||
echo "Editing f64_to_i64 test vectors"
|
||||
sed -ie 's/$/_0_1_5/' $OUTPUT/f64_to_i64_rne.tv
|
||||
sed -ie 's/$/_1_1_5/' $OUTPUT/f64_to_i64_rz.tv
|
||||
sed -ie 's/$/_3_1_5/' $OUTPUT/f64_to_i64_ru.tv
|
||||
sed -ie 's/$/_2_1_5/' $OUTPUT/f64_to_i64_rd.tv
|
||||
sed -ie 's/$/_4_1_5/' $OUTPUT/f64_to_i64_rnm.tv
|
||||
echo "Editing f128_to_i64 test vectors"
|
||||
sed -ie 's/$/_0_3_5/' $OUTPUT/f128_to_i64_rne.tv
|
||||
sed -ie 's/$/_1_3_5/' $OUTPUT/f128_to_i64_rz.tv
|
||||
sed -ie 's/$/_3_3_5/' $OUTPUT/f128_to_i64_ru.tv
|
||||
sed -ie 's/$/_2_3_5/' $OUTPUT/f128_to_i64_rd.tv
|
||||
sed -ie 's/$/_4_3_5/' $OUTPUT/f128_to_i64_rnm.tv
|
||||
echo "Editing f16_to_f32 test vectors"
|
||||
sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f32_rne.tv
|
||||
sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f32_rz.tv
|
||||
sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f32_ru.tv
|
||||
sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f32_rd.tv
|
||||
sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f32_rnm.tv
|
||||
echo "Editing f16_to_f64 test vectors"
|
||||
sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f64_rne.tv
|
||||
sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f64_rz.tv
|
||||
sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f64_ru.tv
|
||||
sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f64_rd.tv
|
||||
sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f64_rnm.tv
|
||||
echo "Editing f16_to_f128 test vectors"
|
||||
sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f128_rne.tv
|
||||
sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f128_rz.tv
|
||||
sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f128_ru.tv
|
||||
sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f128_rd.tv
|
||||
sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f128_rnm.tv
|
||||
echo "Editing f32_to_f16 test vectors"
|
||||
sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f16_rne.tv
|
||||
sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f16_rz.tv
|
||||
sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f16_ru.tv
|
||||
sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f16_rd.tv
|
||||
sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f16_rnm.tv
|
||||
echo "Editing f32_to_f64 test vectors"
|
||||
sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f64_rne.tv
|
||||
sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f64_rz.tv
|
||||
sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f64_ru.tv
|
||||
sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f64_rd.tv
|
||||
sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f64_rnm.tv
|
||||
echo "Editing f32_to_f128 test vectors"
|
||||
sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f128_rne.tv
|
||||
sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f128_rz.tv
|
||||
sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f128_ru.tv
|
||||
sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f128_rd.tv
|
||||
sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f128_rnm.tv
|
||||
echo "Editing f64_to_f16 test vectors"
|
||||
sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f16_rne.tv
|
||||
sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f16_rz.tv
|
||||
sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f16_ru.tv
|
||||
sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f16_rd.tv
|
||||
sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f16_rnm.tv
|
||||
echo "Editing f64_to_f32 test vectors"
|
||||
sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f32_rne.tv
|
||||
sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f32_rz.tv
|
||||
sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f32_ru.tv
|
||||
sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f32_rd.tv
|
||||
sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f32_rnm.tv
|
||||
echo "Editing f64_to_f128 test vectors"
|
||||
sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f128_rne.tv
|
||||
sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f128_rz.tv
|
||||
sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f128_ru.tv
|
||||
sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f128_rd.tv
|
||||
sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f128_rnm.tv
|
||||
echo "Editing f128_to_f16 test vectors"
|
||||
sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f16_rne.tv
|
||||
sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f16_rz.tv
|
||||
sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f16_ru.tv
|
||||
sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f16_rd.tv
|
||||
sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f16_rnm.tv
|
||||
echo "Editing f128_to_f32 test vectors"
|
||||
sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f32_rne.tv
|
||||
sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f32_rz.tv
|
||||
sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f32_ru.tv
|
||||
sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f32_rd.tv
|
||||
sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f32_rnm.tv
|
||||
echo "Editing f128_to_f64 test vectors"
|
||||
sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f64_rne.tv
|
||||
sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f64_rz.tv
|
||||
sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f64_ru.tv
|
||||
sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f64_rd.tv
|
||||
sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f64_rnm.tv
|
||||
echo "Editing f16_add test vectors"
|
||||
sed -ie 's/$/_0_2_6/' $OUTPUT/f16_add_rne.tv
|
||||
sed -ie 's/$/_1_2_6/' $OUTPUT/f16_add_rz.tv
|
||||
sed -ie 's/$/_3_2_6/' $OUTPUT/f16_add_ru.tv
|
||||
sed -ie 's/$/_2_2_6/' $OUTPUT/f16_add_rd.tv
|
||||
sed -ie 's/$/_4_2_6/' $OUTPUT/f16_add_rnm.tv
|
||||
echo "Editing f32_add test vectors"
|
||||
sed -ie 's/$/_0_0_6/' $OUTPUT/f32_add_rne.tv
|
||||
sed -ie 's/$/_1_0_6/' $OUTPUT/f32_add_rz.tv
|
||||
sed -ie 's/$/_3_0_6/' $OUTPUT/f32_add_ru.tv
|
||||
sed -ie 's/$/_2_0_6/' $OUTPUT/f32_add_rd.tv
|
||||
sed -ie 's/$/_4_0_6/' $OUTPUT/f32_add_rnm.tv
|
||||
echo "Editing f64_add test vectors"
|
||||
sed -ie 's/$/_0_1_6/' $OUTPUT/f64_add_rne.tv
|
||||
sed -ie 's/$/_1_1_6/' $OUTPUT/f64_add_rz.tv
|
||||
sed -ie 's/$/_3_1_6/' $OUTPUT/f64_add_ru.tv
|
||||
sed -ie 's/$/_2_1_6/' $OUTPUT/f64_add_rd.tv
|
||||
sed -ie 's/$/_4_1_6/' $OUTPUT/f64_add_rnm.tv
|
||||
echo "Editing f128_add test vectors"
|
||||
sed -ie 's/$/_0_3_6/' $OUTPUT/f128_add_rne.tv
|
||||
sed -ie 's/$/_1_3_6/' $OUTPUT/f128_add_rz.tv
|
||||
sed -ie 's/$/_3_3_6/' $OUTPUT/f128_add_ru.tv
|
||||
sed -ie 's/$/_2_3_6/' $OUTPUT/f128_add_rd.tv
|
||||
sed -ie 's/$/_4_3_6/' $OUTPUT/f128_add_rnm.tv
|
||||
echo "Editing f16_sub test vectors"
|
||||
sed -ie 's/$/_0_2_7/' $OUTPUT/f16_sub_rne.tv
|
||||
sed -ie 's/$/_1_2_7/' $OUTPUT/f16_sub_rz.tv
|
||||
sed -ie 's/$/_3_2_7/' $OUTPUT/f16_sub_ru.tv
|
||||
sed -ie 's/$/_2_2_7/' $OUTPUT/f16_sub_rd.tv
|
||||
sed -ie 's/$/_4_2_7/' $OUTPUT/f16_sub_rnm.tv
|
||||
echo "Editing f32_sub test vectors"
|
||||
sed -ie 's/$/_0_0_7/' $OUTPUT/f32_sub_rne.tv
|
||||
sed -ie 's/$/_1_0_7/' $OUTPUT/f32_sub_rz.tv
|
||||
sed -ie 's/$/_3_0_7/' $OUTPUT/f32_sub_ru.tv
|
||||
sed -ie 's/$/_2_0_7/' $OUTPUT/f32_sub_rd.tv
|
||||
sed -ie 's/$/_4_0_7/' $OUTPUT/f32_sub_rnm.tv
|
||||
echo "Editing f64_sub test vectors"
|
||||
sed -ie 's/$/_0_1_7/' $OUTPUT/f64_sub_rne.tv
|
||||
sed -ie 's/$/_1_1_7/' $OUTPUT/f64_sub_rz.tv
|
||||
sed -ie 's/$/_3_1_7/' $OUTPUT/f64_sub_ru.tv
|
||||
sed -ie 's/$/_2_1_7/' $OUTPUT/f64_sub_rd.tv
|
||||
sed -ie 's/$/_4_1_7/' $OUTPUT/f64_sub_rnm.tv
|
||||
echo "Editing f128_sub test vectors"
|
||||
sed -ie 's/$/_0_3_7/' $OUTPUT/f128_sub_rne.tv
|
||||
sed -ie 's/$/_1_3_7/' $OUTPUT/f128_sub_rz.tv
|
||||
sed -ie 's/$/_3_3_7/' $OUTPUT/f128_sub_ru.tv
|
||||
sed -ie 's/$/_2_3_7/' $OUTPUT/f128_sub_rd.tv
|
||||
sed -ie 's/$/_4_3_7/' $OUTPUT/f128_sub_rnm.tv
|
||||
echo "Editing f16_mul test vectors"
|
||||
sed -ie 's/$/_0_2_4/' $OUTPUT/f16_mul_rne.tv
|
||||
sed -ie 's/$/_1_2_4/' $OUTPUT/f16_mul_rz.tv
|
||||
sed -ie 's/$/_3_2_4/' $OUTPUT/f16_mul_ru.tv
|
||||
sed -ie 's/$/_2_2_4/' $OUTPUT/f16_mul_rd.tv
|
||||
sed -ie 's/$/_4_2_4/' $OUTPUT/f16_mul_rnm.tv
|
||||
echo "Editing f32_mul test vectors"
|
||||
sed -ie 's/$/_0_0_4/' $OUTPUT/f32_mul_rne.tv
|
||||
sed -ie 's/$/_1_0_4/' $OUTPUT/f32_mul_rz.tv
|
||||
sed -ie 's/$/_3_0_4/' $OUTPUT/f32_mul_ru.tv
|
||||
sed -ie 's/$/_2_0_4/' $OUTPUT/f32_mul_rd.tv
|
||||
sed -ie 's/$/_4_0_4/' $OUTPUT/f32_mul_rnm.tv
|
||||
echo "Editing f64_mul test vectors"
|
||||
sed -ie 's/$/_0_1_4/' $OUTPUT/f64_mul_rne.tv
|
||||
sed -ie 's/$/_1_1_4/' $OUTPUT/f64_mul_rz.tv
|
||||
sed -ie 's/$/_3_1_4/' $OUTPUT/f64_mul_ru.tv
|
||||
sed -ie 's/$/_2_1_4/' $OUTPUT/f64_mul_rd.tv
|
||||
sed -ie 's/$/_4_1_4/' $OUTPUT/f64_mul_rnm.tv
|
||||
echo "Editing f128_mul test vectors"
|
||||
sed -ie 's/$/_0_3_4/' $OUTPUT/f128_mul_rne.tv
|
||||
sed -ie 's/$/_1_3_4/' $OUTPUT/f128_mul_rz.tv
|
||||
sed -ie 's/$/_3_3_4/' $OUTPUT/f128_mul_ru.tv
|
||||
sed -ie 's/$/_2_3_4/' $OUTPUT/f128_mul_rd.tv
|
||||
sed -ie 's/$/_4_3_4/' $OUTPUT/f128_mul_rnm.tv
|
||||
echo "Editing f16_div test vectors"
|
||||
sed -ie 's/$/_0_2_0/' $OUTPUT/f16_div_rne.tv
|
||||
sed -ie 's/$/_1_2_0/' $OUTPUT/f16_div_rz.tv
|
||||
sed -ie 's/$/_3_2_0/' $OUTPUT/f16_div_ru.tv
|
||||
sed -ie 's/$/_2_2_0/' $OUTPUT/f16_div_rd.tv
|
||||
sed -ie 's/$/_4_2_0/' $OUTPUT/f16_div_rnm.tv
|
||||
echo "Editing f32_div test vectors"
|
||||
sed -ie 's/$/_0_0_0/' $OUTPUT/f32_div_rne.tv
|
||||
sed -ie 's/$/_1_0_0/' $OUTPUT/f32_div_rz.tv
|
||||
sed -ie 's/$/_3_0_0/' $OUTPUT/f32_div_ru.tv
|
||||
sed -ie 's/$/_2_0_0/' $OUTPUT/f32_div_rd.tv
|
||||
sed -ie 's/$/_4_0_0/' $OUTPUT/f32_div_rnm.tv
|
||||
echo "Editing f64_div test vectors"
|
||||
sed -ie 's/$/_0_1_0/' $OUTPUT/f64_div_rne.tv
|
||||
sed -ie 's/$/_1_1_0/' $OUTPUT/f64_div_rz.tv
|
||||
sed -ie 's/$/_3_1_0/' $OUTPUT/f64_div_ru.tv
|
||||
sed -ie 's/$/_2_1_0/' $OUTPUT/f64_div_rd.tv
|
||||
sed -ie 's/$/_4_1_0/' $OUTPUT/f64_div_rnm.tv
|
||||
echo "Editing f128_div test vectors"
|
||||
sed -ie 's/$/_0_3_0/' $OUTPUT/f128_div_rne.tv
|
||||
sed -ie 's/$/_1_3_0/' $OUTPUT/f128_div_rz.tv
|
||||
sed -ie 's/$/_3_3_0/' $OUTPUT/f128_div_ru.tv
|
||||
sed -ie 's/$/_2_3_0/' $OUTPUT/f128_div_rd.tv
|
||||
sed -ie 's/$/_4_3_0/' $OUTPUT/f128_div_rnm.tv
|
||||
echo "Editing f16_sqrt test vectors"
|
||||
sed -ie 's/$/_0_2_1/' $OUTPUT/f16_sqrt_rne.tv
|
||||
sed -ie 's/$/_1_2_1/' $OUTPUT/f16_sqrt_rz.tv
|
||||
sed -ie 's/$/_3_2_1/' $OUTPUT/f16_sqrt_ru.tv
|
||||
sed -ie 's/$/_2_2_1/' $OUTPUT/f16_sqrt_rd.tv
|
||||
sed -ie 's/$/_4_2_1/' $OUTPUT/f16_sqrt_rnm.tv
|
||||
echo "Editing f32_sqrt test vectors"
|
||||
sed -ie 's/$/_0_0_1/' $OUTPUT/f32_sqrt_rne.tv
|
||||
sed -ie 's/$/_1_0_1/' $OUTPUT/f32_sqrt_rz.tv
|
||||
sed -ie 's/$/_3_0_1/' $OUTPUT/f32_sqrt_ru.tv
|
||||
sed -ie 's/$/_2_0_1/' $OUTPUT/f32_sqrt_rd.tv
|
||||
sed -ie 's/$/_4_0_1/' $OUTPUT/f32_sqrt_rnm.tv
|
||||
echo "Editing f64_sqrt test vectors"
|
||||
sed -ie 's/$/_0_1_1/' $OUTPUT/f64_sqrt_rne.tv
|
||||
sed -ie 's/$/_1_1_1/' $OUTPUT/f64_sqrt_rz.tv
|
||||
sed -ie 's/$/_3_1_1/' $OUTPUT/f64_sqrt_ru.tv
|
||||
sed -ie 's/$/_2_1_1/' $OUTPUT/f64_sqrt_rd.tv
|
||||
sed -ie 's/$/_4_1_1/' $OUTPUT/f64_sqrt_rnm.tv
|
||||
echo "Editing f128_sqrt test vectors"
|
||||
sed -ie 's/$/_0_3_1/' $OUTPUT/f128_sqrt_rne.tv
|
||||
sed -ie 's/$/_1_3_1/' $OUTPUT/f128_sqrt_rz.tv
|
||||
sed -ie 's/$/_3_3_1/' $OUTPUT/f128_sqrt_ru.tv
|
||||
sed -ie 's/$/_2_3_1/' $OUTPUT/f128_sqrt_rd.tv
|
||||
sed -ie 's/$/_4_3_1/' $OUTPUT/f128_sqrt_rnm.tv
|
||||
echo "Editing f16_eq test vectors"
|
||||
sed -ie 's/$/_0_2_2/' $OUTPUT/f16_eq_rne.tv
|
||||
sed -ie 's/$/_1_2_2/' $OUTPUT/f16_eq_rz.tv
|
||||
sed -ie 's/$/_3_2_2/' $OUTPUT/f16_eq_ru.tv
|
||||
sed -ie 's/$/_2_2_2/' $OUTPUT/f16_eq_rd.tv
|
||||
sed -ie 's/$/_4_2_2/' $OUTPUT/f16_eq_rnm.tv
|
||||
echo "Editing f32_eq test vectors"
|
||||
sed -ie 's/$/_0_0_2/' $OUTPUT/f32_eq_rne.tv
|
||||
sed -ie 's/$/_1_0_2/' $OUTPUT/f32_eq_rz.tv
|
||||
sed -ie 's/$/_3_0_2/' $OUTPUT/f32_eq_ru.tv
|
||||
sed -ie 's/$/_2_0_2/' $OUTPUT/f32_eq_rd.tv
|
||||
sed -ie 's/$/_4_0_2/' $OUTPUT/f32_eq_rnm.tv
|
||||
echo "Editing f64_eq test vectors"
|
||||
sed -ie 's/$/_0_1_2/' $OUTPUT/f64_eq_rne.tv
|
||||
sed -ie 's/$/_1_1_2/' $OUTPUT/f64_eq_rz.tv
|
||||
sed -ie 's/$/_3_1_2/' $OUTPUT/f64_eq_ru.tv
|
||||
sed -ie 's/$/_2_1_2/' $OUTPUT/f64_eq_rd.tv
|
||||
sed -ie 's/$/_4_1_2/' $OUTPUT/f64_eq_rnm.tv
|
||||
echo "Editing f128_eq test vectors"
|
||||
sed -ie 's/$/_0_3_2/' $OUTPUT/f128_eq_rne.tv
|
||||
sed -ie 's/$/_1_3_2/' $OUTPUT/f128_eq_rz.tv
|
||||
sed -ie 's/$/_3_3_2/' $OUTPUT/f128_eq_ru.tv
|
||||
sed -ie 's/$/_2_3_2/' $OUTPUT/f128_eq_rd.tv
|
||||
sed -ie 's/$/_4_3_2/' $OUTPUT/f128_eq_rnm.tv
|
||||
echo "Editing f16_le test vectors"
|
||||
sed -ie 's/$/_0_2_3/' $OUTPUT/f16_le_rne.tv
|
||||
sed -ie 's/$/_1_2_3/' $OUTPUT/f16_le_rz.tv
|
||||
sed -ie 's/$/_3_2_3/' $OUTPUT/f16_le_ru.tv
|
||||
sed -ie 's/$/_2_2_3/' $OUTPUT/f16_le_rd.tv
|
||||
sed -ie 's/$/_4_2_3/' $OUTPUT/f16_le_rnm.tv
|
||||
echo "Editing f32_le test vectors"
|
||||
sed -ie 's/$/_0_0_3/' $OUTPUT/f32_le_rne.tv
|
||||
sed -ie 's/$/_1_0_3/' $OUTPUT/f32_le_rz.tv
|
||||
sed -ie 's/$/_3_0_3/' $OUTPUT/f32_le_ru.tv
|
||||
sed -ie 's/$/_2_0_3/' $OUTPUT/f32_le_rd.tv
|
||||
sed -ie 's/$/_4_0_3/' $OUTPUT/f32_le_rnm.tv
|
||||
echo "Editing f64_le test vectors"
|
||||
sed -ie 's/$/_0_1_3/' $OUTPUT/f64_le_rne.tv
|
||||
sed -ie 's/$/_1_1_3/' $OUTPUT/f64_le_rz.tv
|
||||
sed -ie 's/$/_3_1_3/' $OUTPUT/f64_le_ru.tv
|
||||
sed -ie 's/$/_2_1_3/' $OUTPUT/f64_le_rd.tv
|
||||
sed -ie 's/$/_4_1_3/' $OUTPUT/f64_le_rnm.tv
|
||||
echo "Editing f128_le test vectors"
|
||||
sed -ie 's/$/_0_3_3/' $OUTPUT/f128_le_rne.tv
|
||||
sed -ie 's/$/_1_3_3/' $OUTPUT/f128_le_rz.tv
|
||||
sed -ie 's/$/_3_3_3/' $OUTPUT/f128_le_ru.tv
|
||||
sed -ie 's/$/_2_3_3/' $OUTPUT/f128_le_rd.tv
|
||||
sed -ie 's/$/_4_3_3/' $OUTPUT/f128_le_rnm.tv
|
||||
echo "Editing f16_lt test vectors"
|
||||
sed -ie 's/$/_0_2_1/' $OUTPUT/f16_lt_rne.tv
|
||||
sed -ie 's/$/_1_2_1/' $OUTPUT/f16_lt_rz.tv
|
||||
sed -ie 's/$/_3_2_1/' $OUTPUT/f16_lt_ru.tv
|
||||
sed -ie 's/$/_2_2_1/' $OUTPUT/f16_lt_rd.tv
|
||||
sed -ie 's/$/_4_2_1/' $OUTPUT/f16_lt_rnm.tv
|
||||
echo "Editing f32_lt test vectors"
|
||||
sed -ie 's/$/_0_0_1/' $OUTPUT/f32_lt_rne.tv
|
||||
sed -ie 's/$/_1_0_1/' $OUTPUT/f32_lt_rz.tv
|
||||
sed -ie 's/$/_3_0_1/' $OUTPUT/f32_lt_ru.tv
|
||||
sed -ie 's/$/_2_0_1/' $OUTPUT/f32_lt_rd.tv
|
||||
sed -ie 's/$/_4_0_1/' $OUTPUT/f32_lt_rnm.tv
|
||||
echo "Editing f64_lt test vectors"
|
||||
sed -ie 's/$/_0_1_1/' $OUTPUT/f64_lt_rne.tv
|
||||
sed -ie 's/$/_1_1_1/' $OUTPUT/f64_lt_rz.tv
|
||||
sed -ie 's/$/_3_1_1/' $OUTPUT/f64_lt_ru.tv
|
||||
sed -ie 's/$/_2_1_1/' $OUTPUT/f64_lt_rd.tv
|
||||
sed -ie 's/$/_4_1_1/' $OUTPUT/f64_lt_rnm.tv
|
||||
echo "Editing f128_lt test vectors"
|
||||
sed -ie 's/$/_0_3_1/' $OUTPUT/f128_lt_rne.tv
|
||||
sed -ie 's/$/_1_3_1/' $OUTPUT/f128_lt_rz.tv
|
||||
sed -ie 's/$/_3_3_1/' $OUTPUT/f128_lt_ru.tv
|
||||
sed -ie 's/$/_2_3_1/' $OUTPUT/f128_lt_rd.tv
|
||||
sed -ie 's/$/_4_3_1/' $OUTPUT/f128_lt_rnm.tv
|
||||
echo "Editing f16_mulAdd test vectors"
|
||||
sed -ie 's/$/_0_2_0/' $OUTPUT/f16_mulAdd_rne.tv
|
||||
sed -ie 's/$/_1_2_0/' $OUTPUT/f16_mulAdd_rz.tv
|
||||
sed -ie 's/$/_3_2_0/' $OUTPUT/f16_mulAdd_ru.tv
|
||||
sed -ie 's/$/_2_2_0/' $OUTPUT/f16_mulAdd_rd.tv
|
||||
sed -ie 's/$/_4_2_0/' $OUTPUT/f16_mulAdd_rnm.tv
|
||||
echo "Editing f32_mulAdd test vectors"
|
||||
sed -ie 's/$/_0_0_0/' $OUTPUT/f32_mulAdd_rne.tv
|
||||
sed -ie 's/$/_1_0_0/' $OUTPUT/f32_mulAdd_rz.tv
|
||||
sed -ie 's/$/_3_0_0/' $OUTPUT/f32_mulAdd_ru.tv
|
||||
sed -ie 's/$/_2_0_0/' $OUTPUT/f32_mulAdd_rd.tv
|
||||
sed -ie 's/$/_4_0_0/' $OUTPUT/f32_mulAdd_rnm.tv
|
||||
echo "Editing f64_mulAdd test vectors"
|
||||
sed -ie 's/$/_0_1_0/' $OUTPUT/f64_mulAdd_rne.tv
|
||||
sed -ie 's/$/_1_1_0/' $OUTPUT/f64_mulAdd_rz.tv
|
||||
sed -ie 's/$/_3_1_0/' $OUTPUT/f64_mulAdd_ru.tv
|
||||
sed -ie 's/$/_2_1_0/' $OUTPUT/f64_mulAdd_rd.tv
|
||||
sed -ie 's/$/_4_1_0/' $OUTPUT/f64_mulAdd_rnm.tv
|
||||
echo "Editing f128_mulAdd test vectors"
|
||||
sed -ie 's/$/_0_3_0/' $OUTPUT/f128_mulAdd_rne.tv
|
||||
sed -ie 's/$/_1_3_0/' $OUTPUT/f128_mulAdd_rz.tv
|
||||
sed -ie 's/$/_3_3_0/' $OUTPUT/f128_mulAdd_ru.tv
|
||||
sed -ie 's/$/_2_3_0/' $OUTPUT/f128_mulAdd_rd.tv
|
||||
sed -ie 's/$/_4_3_0/' $OUTPUT/f128_mulAdd_rnm.tv
|
||||
rm vectors/*.tve
|
||||
Loading…
Reference in New Issue
Block a user