mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 10:15:19 +00:00
Repaired wavefile and fixed modelsim warning.
This commit is contained in:
Ross Thompson
parent
1476a79ea2
commit
3475e142a5
@ -177,15 +177,15 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK
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add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED
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add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState
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add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/interlockfsm/InterlockCurrState
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add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
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add wave -noupdate -group lsu /testbench/dut/core/lsu/InterlockStall
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add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/SelUncachedAdr
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add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busfsm/BusCurrState
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add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr
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add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
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add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
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add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusRead
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add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusWrite
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@ -201,7 +201,7 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMWordEnable
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMLineWayWriteEnable
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SelAdr
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/MEM_VIRTMEM/SelReplayCPURequest
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/SelReplayCPURequest
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/RAdr
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@ -349,15 +349,15 @@ add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpch
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add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
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add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
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add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
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add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/WalkerState
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/PCF
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/HPTWAdr
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/PTE
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/ITLBMissF
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/DTLBMissM
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/ITLBWriteF
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/DTLBWriteM
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add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/WalkerState
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/PCF
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/HPTWReadPTE
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/HPTWAdr
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/PTE
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/ITLBMissF
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/DTLBMissM
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/ITLBWriteF
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/DTLBWriteM
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
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@ -434,14 +434,13 @@ add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
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add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
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add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
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add wave -noupdate /testbench/dut/core/priv/priv/csr/MEPC_REGW
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add wave -noupdate /testbench/dut/core/lsu/LocalLSUBusAdr
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add wave -noupdate /testbench/dut/core/lsu/bus/busfsm/BusNextState
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add wave -noupdate /testbench/dut/core/lsu/bus/busfsm/DCacheFetchLine
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add wave -noupdate /testbench/dut/core/lsu/bus/busfsm/DCacheWriteLine
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add wave -noupdate -expand -group ifu -color Gold /testbench/dut/core/ifu/bus/busfsm/BusCurrState
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add wave -noupdate /testbench/dut/core/lsu/bus/busdp/LocalLSUBusAdr
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add wave -noupdate /testbench/dut/core/lsu/bus/busdp/busfsm/DCacheFetchLine
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add wave -noupdate /testbench/dut/core/lsu/bus/busdp/busfsm/DCacheWriteLine
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add wave -noupdate -expand -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
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add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusRead
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add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusAdr
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add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/bus/busfsm/LSUBusAck
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add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusAck
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add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusHRDATA
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add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
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add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
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@ -49,7 +49,7 @@ module busdp #(parameter WORDSPERLINE, parameter LINELEN)
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// cache interface.
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input logic [`PA_BITS-1:0] DCacheBusAdr,
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input logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0],
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input var logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0],
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input logic DCacheFetchLine,
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input logic DCacheWriteLine,
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output logic DCacheBusAck,
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