cvw/pipelined
2022-03-29 23:48:19 -05:00
..
config reverted temporary change to configs. 2022-03-22 22:31:34 -05:00
fpu-testfloat/FMA/tbgen FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
misc Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
regression Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:06:27 +00:00
src rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory. 2022-03-29 23:48:19 -05:00
srt Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath 2022-02-28 20:50:51 +00:00
testbench rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory. 2022-03-29 23:48:19 -05:00