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Six tests passing and a bunch of sizizing issues fixed

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This commit is contained in:
cturek 2022-07-14 19:38:27 +00:00
parent 83cc429700
commit cabd41a5a0
4 changed files with 33 additions and 24 deletions
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2
pipelined/config/shared/wally-shared.vh
View File

@ -104,6 +104,8 @@
`define RADIX 32'h4
`define DIVCOPIES 32'h4
`define DIVLEN ((`NF < `XLEN) ? (`XLEN) : (`NF + 3))
`define EXTRAFRACBITS ((`NF<(`XLEN)) ? (`XLEN - `NF) : 3)
`define EXTRAINTBITS ((`NF<(`XLEN)) ? 0 : (`NF - `XLEN + 3))
`define DIVRESLEN ((`NF>`XLEN) ? `NF+4 : `XLEN)
`define LOGR ((`RADIX==2) ? 32'h1 : 32'h2)
// FPDUR = ceil(DIVRESLEN/(LOGR*DIVCOPIES))

15
pipelined/srt/sqrttestgen.c
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@ -30,11 +30,11 @@ void main(void)
FILE *fptr;
double aFrac, rFrac;
int aExp, rExp;
double mans[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625,
double mans[ENTRIES] = {1, 1849.0/1024, 1.25, 1.125, 1.0625,
1.75, 1.875, 1.99999,
1.1, 1.2, 1.01, 1.001, 1.0001,
2/1.1, 2/1.5, 2/1.25, 2/1.125};
double exps[ENTRIES] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
double exps[ENTRIES] = {0, 0, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11, 12, 13, 14, 15, 16};
int i;
int bias = 1023;
@ -47,10 +47,19 @@ void main(void)
for (i=0; i<ENTRIES; i++) {
aFrac = mans[i];
aExp = exps[i] + bias;
rFrac = sqrt(aFrac * pow(2, aExp - bias));
rFrac = sqrt(aFrac * pow(2, exps[i]));
rExp = (int) (log(rFrac)/log(2) + bias);
output(fptr, aExp, aFrac, rExp, rFrac);
}
// WS
// Test 1: sqrt(1) = 1 0000 0000 0000 00
// Test 2: sqrt(1849/1024) = 43/32 0000 1100 1110 01
// Test 3: sqrt(5) 0000 0100 0000 00
// Test 4: sqrt(9) = 3 1111 1001 0000 00
// Test 5: sqrt(17) 0000 0001 0000 00
// Test 6: sqrt(56) 1111 1110 0000 00
// Test 7: sqrt(120) 0000 1110 0000 00
// for (i = 0; i< RANDOM_VECS; i++) {
// a = random_input();

8
pipelined/srt/srt.sv
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@ -29,8 +29,6 @@
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
`define EXTRAFRACBITS ((`NF<(`XLEN)) ? (`XLEN - `NF + 2) : 2)
`define EXTRAINTBITS ((`NF<(`XLEN)) ? 2 : (`NF - `XLEN + 2))
module srt (
input logic clk,
@ -49,7 +47,7 @@ module srt (
input logic Int, // Choose integer inputs
input logic Sqrt, // perform square root, not divide
output logic rsign, done,
output logic [`DIVLEN-3:0] Rem, Quot, // *** later handle integers
output logic [`DIVLEN-2:0] Rem, Quot, // *** later handle integers
output logic [`NE-1:0] rExp,
output logic [3:0] Flags
);
@ -268,7 +266,7 @@ module sotfc2(
input logic Start,
input logic sp, sn,
input logic [`DIVLEN+3:0] C,
output logic [`DIVLEN-3:0] Sq,
output logic [`DIVLEN-2:0] Sq,
output logic [`DIVLEN+3:0] F
);
// The on-the-fly converter transfers the square root
@ -292,7 +290,7 @@ module sotfc2(
SMNext = SM | ((C << 1) & ~(C << 2));
end
end
assign Sq = S[`DIVLEN] ? S[`DIVLEN-1:2] : S[`DIVLEN-2:1];
assign Sq = S[`DIVLEN] ? S[`DIVLEN-1:1] : S[`DIVLEN-2:0];
fsel2 fsel(sp, sn, C, S, SM, F);

32
pipelined/srt/testbench.sv
View File

@ -1,4 +1,4 @@
`define DIVLEN 64
`include "wally-config.vh"
/////////////
// counter //
@ -39,17 +39,17 @@ endmodule
// testbench //
//////////
module testbench;
logic clk;
logic req;
logic done;
logic Int;
logic [63:0] a, b;
logic [51:0] afrac, bfrac;
logic [10:0] aExp, bExp;
logic asign, bsign;
logic [51:0] r;
logic [63:0] rInt;
logic [`DIVLEN-1:0] Quot;
logic clk;
logic req;
logic done;
logic Int;
logic [`XLEN-1:0] a, b;
logic [`NF-1:0] afrac, bfrac;
logic [`NE-1:0] aExp, bExp;
logic asign, bsign;
logic [`NF-1:0] r;
logic [`XLEN-1:0] rInt;
logic [`DIVLEN-2:0] Quot;
// Test parameters
parameter MEM_SIZE = 40000;
@ -108,16 +108,16 @@ module testbench;
b = Vec[`memb];
{bsign, bExp, bfrac} = b;
nextr = Vec[`memr];
r = Quot[(`DIVLEN - 1):(`DIVLEN - 52)];
rInt = Quot;
r = Quot[(`DIVLEN - 2):(`DIVLEN - `NF - 1)];
rInt = {1'b1, Quot};
req <= #5 1;
end
// Apply directed test vectors read from file.
always @(posedge clk) begin
r = Quot[(`DIVLEN - 1):(`DIVLEN - 52)];
rInt = Quot;
r = Quot[(`DIVLEN - 2):(`DIVLEN - `NF - 1)];
rInt = {1'b1, Quot};
if (done) begin
if (~Int & ~Sqrt) begin
req <= #5 1;