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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
Katherine Parry 2022-05-23 23:11:41 +00:00
commit 18bdaf0179
13 changed files with 1639 additions and 452 deletions
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2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86

167
fpga/constraints/debug2.xdc
View File

@ -95,22 +95,29 @@ create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe19]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe20]
set_property port_width 5 [get_debug_ports u_ila_0/probe20]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[63]} ]]
connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[4]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe21]
set_property port_width 8 [get_debug_ports u_ila_0/probe21]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[9]} ]]
connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe22]
set_property port_width 64 [get_debug_ports u_ila_0/probe22]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[9]} ]]
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 63 [get_debug_ports u_ila_0/probe23]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[63]} ]]
connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe24]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
@ -122,11 +129,13 @@ connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncore/sdc
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe26]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[0]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[1]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[2]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[3]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[4]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[5]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[6]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[7]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[8]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[9]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[10]} {wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[11]} ]]
connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[0]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[1]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[2]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[3]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[4]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[5]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[6]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[7]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[8]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[9]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[10]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[11]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe27]
set_property port_width 4 [get_debug_ports u_ila_0/probe27]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[63]} ]]
connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 6 [get_debug_ports u_ila_0/probe28]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
@ -526,9 +535,9 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113]
connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/core/ebu/HPROT[0]} {wallypipelinedsoc/core/ebu/HPROT[1]} {wallypipelinedsoc/core/ebu/HPROT[2]} {wallypipelinedsoc/core/ebu/HPROT[3]}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe114]
set_property port_width 4 [get_debug_ports u_ila_0/probe114]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe114]
connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/core/ebu/HMASTLOCK}]]
connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore/uart.uart/u/IER[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe115]
@ -633,82 +642,76 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133]
connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe134]
set_property port_width 8 [get_debug_ports u_ila_0/probe134]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe134]
connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[0]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[1]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[2]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[3]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[4]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[5]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[6]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[7]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[8]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[9]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[10]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[11]} ]]
connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe135]
set_property port_width 8 [get_debug_ports u_ila_0/probe135]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe135]
connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncore/plic.plic/requests[12]}]]
connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe136]
set_property port_width 8 [get_debug_ports u_ila_0/probe136]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe136]
connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[12]}]]
connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe137]
set_property port_width 8 [get_debug_ports u_ila_0/probe137]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137]
connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore/plic.plic/intPending[12]}]]
connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe138]
set_property port_width 2 [get_debug_ports u_ila_0/probe138]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138]
connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[0]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[1]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[2]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[3]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[4]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[5]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[6]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[7]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[8]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[9]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[10]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11]}]]
connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/txstate[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe139]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139]
connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM}]]
connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe140]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140]
connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM} ]]
connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe141]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141]
connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM} ]]
connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe142]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142]
connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM} ]]
connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]]
create_debug_port u_ila_0 probe
set_property port_width 70 [get_debug_ports u_ila_0/probe143]
set_property port_width 11 [get_debug_ports u_ila_0/probe143]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143]
connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10]} ]]
connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[10]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe144]
set_property port_width 1 [get_debug_ports u_ila_0/probe144]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144]
connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][2]} ]]
connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxparityerr} ]]
create_debug_port u_ila_0 probe
set_property port_width 10 [get_debug_ports u_ila_0/probe145]
set_property port_width 2 [get_debug_ports u_ila_0/probe145]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145]
connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10]} ]]
connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/rxstate[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe146]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146]
connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsoc/uncore/clint.clint/MTIME[0]} {wallypipelinedsoc/uncore/clint.clint/MTIME[1]} {wallypipelinedsoc/uncore/clint.clint/MTIME[2]} {wallypipelinedsoc/uncore/clint.clint/MTIME[3]} {wallypipelinedsoc/uncore/clint.clint/MTIME[4]} {wallypipelinedsoc/uncore/clint.clint/MTIME[5]} {wallypipelinedsoc/uncore/clint.clint/MTIME[6]} {wallypipelinedsoc/uncore/clint.clint/MTIME[7]} {wallypipelinedsoc/uncore/clint.clint/MTIME[8]} {wallypipelinedsoc/uncore/clint.clint/MTIME[9]} {wallypipelinedsoc/uncore/clint.clint/MTIME[10]} {wallypipelinedsoc/uncore/clint.clint/MTIME[11]} {wallypipelinedsoc/uncore/clint.clint/MTIME[12]} {wallypipelinedsoc/uncore/clint.clint/MTIME[13]} {wallypipelinedsoc/uncore/clint.clint/MTIME[14]} {wallypipelinedsoc/uncore/clint.clint/MTIME[15]} {wallypipelinedsoc/uncore/clint.clint/MTIME[16]} {wallypipelinedsoc/uncore/clint.clint/MTIME[17]} {wallypipelinedsoc/uncore/clint.clint/MTIME[18]} {wallypipelinedsoc/uncore/clint.clint/MTIME[19]} {wallypipelinedsoc/uncore/clint.clint/MTIME[20]} {wallypipelinedsoc/uncore/clint.clint/MTIME[21]} {wallypipelinedsoc/uncore/clint.clint/MTIME[22]} {wallypipelinedsoc/uncore/clint.clint/MTIME[23]} {wallypipelinedsoc/uncore/clint.clint/MTIME[24]} {wallypipelinedsoc/uncore/clint.clint/MTIME[25]} {wallypipelinedsoc/uncore/clint.clint/MTIME[26]} {wallypipelinedsoc/uncore/clint.clint/MTIME[27]} {wallypipelinedsoc/uncore/clint.clint/MTIME[28]} {wallypipelinedsoc/uncore/clint.clint/MTIME[29]} {wallypipelinedsoc/uncore/clint.clint/MTIME[30]} {wallypipelinedsoc/uncore/clint.clint/MTIME[31]} {wallypipelinedsoc/uncore/clint.clint/MTIME[32]} {wallypipelinedsoc/uncore/clint.clint/MTIME[33]} {wallypipelinedsoc/uncore/clint.clint/MTIME[34]} {wallypipelinedsoc/uncore/clint.clint/MTIME[35]} {wallypipelinedsoc/uncore/clint.clint/MTIME[36]} {wallypipelinedsoc/uncore/clint.clint/MTIME[37]} {wallypipelinedsoc/uncore/clint.clint/MTIME[38]} {wallypipelinedsoc/uncore/clint.clint/MTIME[39]} {wallypipelinedsoc/uncore/clint.clint/MTIME[40]} {wallypipelinedsoc/uncore/clint.clint/MTIME[41]} {wallypipelinedsoc/uncore/clint.clint/MTIME[42]} {wallypipelinedsoc/uncore/clint.clint/MTIME[43]} {wallypipelinedsoc/uncore/clint.clint/MTIME[44]} {wallypipelinedsoc/uncore/clint.clint/MTIME[45]} {wallypipelinedsoc/uncore/clint.clint/MTIME[46]} {wallypipelinedsoc/uncore/clint.clint/MTIME[47]} {wallypipelinedsoc/uncore/clint.clint/MTIME[48]} {wallypipelinedsoc/uncore/clint.clint/MTIME[49]} {wallypipelinedsoc/uncore/clint.clint/MTIME[50]} {wallypipelinedsoc/uncore/clint.clint/MTIME[51]} {wallypipelinedsoc/uncore/clint.clint/MTIME[52]} {wallypipelinedsoc/uncore/clint.clint/MTIME[53]} {wallypipelinedsoc/uncore/clint.clint/MTIME[54]} {wallypipelinedsoc/uncore/clint.clint/MTIME[55]} {wallypipelinedsoc/uncore/clint.clint/MTIME[56]} {wallypipelinedsoc/uncore/clint.clint/MTIME[57]} {wallypipelinedsoc/uncore/clint.clint/MTIME[58]} {wallypipelinedsoc/uncore/clint.clint/MTIME[59]} {wallypipelinedsoc/uncore/clint.clint/MTIME[60]} {wallypipelinedsoc/uncore/clint.clint/MTIME[61]} {wallypipelinedsoc/uncore/clint.clint/MTIME[62]} {wallypipelinedsoc/uncore/clint.clint/MTIME[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe147]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147]
connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[0]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[1]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[2]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[3]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[4]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[5]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[6]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[7]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[8]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[9]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[10]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[11]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[12]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[13]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[14]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[15]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[16]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[17]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[18]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[19]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[20]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[21]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[22]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[23]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[24]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[25]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[26]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[27]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[28]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[29]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[30]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[31]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[32]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[33]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[34]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[35]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[36]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[37]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[38]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[39]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[40]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[41]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[42]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[43]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[44]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[45]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[46]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[47]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[48]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[49]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[50]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[51]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[52]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[53]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[54]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[55]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[56]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[57]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[58]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[59]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[60]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[61]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[62]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe148]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148]
@ -744,74 +747,96 @@ set_property port_width 64 [get_debug_ports u_ila_0/probe154]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154]
connect_debug_port u_ila_0/probe154 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 11 [get_debug_ports u_ila_0/probe155]
set_property port_width 8 [get_debug_ports u_ila_0/probe155]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155]
connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[10]} ]]
connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe156]
set_property port_width 12 [get_debug_ports u_ila_0/probe156]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156]
connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxparityerr} ]]
connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncore/plic.plic/requests[12]}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe157]
set_property port_width 12 [get_debug_ports u_ila_0/probe157]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157]
connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/rxstate[1]} ]]
connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[12]}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe158]
set_property port_width 12 [get_debug_ports u_ila_0/probe158]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158]
connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/txstate[1]} ]]
connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore/plic.plic/intPending[12]}]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe159]
set_property port_width 70 [get_debug_ports u_ila_0/probe159]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159]
connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[7]} ]]
connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe160]
set_property port_width 3 [get_debug_ports u_ila_0/probe160]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160]
connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[7]} ]]
connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe161]
set_property port_width 10 [get_debug_ports u_ila_0/probe161]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161]
connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[7]} ]]
connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe162]
set_property port_width 3 [get_debug_ports u_ila_0/probe162]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162]
connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[7]} ]]
connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/intrID[0]} {wallypipelinedsoc/uncore/uart.uart/u/intrID[1]} {wallypipelinedsoc/uncore/uart.uart/u/intrID[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe163]
set_property port_width 1 [get_debug_ports u_ila_0/probe163]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163]
connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[7]} ]]
connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxdataavailintr} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe164]
set_property port_width 1 [get_debug_ports u_ila_0/probe164]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164]
connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore/uart.uart/u/IER[3]} ]]
connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/fifoenabled} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe165]
set_property port_width 1 [get_debug_ports u_ila_0/probe165]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165]
connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[3]} ]]
connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxfifotriggered} ]]
create_debug_port u_ila_0 probe
set_property port_width 5 [get_debug_ports u_ila_0/probe166]
set_property port_width 4 [get_debug_ports u_ila_0/probe166]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166]
connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[4]} ]]
connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifoentries[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe167]
set_property port_width 1 [get_debug_ports u_ila_0/probe167]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167]
connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[7]} ]]
connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxdataready} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe168]
set_property port_width 1 [get_debug_ports u_ila_0/probe168]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168]
connect_debug_port u_ila_0/probe168 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
connect_debug_port u_ila_0/probe168 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/THRE_IP} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe169]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169]
connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/modemstatusintr} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe170]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170]
connect_debug_port u_ila_0/probe170 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxfifohead[0]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifohead[1]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifohead[2]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifohead[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe171]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171]
connect_debug_port u_ila_0/probe171 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxfifotail[0]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifotail[1]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifotail[2]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifotail[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe172]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172]
connect_debug_port u_ila_0/probe172 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RXerrIP} ]]

24
linux/testvector-generation/debug.sh
View File

@ -4,18 +4,18 @@ tvDir=$RISCV/linux-testvectors
tcpPort=1239
# QEMU Simulation
(qemu-system-riscv64 \
qemu-system-riscv64 \
-M virt -dtb $imageDir/wally-virt.dtb \
-nographic \
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on \
> ./qemu-serial \
-gdb tcp::$tcpPort -S) \
& riscv64-unknown-elf-gdb -quiet \
-ex "set pagination off" \
-ex "set logging overwrite on" \
-ex "set logging redirect on" \
-ex "set confirm off" \
-ex "target extended-remote :$tcpPort" \
-ex "maintenance packet Qqemu.PhyMemMode:1" \
-ex "file $imageDir/vmlinux"
-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on
# > ./qemu-serial \
# -gdb tcp::$tcpPort -S) \
# & riscv64-unknown-elf-gdb -quiet \
# -ex "set pagination off" \
# -ex "set logging overwrite on" \
# -ex "set logging redirect on" \
# -ex "set confirm off" \
# -ex "target extended-remote :$tcpPort" \
# -ex "maintenance packet Qqemu.PhyMemMode:1" \
# -ex "file $imageDir/vmlinux"

369
pipelined/src/ppa/ppa.sv
View File

@ -214,7 +214,39 @@ module ppa_alu #(parameter WIDTH=32) (
else assign Result = FullResult;
endmodule
module ppa_shiftleft #(parameter WIDTH=32) (
module ppa_shiftleft_8 #(parameter WIDTH=8) (
input logic [WIDTH-1:0] a,
input logic [$clog2(WIDTH)-1:0] amt,
output logic [WIDTH-1:0] y);
assign y = a << amt;
endmodule
module ppa_shiftleft_16 #(parameter WIDTH=16) (
input logic [WIDTH-1:0] a,
input logic [$clog2(WIDTH)-1:0] amt,
output logic [WIDTH-1:0] y);
assign y = a << amt;
endmodule
module ppa_shiftleft_32 #(parameter WIDTH=32) (
input logic [WIDTH-1:0] a,
input logic [$clog2(WIDTH)-1:0] amt,
output logic [WIDTH-1:0] y);
assign y = a << amt;
endmodule
module ppa_shiftleft_64 #(parameter WIDTH=64) (
input logic [WIDTH-1:0] a,
input logic [$clog2(WIDTH)-1:0] amt,
output logic [WIDTH-1:0] y);
assign y = a << amt;
endmodule
module ppa_shiftleft_128 #(parameter WIDTH=128) (
input logic [WIDTH-1:0] a,
input logic [$clog2(WIDTH)-1:0] amt,
output logic [WIDTH-1:0] y);
@ -329,30 +361,132 @@ module ppa_prioritythermometer #(parameter N = 8) (
end
endmodule
module ppa_priorityonehot #(parameter N = 8) (
input logic [N-1:0] a,
output logic [N-1:0] y);
logic [N-1:0] nolower;
module ppa_priorityonehot #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] a,
output logic [WIDTH-1:0] y);
logic [WIDTH-1:0] nolower;
// create thermometer code mask
ppa_prioritythermometer #(N) maskgen(.a({a[N-2:0], 1'b0}), .y(nolower));
ppa_prioritythermometer #(WIDTH) maskgen(.a({a[WIDTH-2:0], 1'b0}), .y(nolower));
assign y = a & nolower;
endmodule
module ppa_priorityencoder #(parameter N = 8) (
input logic [N-1:0] a,
output logic [$clog2(N)-1:0] y);
// Carefully crafted so design compiler will synthesize into a fast tree structure
// Rather than linear.
module ppa_priorityonehot_8 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] a,
output logic [WIDTH-1:0] y);
logic [WIDTH-1:0] nolower;
// create thermometer code mask
ppa_priorityonehot #(WIDTH) poh (.*);
endmodule
module ppa_priorityonehot_16 #(parameter WIDTH = 16) (
input logic [WIDTH-1:0] a,
output logic [WIDTH-1:0] y);
logic [WIDTH-1:0] nolower;
// create thermometer code mask
ppa_priorityonehot #(WIDTH) poh (.*);
endmodule
module ppa_priorityonehot_32 #(parameter WIDTH = 32) (
input logic [WIDTH-1:0] a,
output logic [WIDTH-1:0] y);
logic [WIDTH-1:0] nolower;
// create thermometer code mask
ppa_priorityonehot #(WIDTH) poh (.*);
endmodule
module ppa_priorityonehot_64 #(parameter WIDTH = 64) (
input logic [WIDTH-1:0] a,
output logic [WIDTH-1:0] y);
logic [WIDTH-1:0] nolower;
// create thermometer code mask
ppa_priorityonehot #(WIDTH) poh (.*);
endmodule
module ppa_priorityonehot_128 #(parameter WIDTH = 128) (
input logic [WIDTH-1:0] a,
output logic [WIDTH-1:0] y);
logic [WIDTH-1:0] nolower;
// create thermometer code mask
ppa_priorityonehot #(WIDTH) poh (.*);
endmodule
module ppa_priorityencoder_8 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] a,
output logic [$clog2(WIDTH)-1:0] y);
ppa_priorityencoder #(WIDTH) pe (.*);
endmodule
module ppa_priorityencoder_16 #(parameter WIDTH = 16) (
input logic [WIDTH-1:0] a,
output logic [$clog2(WIDTH)-1:0] y);
ppa_priorityencoder #(WIDTH) pe (.*);
endmodule
module ppa_priorityencoder_32 #(parameter WIDTH = 32) (
input logic [WIDTH-1:0] a,
output logic [$clog2(WIDTH)-1:0] y);
ppa_priorityencoder #(WIDTH) pe (.*);
endmodule
module ppa_priorityencoder_64 #(parameter WIDTH = 64) (
input logic [WIDTH-1:0] a,
output logic [$clog2(WIDTH)-1:0] y);
ppa_priorityencoder #(WIDTH) pe (.*);
endmodule
module ppa_priorityencoder_128 #(parameter WIDTH = 128) (
input logic [WIDTH-1:0] a,
output logic [$clog2(WIDTH)-1:0] y);
ppa_priorityencoder #(WIDTH) pe (.*);
endmodule
module ppa_priorityencoder #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] a,
output logic [$clog2(WIDTH)-1:0] y);
int i;
always_comb
for (i=0; i<N; i++) begin:pri
for (i=0; i<WIDTH; i++) begin:pri
if (a[i]) y= i;
end
endmodule
module ppa_decoder_8 #(parameter WIDTH = 8) (
input logic [$clog2(WIDTH)-1:0] a,
output logic [WIDTH-1:0] y);
ppa_decoder #(WIDTH) dec (.*);
endmodule
module ppa_decoder_16 #(parameter WIDTH = 16) (
input logic [$clog2(WIDTH)-1:0] a,
output logic [WIDTH-1:0] y);
ppa_decoder #(WIDTH) dec (.*);
endmodule
module ppa_decoder_32 #(parameter WIDTH = 32) (
input logic [$clog2(WIDTH)-1:0] a,
output logic [WIDTH-1:0] y);
ppa_decoder #(WIDTH) dec (.*);
endmodule
module ppa_decoder_64 #(parameter WIDTH = 64) (
input logic [$clog2(WIDTH)-1:0] a,
output logic [WIDTH-1:0] y);
ppa_decoder #(WIDTH) dec (.*);
endmodule
module ppa_decoder_128 #(parameter WIDTH = 128) (
input logic [$clog2(WIDTH)-1:0] a,
output logic [WIDTH-1:0] y);
ppa_decoder #(WIDTH) dec (.*);
endmodule
module ppa_decoder #(parameter WIDTH = 8) (
input logic [$clog2(WIDTH)-1:0] a,
output logic [WIDTH-1:0] y);
@ -362,7 +496,7 @@ module ppa_decoder #(parameter WIDTH = 8) (
end
endmodule
module ppa_mux2_1 #(parameter WIDTH = 1) (
module ppa_mux2_8 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
@ -404,7 +538,7 @@ endmodule
// *** some way to express data-critical inputs
module ppa_flop #(parameter WIDTH = 8) (
module ppa_flop_8 #(parameter WIDTH = 8) (
input logic clk,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
@ -413,7 +547,43 @@ module ppa_flop #(parameter WIDTH = 8) (
q <= #1 d;
endmodule
module ppa_flopr #(parameter WIDTH = 8) (
module ppa_flop_16 #(parameter WIDTH = 16) (
input logic clk,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
q <= #1 d;
endmodule
module ppa_flop_32 #(parameter WIDTH = 32) (
input logic clk,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
q <= #1 d;
endmodule
module ppa_flop_64 #(parameter WIDTH = 64) (
input logic clk,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
q <= #1 d;
endmodule
module ppa_flop_128 #(parameter WIDTH = 128) (
input logic clk,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
q <= #1 d;
endmodule
module ppa_flopr_8 #(parameter WIDTH = 8) (
input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
@ -423,7 +593,47 @@ module ppa_flopr #(parameter WIDTH = 8) (
else q <= #1 d;
endmodule
module ppa_floprasynnc #(parameter WIDTH = 8) (
module ppa_flopr_16 #(parameter WIDTH = 16) (
input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (reset) q <= #1 0;
else q <= #1 d;
endmodule
module ppa_flopr_32 #(parameter WIDTH = 32) (
input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (reset) q <= #1 0;
else q <= #1 d;
endmodule
module ppa_flopr_64 #(parameter WIDTH = 64) (
input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (reset) q <= #1 0;
else q <= #1 d;
endmodule
module ppa_flopr_128 #(parameter WIDTH = 128) (
input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (reset) q <= #1 0;
else q <= #1 d;
endmodule
module ppa_floprasync_8 #(parameter WIDTH = 8) (
input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
@ -433,7 +643,47 @@ module ppa_floprasynnc #(parameter WIDTH = 8) (
else q <= #1 d;
endmodule
module ppa_flopenr #(parameter WIDTH = 8) (
module ppa_floprasync_16 #(parameter WIDTH = 16) (
input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk or posedge reset)
if (reset) q <= #1 0;
else q <= #1 d;
endmodule
module ppa_floprasync_32 #(parameter WIDTH = 32) (
input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk or posedge reset)
if (reset) q <= #1 0;
else q <= #1 d;
endmodule
module ppa_floprasync_64 #(parameter WIDTH = 64) (
input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk or posedge reset)
if (reset) q <= #1 0;
else q <= #1 d;
endmodule
module ppa_floprasync_128 #(parameter WIDTH = 128) (
input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk or posedge reset)
if (reset) q <= #1 0;
else q <= #1 d;
endmodule
module ppa_flopenr_8 #(parameter WIDTH = 8) (
input logic clk, reset, en,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
@ -442,3 +692,88 @@ module ppa_flopenr #(parameter WIDTH = 8) (
if (reset) q <= #1 0;
else if (en) q <= #1 d;
endmodule
module ppa_flopenr_16 #(parameter WIDTH = 16) (
input logic clk, reset, en,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (reset) q <= #1 0;
else if (en) q <= #1 d;
endmodule
module ppa_flopenr_32 #(parameter WIDTH = 32) (
input logic clk, reset, en,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (reset) q <= #1 0;
else if (en) q <= #1 d;
endmodule
module ppa_flopenr_64 #(parameter WIDTH = 64) (
input logic clk, reset, en,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (reset) q <= #1 0;
else if (en) q <= #1 d;
endmodule
module ppa_flopenr_128 #(parameter WIDTH = 128) (
input logic clk, reset, en,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (reset) q <= #1 0;
else if (en) q <= #1 d;
endmodule
module ppa_csa_8 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] a, b, c,
output logic [WIDTH-1:0] sum, carry);
assign sum = a ^ b ^ c;
assign carry = (a & (b | c)) | (b & c);
endmodule
module ppa_csa_16 #(parameter WIDTH = 16) (
input logic [WIDTH-1:0] a, b, c,
output logic [WIDTH-1:0] sum, carry);
assign sum = a ^ b ^ c;
assign carry = (a & (b | c)) | (b & c);
endmodule
module ppa_csa_32 #(parameter WIDTH = 32) (
input logic [WIDTH-1:0] a, b, c,
output logic [WIDTH-1:0] sum, carry);
assign sum = a ^ b ^ c;
assign carry = (a & (b | c)) | (b & c);
endmodule
module ppa_csa_64 #(parameter WIDTH = 64) (
input logic [WIDTH-1:0] a, b, c,
output logic [WIDTH-1:0] sum, carry);
assign sum = a ^ b ^ c;
assign carry = (a & (b | c)) | (b & c);
endmodule
module ppa_csa_128 #(parameter WIDTH = 128) (
input logic [WIDTH-1:0] a, b, c,
output logic [WIDTH-1:0] sum, carry);
assign sum = a ^ b ^ c;
assign carry = (a & (b | c)) | (b & c);
endmodule

2
pipelined/src/privileged/csrs.sv
View File

@ -57,7 +57,7 @@ module csrs #(parameter
input logic STATUS_TVM,
input logic [`XLEN-1:0] CSRWriteValM,
input logic [1:0] PrivilegeModeW,
output logic [`XLEN-1:0] CSRSReadValM, STVEC_REGW,
(* mark_debug = "true" *) output logic [`XLEN-1:0] CSRSReadValM, STVEC_REGW,
(* mark_debug = "true" *) output logic [`XLEN-1:0] SEPC_REGW,
output logic [31:0] SCOUNTEREN_REGW,
output logic [`XLEN-1:0] SATP_REGW,

3
pipelined/src/uncore/plic.sv
View File

@ -176,7 +176,8 @@ module plic (
end
// pending interrupt requests
assign nextIntPending = (intPending | requests) & ~intInProgress;
//assign nextIntPending = (intPending | requests) & ~intInProgress;
assign nextIntPending = requests;
flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
// context-dependent signals

22
pipelined/src/uncore/uartPC16550D.sv
View File

@ -93,8 +93,8 @@ module uartPC16550D(
logic [10:0] rxfifo[15:0];
logic [7:0] txfifo[15:0];
logic [4:0] rxfifotailunwrapped;
logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel;
logic [3:0] rxfifoentries, txfifoentries;
(* mark_debug = "true" *) logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel;
(* mark_debug = "true" *) logic [3:0] rxfifoentries, txfifoentries;
logic [3:0] rxbitsexpected, txbitsexpected;
// receive data
@ -103,8 +103,8 @@ module uartPC16550D(
logic rxcentered;
logic rxparity, rxparitybit, rxstopbit;
(* mark_debug = "true" *) logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
logic rxdataready;
logic rxfifoempty, rxfifotriggered, rxfifotimeout;
(* mark_debug = "true" *) logic rxdataready;
(* mark_debug = "true" *) logic rxfifoempty, rxfifotriggered, rxfifotimeout;
logic rxfifodmaready;
logic [8:0] rxdata9;
logic [7:0] rxdata;
@ -119,13 +119,13 @@ module uartPC16550D(
logic txfifoempty, txfifofull, txfifodmaready;
// control signals
logic fifoenabled, fifodmamodesel, evenparitysel;
(* mark_debug = "true" *) logic fifoenabled, fifodmamodesel, evenparitysel;
// interrupts
logic RXerr, RXerrIP, squashRXerrIP, prevSquashRXerrIP, setSquashRXerrIP, resetSquashRXerrIP;
logic THRE, THRE_IP, squashTHRE_IP, prevSquashTHRE_IP, setSquashTHRE_IP, resetSquashTHRE_IP;
logic rxdataavailintr, modemstatusintr, intrpending;
logic [2:0] intrID;
(* mark_debug = "true" *) logic RXerr, RXerrIP, squashRXerrIP, prevSquashRXerrIP, setSquashRXerrIP, resetSquashRXerrIP;
(* mark_debug = "true" *) logic THRE, THRE_IP, squashTHRE_IP, prevSquashTHRE_IP, setSquashTHRE_IP, resetSquashTHRE_IP;
(* mark_debug = "true" *) logic rxdataavailintr, modemstatusintr, intrpending;
(* mark_debug = "true" *) logic [2:0] intrID;
logic baudpulseComb;
@ -326,8 +326,8 @@ module uartPC16550D(
rxdataready <= #1 1;
end else if (~MEMRb & A == 3'b000 & ~DLAB) begin // reading RBR updates ready / pops fifo
if (fifoenabled) begin
if (rxfifotail+1 < rxfifohead) rxfifotail <= #1 rxfifotail + 1;
if (rxfifohead == rxfifotail +1) rxdataready <= #1 0;
if (~rxfifoempty) rxfifotail <= #1 rxfifotail + 1;
if (rxfifoempty) rxdataready <= #1 0;
end else begin
rxdataready <= #1 0;
RXBR <= #1 {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)

201
pipelined/srt/qst2.c Normal file
View File

@ -0,0 +1,201 @@
/*
Program: qst2.c
Description: Prints out QST (assumes CPA is utilized to reduce memory)
User: James E. Stine
*/
#include <stdio.h>
#include <math.h>
#define DIVISOR_SIZE 3
#define CARRY_SIZE 7
#define SUM_SIZE 7
#define TOT_SIZE 7
void disp_binary(double, int, int);
struct bits {
unsigned int divisor : DIVISOR_SIZE;
int tot : TOT_SIZE;
} pla;
/*
Function: disp_binary
Description: This function displays a Double-Precision number into
four 16 bit integers using the global union variable
dp_number
Argument List: double x The value to be converted
int bits_to_left Number of bits left of radix point
int bits_to_right Number of bits right of radix point
Return value: none
*/
void disp_binary(double x, int bits_to_left, int bits_to_right) {
int i;
double diff;
if (fabs(x) < pow(2.0, ((double) -bits_to_right)) ) {
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
printf("0");
}
if (i == bits_to_right+1)
printf(" ");
return;
}
if (x < 0.0)
x = pow(2.0, ((double) bits_to_left)) + x;
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
diff = pow(2.0, ((double) -i) );
if (x < diff)
printf("0");
else {
printf("1");
x -= diff;
}
if (i == 0)
printf(" ");
}
}
int main() {
int m;
int n;
int o;
pla.divisor = 0;
pla.tot = 0;
for (o=0; o < pow(2.0, DIVISOR_SIZE); o++) {
for (m=0; m < pow(2.0, TOT_SIZE); m++) {
disp_binary((double) pla.divisor, DIVISOR_SIZE, 0);
disp_binary((double) pla.tot, TOT_SIZE, 0);
/*
4 bits for Radix 4 (a=2)
1000 = +2
0100 = +1
0000 = 0
0010 = -1
0001 = -2
*/
switch (pla.divisor) {
case 0:
if ((pla.tot) >= 12)
printf(" 1000");
else if ((pla.tot) >= 4)
printf(" 0100");
else if ((pla.tot) >= -4)
printf(" 0000");
else if ((pla.tot) >= -13)
printf(" 0010");
else
printf(" 0001");
break;
case 1:
if ((pla.tot) >= 14)
printf(" 1000");
else if ((pla.tot) >= 4)
printf(" 0100");
else if ((pla.tot) >= -6)
printf(" 0000");
else if ((pla.tot) >= -15)
printf(" 0010");
else
printf(" 0001");
break;
case 2:
if ((pla.tot) >= 15)
printf(" 1000");
else if ((pla.tot) >= 4)
printf(" 0100");
else if ((pla.tot) >= -6)
printf(" 0000");
else if ((pla.tot) >= -16)
printf(" 0010");
else
printf(" 0001");
break;
case 3:
if ((pla.tot) >= 16)
printf(" 1000");
else if ((pla.tot) >= 4)
printf(" 0100");
else if ((pla.tot) >= -6)
printf(" 0000");
else if ((pla.tot) >= -18)
printf(" 0010");
else
printf(" 0001");
break;
case 4:
if ((pla.tot) >= 18)
printf(" 1000");
else if ((pla.tot) >= 6)
printf(" 0100");
else if ((pla.tot) >= -8)
printf(" 0000");
else if ((pla.tot) >= -20)
printf(" 0010");
else
printf(" 0001");
break;
case 5:
if ((pla.tot) >= 20)
printf(" 1000");
else if ((pla.tot) >= 6)
printf(" 0100");
else if ((pla.tot) >= -8)
printf(" 0000");
else if ((pla.tot) >= -20)
printf(" 0010");
else
printf(" 0001");
break;
case 6:
if ((pla.tot) >= 20)
printf(" 1000");
else if ((pla.tot) >= 8)
printf(" 0100");
else if ((pla.tot) >= -8)
printf(" 0000");
else if ((pla.tot) >= -22)
printf(" 0010");
else
printf(" 0001");
break;
case 7:
if ((pla.tot) >= 24)
printf(" 1000");
else if ((pla.tot) >= 8)
printf(" 0100");
else if ((pla.tot) >= -8)
printf(" 0000");
else if ((pla.tot) >= -24)
printf(" 0010");
else
printf(" 0001");
break;
default:
printf (" XXX");
}
printf("\n");
(pla.tot)++;
}
(pla.divisor)++;
}
}

32
pipelined/testbench/testbench-linux.sv
View File

@ -36,7 +36,7 @@ module testbench;
parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim
parameter CHECKPOINT = 0;
parameter RISCV_DIR = "/opt/riscv";
parameter NO_IE_MTIME_CHECKPOINT = 0;
parameter NO_SPOOFING = 0;
parameter DEBUG_TRACE = 0;
// Debug Levels
// 0: don't check against QEMU
@ -93,7 +93,7 @@ module testbench;
logic [`XLEN-1:0] ExpectedRegValue``STAGE; \
logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
string ExpectedCSRArray``STAGE[10:0]; \
logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0];
logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant?
`DECLARE_TRACE_SCANNER_SIGNALS(E)
`DECLARE_TRACE_SCANNER_SIGNALS(M)
// M-stage expected values
@ -216,7 +216,7 @@ module testbench;
/////////////////////////////// Cache Issue ///////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
logic probe;
if (NO_IE_MTIME_CHECKPOINT)
if (NO_SPOOFING)
assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c
& testbench.dut.core.InstrM != 32'h14021273
& testbench.dut.core.InstrValidM;
@ -356,7 +356,7 @@ module testbench;
`INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]);
if(!NO_IE_MTIME_CHECKPOINT) begin
if(!NO_SPOOFING) begin
`INIT_CHECKPOINT_VAL(MIE, [11:0]);
`INIT_CHECKPOINT_VAL(MIP, [11:0]);
end
@ -393,7 +393,7 @@ module testbench;
// ========== INITIALIZATION ==========
initial begin
if(!NO_IE_MTIME_CHECKPOINT) begin
if(!NO_SPOOFING) begin
force `MEIP = 0;
force `SEIP = 0;
force `UART_IP = 0;
@ -403,7 +403,7 @@ module testbench;
$sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR);
if (CHECKPOINT!=0)
$sformat(checkpointDir,"%s/linux-testvectors/checkpoint%0d/",RISCV_DIR,CHECKPOINT);
$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); // *** initialize these using zeroes rather than reading from files, see testbench.sv
$readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
ProgramAddrMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.addr"};
ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"};
@ -460,7 +460,7 @@ module testbench;
release `INSTRET;
end
// Get the E-stage trace reader ahead of the M-stage trace reader
matchCountE = $fgets(lineE,traceFileE);
matchCountE = $fgets(lineE,traceFileE); // *** look at removing?
end
///////////////////////////////////////////////////////////////////////////////
@ -545,16 +545,16 @@ module testbench;
if(`"STAGE`"=="M") begin \
// override on special conditions \
if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) begin \
if(!NO_IE_MTIME_CHECKPOINT) begin \
$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, AttemptedInstructionCount); \
if(!NO_SPOOFING) begin \
$display("%tns, %d instrs: Overwrite UART's Register in memory stage.", $time, AttemptedInstructionCount); \
force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
end \
end else \
if(!NO_IE_MTIME_CHECKPOINT) \
if(!NO_SPOOFING) \
release dut.core.ieu.dp.ReadDataM; \
if(textM.substr(0,5) == "rdtime") begin \
//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
if(!NO_IE_MTIME_CHECKPOINT) \
if(!NO_SPOOFING) \
force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
end \
end \
@ -631,7 +631,7 @@ module testbench;
if(~dut.core.StallW) begin
if(textW.substr(0,5) == "rdtime") begin
//$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount);
if(!NO_IE_MTIME_CHECKPOINT)
if(!NO_SPOOFING)
release dut.uncore.clint.clint.MTIME;
end
//if (ExpectedIEUAdrM == 'h10000005) begin
@ -700,7 +700,7 @@ module testbench;
"stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW)
"mip": begin
`checkCSR(`CSR_BASE.csrm.MIP_REGW)
if(!NO_IE_MTIME_CHECKPOINT) begin
if(!NO_SPOOFING) begin
if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<11) == 0)
force `MEIP = 0;
if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<09) == 0)
@ -716,7 +716,7 @@ module testbench;
if (fault == 1) begin
errorCount +=1;
$display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount);
$stop;
$stop; $stop;
end
end // if (DEBUG_TRACE >= 1)
end // if (checkInstrW)
@ -732,7 +732,7 @@ module testbench;
always @(negedge clk) begin
if(checkInterruptM) begin
if((interruptInstrCount+1) == AttemptedInstructionCount) begin
if(!NO_IE_MTIME_CHECKPOINT) begin
if(!NO_SPOOFING) begin
case (interruptCauseVal)
11: begin
force `MEIP = 1;
@ -763,7 +763,7 @@ module testbench;
end
end
end

10
pipelined/testbench/testbench.sv
View File

@ -328,18 +328,18 @@ logic [3:0] dummy;
// initialize the branch predictor
if (`BPRED_ENABLED == 1)
initial begin
integer adrindex;
begin
genvar adrindex;
// Initializing all zeroes into the branch predictor memory.
for(adrindex = 0; adrindex < 1024; adrindex++) begin
initial begin
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
end
#1;
for(adrindex = 0; adrindex < 1024; adrindex++) begin
#1;
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
end
end
end
endmodule

142
synthDC/ppaAnalyze.py
View File

@ -1,4 +1,6 @@
#!/usr/bin/python3
# Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22
from distutils.log import error
from statistics import median
import subprocess
@ -10,16 +12,23 @@ import matplotlib.lines as lines
import numpy as np
def getData():
bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*"
def getData(mod=None, width=None):
specStr = ''
if mod != None:
specStr = mod
if width != None:
specStr += ('_'+str(width))
specStr += '*'
bashCommand = "grep 'Critical Path Length' runs/ppa_{}/reports/*qor*".format(specStr)
outputCPL = subprocess.check_output(['bash','-c', bashCommand])
linesCPL = outputCPL.decode("utf-8").split('\n')[:-1]
bashCommand = "grep 'Design Area' runs/ppa_*/reports/*qor*"
bashCommand = "grep 'Design Area' runs/ppa_{}/reports/*qor*".format(specStr)
outputDA = subprocess.check_output(['bash','-c', bashCommand])
linesDA = outputDA.decode("utf-8").split('\n')[:-1]
bashCommand = "grep '100' runs/ppa_*/reports/*power*"
bashCommand = "grep '100' runs/ppa_{}/reports/*power*".format(specStr)
outputP = subprocess.check_output(['bash','-c', bashCommand])
linesP = outputP.decode("utf-8").split('\n')[:-1]
@ -30,7 +39,6 @@ def getData():
p = re.compile('\d+\.\d+[e-]*\d+')
allSynths = []
for i in range(len(linesCPL)):
line = linesCPL[i]
mwm = wm.findall(line)[0][4:-4].split('_')
@ -42,15 +50,16 @@ def getData():
power = p.findall(linesP[i])
lpower = float(power[2])
denergy = float(power[1])/freq
denergy = float(power[1])*delay
oneSynth = [mod, width, freq, delay, area, lpower, denergy]
allSynths += [oneSynth]
return allSynths
def getVals(module, freq, var):
global allSynths
def getVals(module, var, freq=None):
allSynths = getData(mod=module)
if (var == 'delay'):
ind = 3
units = " (ns)"
@ -68,15 +77,25 @@ def getVals(module, freq, var):
widths = []
metric = []
for oneSynth in allSynths:
if (oneSynth[0] == module) & (oneSynth[2] == freq):
widths += [oneSynth[1]]
m = oneSynth[ind]
if (ind==6): m*=1000
metric += [m]
if (freq != None):
for oneSynth in allSynths:
if (oneSynth[2] == freq):
widths += [oneSynth[1]]
metric += [oneSynth[ind]]
else:
widths = [8, 16, 32, 64, 128]
for w in widths:
m = 10000 # large number to start
for oneSynth in allSynths:
if (oneSynth[1] == w):
if (oneSynth[3] < m):
m = oneSynth[3]
met = oneSynth[ind]
metric += [met]
return widths, metric, units
def writeCSV(allSynths):
def writeCSV():
allSynths = getData()
file = open("ppaData.csv", "w")
writer = csv.writer(file)
writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (mJ)'])
@ -112,7 +131,7 @@ def genLegend(fits, coefs, module, r2):
lines.Line2D([0], [0], color='steelblue', ls='', marker='o', label=' R^2='+ str(round(r2, 4)))]
return legend_elements
def plotPPA(module, freq, var, ax=None, fits='clsgn'):
def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn'):
'''
module: string module name
freq: int freq (MHz)
@ -120,7 +139,7 @@ def plotPPA(module, freq, var, ax=None, fits='clsgn'):
fits: constant, linear, square, log2, Nlog2
plots chosen variable vs width for all matching syntheses with regression
'''
widths, metric, units = getVals(module, freq, var)
widths, metric, units = getVals(module, var, freq=freq)
coefs, r2, funcArr = regress(widths, metric, fits)
xp = np.linspace(8, 140, 200)
@ -149,15 +168,6 @@ def plotPPA(module, freq, var, ax=None, fits='clsgn'):
ax.set_title(module + " (target " + str(freq) + "MHz)")
plt.show()
def makePlots(mod, freq):
fig, axs = plt.subplots(2, 2)
plotPPA(mod, freq, 'delay', ax=axs[0,0], fits='cg')
plotPPA(mod, freq, 'area', ax=axs[0,1], fits='s')
plotPPA(mod, freq, 'lpower', ax=axs[1,0], fits='c')
plotPPA(mod, freq, 'denergy', ax=axs[1,1], fits='s')
plt.suptitle(mod + " (target " + str(freq) + "MHz)")
plt.show()
def regress(widths, var, fits='clsgn'):
funcArr = genFuncs(fits)
@ -210,39 +220,58 @@ def genFuncs(fits='clsgn'):
return funcArr
def noOutliers(freqs, delays, areas):
med = statistics.median(freqs)
f=[]
d=[]
a=[]
for i in range(len(freqs)):
norm = freqs[i]/med
if (norm > 0.25) & (norm<1.75):
f += [freqs[i]]
d += [delays[i]]
a += [areas[i]]
try:
med = statistics.median(freqs)
for i in range(len(freqs)):
norm = freqs[i]/med
if (norm > 0.25) & (norm<1.75):
f += [freqs[i]]
d += [delays[i]]
a += [areas[i]]
except: pass
return f, d, a
def freqPlot(mod, width):
freqs = []
delays = []
areas = []
allSynths = getData(mod=mod, width=width)
freqsV, delaysV, areasV, freqsA, delaysA, areasA = ([] for i in range(6))
for oneSynth in allSynths:
if (mod == oneSynth[0]) & (width == oneSynth[1]):
freqs += [oneSynth[2]]
delays += [oneSynth[3]]
areas += [oneSynth[4]]
if (1000/oneSynth[3] < oneSynth[2]):
freqsV += [oneSynth[2]]
delaysV += [oneSynth[3]]
areasV += [oneSynth[4]]
else:
freqsA += [oneSynth[2]]
delaysA += [oneSynth[3]]
areasA += [oneSynth[4]]
freqs, delays, areas = noOutliers(freqs, delays, areas)
freqsV, delaysV, areasV = noOutliers(freqsV, delaysV, areasV)
freqsA, delaysA, areasA = noOutliers(freqsA, delaysA, areasA)
adprod = np.multiply(areas, delays)
adsq = np.multiply(adprod, delays)
adprodA = np.multiply(areasA, delaysA)
adsqA = np.multiply(adprodA, delaysA)
adprodV = np.multiply(areasV, delaysV)
adsqV = np.multiply(adprodV, delaysV)
legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'),
lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')]
f, (ax1, ax2, ax3, ax4) = plt.subplots(4, 1, sharex=True)
ax1.scatter(freqs, delays)
ax2.scatter(freqs, areas)
ax3.scatter(freqs, adprod)
ax4.scatter(freqs, adsq)
ax4.set_xlabel("Freq (MHz)")
ax1.scatter(freqsA, delaysA, color='green')
ax1.scatter(freqsV, delaysV, color='blue')
ax2.scatter(freqsA, areasA, color='green')
ax2.scatter(freqsV, areasV, color='blue')
ax3.scatter(freqsA, adprodA, color='green')
ax3.scatter(freqsV, adprodV, color='blue')
ax4.scatter(freqsA, adsqA, color='green')
ax4.scatter(freqsV, adsqV, color='blue')
ax1.legend(handles=legend_elements)
ax4.set_xlabel("Target Freq (MHz)")
ax1.set_ylabel('Delay (ns)')
ax2.set_ylabel('Area (sq microns)')
ax3.set_ylabel('Area * Delay')
@ -250,12 +279,19 @@ def freqPlot(mod, width):
ax1.set_title(mod + '_' + str(width))
plt.show()
allSynths = getData()
writeCSV(allSynths)
def plotPPA(mod, freq=None):
fig, axs = plt.subplots(2, 2)
oneMetricPlot(mod, 'delay', ax=axs[0,0], fits='clg', freq=freq)
oneMetricPlot(mod, 'area', ax=axs[0,1], fits='s', freq=freq)
oneMetricPlot(mod, 'lpower', ax=axs[1,0], fits='c', freq=freq)
oneMetricPlot(mod, 'denergy', ax=axs[1,1], fits='s', freq=freq)
titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " min delay"
plt.suptitle(mod + titleStr)
plt.show()
# writeCSV()
# makeCoefTable()
# freqPlot('add', 64)
freqPlot('flopr', 128)
makePlots('shifter', 5000)
# plotPPA('mult', 5000, 'delay', fits='cls')
# plotPPA('add')

1050
synthDC/ppaData.csv
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File diff suppressed because it is too large Load Diff

67
synthDC/ppaSynth.py
View File

@ -1,5 +1,8 @@
#!/usr/bin/python3
# Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22
import subprocess
import re
from multiprocessing import Pool
@ -14,27 +17,59 @@ def deleteRedundant(LoT):
bashCommand = synthStr.format(*synth)
outputCPL = subprocess.check_output(['bash','-c', bashCommand])
d = 0.26
f = 1/d * 1000
arr = [-40, -20, -8, -6, -4, -2, 0, 2, 4, 6, 8, 20, 40]
def getData():
bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*"
outputCPL = subprocess.check_output(['bash','-c', bashCommand])
linesCPL = outputCPL.decode("utf-8").split('\n')[:-1]
widths = ['128']
modules = ['comparator']
freqs = [str(round(f+f*x/100)) for x in arr]
cpl = re.compile('\d{1}\.\d{6}')
f = re.compile('_\d*_MHz')
wm = re.compile('ppa_\w*_\d*_qor')
allSynths = []
for i in range(len(linesCPL)):
line = linesCPL[i]
mwm = wm.findall(line)[0][4:-4].split('_')
freq = int(f.findall(line)[0][1:-4])
delay = float(cpl.findall(line)[0])
mod = mwm[0]
width = int(mwm[1])
oneSynth = [mod, width, freq, delay]
allSynths += [oneSynth]
return allSynths
allSynths = getData()
arr = [-40, -20, -8, -6, -4, -2, 0, 2, 4, 6, 8, 10, 14, 20, 40]
widths = [32, 64, 128]
modules = ['flopr']
tech = 'sky90'
LoT = []
for module in modules:
for width in widths:
for freq in freqs:
LoT += [[module, width, tech, freq]]
# # # initial sweep to get estimate of min delay
# freqs = ['7500']
# for module in modules:
# for width in widths:
# for freq in freqs:
# LoT += [[module, width, tech, freq]]
# thorough sweep based on estimate of min delay
for m in modules:
for w in widths:
delays = []
for oneSynth in allSynths:
if (oneSynth[0] == m) & (oneSynth[1] == w):
delays += [oneSynth[3]]
try: f = 1000/min(delays)
except: print(m)
for freq in [str(round(f+f*x/100)) for x in arr]:
LoT += [[m, w, tech, freq]]
deleteRedundant(LoT)
pool = Pool()
pool.starmap(runCommand, LoT)
pool.close()
bashCommand = "wait"
outputCPL = subprocess.check_output(['bash','-c', bashCommand])
pool.close()