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https://github.com/openhwgroup/cvw
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renamed FLoad2 to FStore2
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4
pipelined/src/cache/cache.sv
vendored
4
pipelined/src/cache/cache.sv
vendored
@ -43,7 +43,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
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input logic [`PA_BITS-1:0] PAdr, // physical address
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input logic [(`XLEN-1)/8:0] ByteMask,
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input logic [WORDLEN-1:0] FinalWriteData,
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input logic FLoad2,
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input logic FStore2,
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output logic CacheCommitted,
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output logic CacheStall,
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// to performance counters to cpu
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@ -121,7 +121,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
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// Array of cache ways, along with victim, hit, dirty, and read merging logic
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cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN)
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CacheWays[NUMWAYS-1:0](.clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteMask, .FLoad2,
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CacheWays[NUMWAYS-1:0](.clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteMask, .FStore2,
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.SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
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.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay,
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.Invalidate(InvalidateCacheM));
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4
pipelined/src/cache/cacheway.sv
vendored
4
pipelined/src/cache/cacheway.sv
vendored
@ -38,7 +38,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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input logic [$clog2(NUMLINES)-1:0] RAdr,
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input logic [`PA_BITS-1:0] PAdr,
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input logic [LINELEN-1:0] CacheWriteData,
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input logic FLoad2,
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input logic FStore2,
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input logic SetValidWay,
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input logic ClearValidWay,
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input logic SetDirtyWay,
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@ -79,7 +79,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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logic [2**LOGWPL-1:0] MemPAdrDecodedtmp;
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onehotdecoder #(LOGWPL) adrdec(
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.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecodedtmp));
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assign MemPAdrDecoded = MemPAdrDecodedtmp|{MemPAdrDecodedtmp[2**LOGWPL-2:0]&{2**LOGWPL-1{FLoad2}}, 1'b0};
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assign MemPAdrDecoded = MemPAdrDecodedtmp|{MemPAdrDecodedtmp[2**LOGWPL-2:0]&{2**LOGWPL-1{FStore2}}, 1'b0};
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end else
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onehotdecoder #(LOGWPL) adrdec(
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.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
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@ -42,7 +42,7 @@ module fpu (
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input logic [1:0] STATUS_FS, // Is floating-point enabled?
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output logic FRegWriteM, // FP register write enable
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output logic FpLoadStoreM, // Fp load instruction?
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output logic FLoad2,
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output logic FStore2,
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output logic FStallD, // Stall the decode stage
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output logic FWriteIntE, // integer register write enables
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output logic [`XLEN-1:0] FWriteDataE, // Data to be written to memory
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@ -298,8 +298,8 @@ module fpu (
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assign FWriteDataE = FSrcYE[`XLEN-1:0];
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end else begin
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logic [`FLEN-1:0] FWriteDataE;
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if(`FMTBITS == 2) assign FLoad2 = FmtM == `FMT;
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else assign FLoad2 = FmtM;
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if(`FMTBITS == 2) assign FStore2 = FmtM == `FMT;
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else assign FStore2 = FmtM;
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if (`FPSIZES==1) assign FWriteDataE = FSrcYE;
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else if (`FPSIZES==2) assign FWriteDataE = FmtE ? FSrcYE : {2{FSrcYE[`LEN1-1:0]}};
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@ -226,7 +226,7 @@ module ifu (
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icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM(TrapM), .IgnoreRequestTrapM('0),
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.CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck),
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.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
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.CacheFetchLine(ICacheFetchLine), .FLoad2(),
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.CacheFetchLine(ICacheFetchLine), .FStore2(),
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.CacheWriteLine(), .ReadDataWord(FinalInstrRawF),
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.Cacheable(CacheableF),
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.CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
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@ -58,7 +58,7 @@ module lsu (
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input logic sfencevmaM,
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// fpu
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input logic [`FLEN-1:0] FWriteDataM,
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input logic FLoad2,
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input logic FStore2,
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input logic FpLoadStoreM,
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// faults
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output logic LoadPageFaultM, StoreAmoPageFaultM,
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@ -236,14 +236,14 @@ module lsu (
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if(CACHE_ENABLED) begin : dcache
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if (`LLEN>`FLEN)
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mux2 #(`LLEN) datamux({(`LLEN-`XLEN)'(0), IEUWriteDataM}, FWriteDataM, FpLoadStoreM, FinalWriteDataM);
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mux2 #(`LLEN) datamux({{`LLEN-`XLEN{1'b0}}, IEUWriteDataM}, FWriteDataM, FpLoadStoreM, FinalWriteDataM);
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else
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assign FinalWriteDataM[`XLEN-1:0] = IEUWriteDataM;
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assign FinalWriteDataM = {{`LLEN-`XLEN{1'b0}}, IEUWriteDataM};
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cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
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.NUMWAYS(`DCACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
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.clk, .reset, .CPUBusy, .LSUBusWriteCrit, .RW(LSURWM), .Atomic(LSUAtomicM),
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.FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM),
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.ByteMask(ByteMaskM), .WordCount, .FLoad2,
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.ByteMask(ByteMaskM), .WordCount, .FStore2,
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.FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM),
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.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
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.IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM(1'b0), .CacheCommitted(DCacheCommittedM),
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@ -93,7 +93,7 @@ module wallypipelinedcore (
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logic FStallD;
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logic FWriteIntE;
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logic [`XLEN-1:0] FWriteDataE;
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logic FLoad2;
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logic FStore2;
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logic [`FLEN-1:0] FWriteDataM;
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logic [`XLEN-1:0] FIntResM;
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logic [`XLEN-1:0] FCvtIntResW;
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@ -259,7 +259,7 @@ module wallypipelinedcore (
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.CommittedM, .DCacheMiss, .DCacheAccess,
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.SquashSCW,
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.FpLoadStoreM,
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.FWriteDataM, .FLoad2,
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.FWriteDataM, .FStore2,
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//.DataMisalignedM(DataMisalignedM),
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.IEUAdrE, .IEUAdrM, .WriteDataE,
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.ReadDataW, .FlushDCacheM,
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@ -400,7 +400,7 @@ module wallypipelinedcore (
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.STATUS_FS, // is floating-point enabled?
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.FRegWriteM, // FP register write enable
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.FpLoadStoreM,
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.FLoad2,
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.FStore2,
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.FStallD, // Stall the decode stage
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.FWriteIntE, // integer register write enable
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.FWriteDataE, // Data to be written to memory
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@ -34,7 +34,7 @@
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string tvpaths[] = '{
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"../../addins/imperas-riscv-tests/work/",
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"../../tests/riscof/work/riscv-arch-test/",
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"../../tests/riscof/work/wally-riscv-arch-test/", //"../../tests/wally-riscv-arch-test/work/", //
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"../../tests/wally-riscv-arch-test/work/", //"../../tests/riscof/work/wally-riscv-arch-test/", //
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"../../tests/imperas-riscv-tests/work/",
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"../../benchmarks/coremark/work/",
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"../../addins/embench-iot/"
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