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mild cleanup.

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This commit is contained in:
Ross Thompson 2022-03-11 13:05:47 -06:00
parent 11e5aad38a
commit 81a2fbb6d2
1 changed files with 0 additions and 2 deletions
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2
pipelined/src/cache/cache.sv vendored
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@ -152,12 +152,10 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
.y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset.
else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)];
subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL, LOGWPL) subcachelineread(
.clk, .reset, .PAdr(WordOffsetAddr), .save, .restore,
.ReadDataLine, .ReadDataWord);
/////////////////////////////////////////////////////////////////////////////////////////////
// Write Path: Write data and address. Muxes between writes from bus and writes from CPU.
/////////////////////////////////////////////////////////////////////////////////////////////