Ross Thompson 02d6829f8e Found the complex TrapM giving back the wrong instruction bug. ... As I was reviewing the busfsm I found a typo. assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_READ); It should be assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_READ); There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event. Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into. The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation. IgnoreRequest is is high if there is a TrapM | ITLBMissF. Without the & ~IgnoreRequest the invalid address translation makes the request.		2022-04-11 13:07:52 -05:00
..
config	Added missing ZFH macro to new configs	2022-04-06 07:13:51 +00:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Added bootmem source ccode	2022-04-05 23:22:53 +00:00
src	Found the complex TrapM giving back the wrong instruction bug.	2022-04-11 13:07:52 -05:00
srt	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
testbench	Fixed typo in tests.vh	2022-04-07 16:28:28 -05:00