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I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.

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Ross Thompson 2022-03-25 13:10:31 -05:00
parent abf66ff85f
commit 7099259ff7
1 changed files with 1 additions and 1 deletions
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pipelined/src/privileged/csri.sv
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@ -58,7 +58,7 @@ module csri #(parameter
always_comb begin
IntInM = 0;
IntInM[11] = ExtIntM; // MEIP
IntInM[9] = ExtIntS | (ExtIntM & MIDELEG_REGW[9]); // SEIP
IntInM[9] = (ExtIntM & MIDELEG_REGW[9]); // SEIP
IntInM[7] = TimerIntM; // MTIP
IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP
IntInM[3] = SwIntM; // MSIP