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Notes on what to change in ram.sv.

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Ross Thompson 2022-03-31 15:48:15 -05:00
parent b252122d62
commit e81f317764
1 changed files with 7 additions and 0 deletions
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7
pipelined/src/uncore/ram.sv
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@ -43,6 +43,13 @@ module ram #(parameter BASE=0, RANGE = 65535) (
output logic HRESPRam, HREADYRam
);
// Desired changes.
// 1. find a way to merge read and write address into 1 port.
// 2. remove all unnecessary latencies. (HREADY needs to be able to constant high.)
// 3. implement burst.
// 4. remove the configurable latency.
localparam MemStartAddr = BASE>>(1+`XLEN/32);
localparam MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);