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Constraint changes for 40Mhz wally.

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This commit is contained in:
Ross Thompson 2022-04-04 10:50:48 -05:00
parent 0806d1a134
commit 64846c800e
3 changed files with 5 additions and 6 deletions
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2
fpga/constraints/constraints.xdc
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@ -3,7 +3,7 @@
# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
##### GPI ####
set_property PACKAGE_PIN BB24 [get_ports {GPI[0]}]

2
fpga/generator/xlnx_ddr4.tcl
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@ -41,7 +41,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {10} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {40} \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \

7
pipelined/src/uncore/sdc/SDC.sv
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@ -64,7 +64,7 @@ module SDC
// Register outputs
logic [7:0] CLKDiv;
logic signed [7:0] CLKDiv;
logic [2:0] Command;
logic [63:9] Address;
@ -331,8 +331,7 @@ module SDC
clkdivider #(8) clkdivider(.i_COUNT_IN_MAX(CLKDiv),
// .i_EN(CLKDiv != 'b1),
.i_EN('1),
.i_EN(CLKDiv <= 0), // enable if < 0 (msb is 1)
.i_CLK(CLKGate),
.i_RST(~HRESETn | CLKDivUpdateEn),
.o_CLK(SDCCLKIn));
@ -358,7 +357,7 @@ module SDC
.o_ERROR_CODE_Q(ErrorCode),
.o_FATAL_ERROR(FatalError),
.i_COUNT_IN_MAX(-8'd62),
.LIMIT_SD_TIMERS(1'b1)); // *** must change this to 0 for real hardware.
.LIMIT_SD_TIMERS(1'b0)); // *** must change this to 0 for real hardware.
endmodule