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https://github.com/openhwgroup/cvw
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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commit
7e05935348
@ -8,7 +8,7 @@ onbreak {resume}
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# create library
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vlib worklib
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vlog -lint -work worklib fma16.v testbench.v
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vlog -lint -sv -work worklib fma16.v testbench.v
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vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
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vsim -lib worklib testbenchopt
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@ -176,11 +176,7 @@ module plic (
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end
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// pending interrupt requests
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assign nextIntPending =
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(intPending | // existing pending requests
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(requests & ~intInProgress)) & // assert new requests (if they aren't already being serviced)
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~({`N{((entry == 24'h200004) & memread)}} << (intClaim[0]-1)) & // deassert requests that just completed
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~({`N{((entry == 24'h201004) & memread)}} << (intClaim[1]-1));
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assign nextIntPending = (intPending | requests) & ~intInProgress;
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flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
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// context-dependent signals
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