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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Moved order of reading a, b, and result from test vectors file so that result
matches up with inputs a and b
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parent
88060a74f5
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@ -138,9 +138,10 @@ module testbench;
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if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
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begin
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errors = errors+1;
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$display("a = %h b = %h result = %h",a,b,correctr);
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$display("result was %h, should be %h %h %h\n", result, correctr, diffn, diffp);
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$display("at fail");
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$display("failed\n");
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$display(testnum);
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$stop;
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end
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if (a === 64'hxxxxxxxxxxxxxxxx)
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@ -153,12 +154,14 @@ module testbench;
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begin
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req <= #5 0;
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correctr = nextr;
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$display("pre increment");
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testnum = testnum+1;
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a = Vec[`mema];
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b = Vec[`memb];
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Vec = Tests[testnum];
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$display("a = %h b = %h result = %h",a,b,nextr);
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a = Vec[`mema];
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b = Vec[`memb];
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nextr = Vec[`memr];
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$display("after increment");
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end
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end
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