Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-24 05:24:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Moved some muxes back into the bp.

Browse Source
This commit is contained in:
Ross Thompson 2022-02-08 14:17:44 -06:00
parent d5d9bb9d4d
commit 39149c618f
1 changed files with 9 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
pipelined/src/ifu/ifu.sv
View File

@ -243,20 +243,15 @@ module ifu (
assign PrivilegedChangePCM = RetM | TrapM;
logic SelBPPredF;
logic [`XLEN-1:0] BPPredPCF, PCNext0F;
logic BPPredWrongM;
// The true correct target is IEUAdrE if PCSrcE is 1 else it is the fall through PCLinkE.
mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE));
mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), .y(PCNext2F));
mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF));
mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F));
// Mux only required on instruction class miss prediction.
mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF),
.s(BPPredWrongM), .y(PCBPWrongInvalidate));
@ -266,18 +261,24 @@ module ifu (
// branch and jump predictor
if (`BPRED_ENABLED) begin : bpred
logic BPPredWrongM;
logic SelBPPredF;
bpred bpred(.clk, .reset,
.StallF, .StallD, .StallE, .StallM,
.FlushF, .FlushD, .FlushE, .FlushM,
.InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE,
.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);
mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
// Mux only required on instruction class miss prediction.
mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF),
.s(BPPredWrongM), .y(PCBPWrongInvalidate));
end else begin : bpred
assign BPPredWrongE = PCSrcE;
assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0;
assign SelBPPredF = 1'b0;
assign PCNext0F = PCPlus2or4F;
//assign PCNext1F = PCPlus2or4F;
//assign PCBPWrongInvalidate = PCE;
end