mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
commit
ff8e158ec4
1
.gitignore
vendored
1
.gitignore
vendored
@ -103,3 +103,4 @@ pipelined/config/rv64ic_noMulDiv
|
||||
pipelined/config/rv64ic_noPriv
|
||||
pipelined/config/rv64ic_orig
|
||||
synthDC/Summary.csv
|
||||
pipelined/srt/exptestgen
|
||||
|
@ -1 +1 @@
|
||||
Subproject commit 2d2aaa7b85c60219c591555b647dfa1785ffe1b3
|
||||
Subproject commit 261a65e0a2d3e8d62d81b1d8fe7e309a096bc6a9
|
@ -1 +1 @@
|
||||
Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f
|
||||
Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
|
@ -1 +1 @@
|
||||
Subproject commit cb4295f9ce5da2881d7746015a6105adb8f09071
|
||||
Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172
|
@ -1 +1 @@
|
||||
Subproject commit 3e2bf06b071a77ae62c09bf07c5229d1f9397d94
|
||||
Subproject commit cf04274f50621fd9ef9147793cca6dd1657985c7
|
@ -4,18 +4,18 @@ tvDir=$RISCV/linux-testvectors
|
||||
tcpPort=1239
|
||||
|
||||
# QEMU Simulation
|
||||
(qemu-system-riscv64 \
|
||||
qemu-system-riscv64 \
|
||||
-M virt -dtb $imageDir/wally-virt.dtb \
|
||||
-nographic \
|
||||
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
|
||||
-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on \
|
||||
> ./qemu-serial \
|
||||
-gdb tcp::$tcpPort -S) \
|
||||
& riscv64-unknown-elf-gdb -quiet \
|
||||
-ex "set pagination off" \
|
||||
-ex "set logging overwrite on" \
|
||||
-ex "set logging redirect on" \
|
||||
-ex "set confirm off" \
|
||||
-ex "target extended-remote :$tcpPort" \
|
||||
-ex "maintenance packet Qqemu.PhyMemMode:1" \
|
||||
-ex "file $imageDir/vmlinux"
|
||||
-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on
|
||||
# > ./qemu-serial \
|
||||
# -gdb tcp::$tcpPort -S) \
|
||||
# & riscv64-unknown-elf-gdb -quiet \
|
||||
# -ex "set pagination off" \
|
||||
# -ex "set logging overwrite on" \
|
||||
# -ex "set logging redirect on" \
|
||||
# -ex "set confirm off" \
|
||||
# -ex "target extended-remote :$tcpPort" \
|
||||
# -ex "maintenance packet Qqemu.PhyMemMode:1" \
|
||||
# -ex "file $imageDir/vmlinux"
|
||||
|
@ -38,12 +38,13 @@
|
||||
`define IEEE754 1
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
`define MISA (32'h00000104 | 1 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
|
||||
//16 - quad 3 - double 5 - single
|
||||
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define ZFH_SUPPORTED 1
|
||||
|
||||
/// Microarchitectural Features
|
||||
`define UARCH_PIPELINED 1
|
||||
|
@ -131,8 +131,8 @@
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
|
||||
`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/shared/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
|
52
pipelined/regression/fp.do
Normal file
52
pipelined/regression/fp.do
Normal file
@ -0,0 +1,52 @@
|
||||
# wally-pipelined.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
|
||||
|
||||
# Use this wally-pipelined.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-pipelined.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
# $num = the added words after the call
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv -suppress 2583,7063,8607,2697
|
||||
|
||||
vsim -voptargs=+acc work.testbenchfp -G TEST=$2
|
||||
|
||||
view wave
|
||||
#-- display input and output signals as hexidecimal values
|
||||
#do ./wave-dos/peripheral-waves.do
|
||||
#add log -recursive /*
|
||||
#do wave.do deal with when ready
|
||||
|
||||
do wave-fpu.do
|
||||
|
||||
#-- Run the Simulation
|
||||
#run 3600
|
||||
run -all
|
||||
noview testbench-fp.sv
|
||||
view wave
|
||||
|
@ -1,14 +1,16 @@
|
||||
#!/bin/bash
|
||||
|
||||
rm -r work*
|
||||
cd ../../tests/imperas-riscv-tests/
|
||||
make allclean
|
||||
make
|
||||
cd ../wally-riscv-arch-test
|
||||
make allclean
|
||||
make
|
||||
make XLEN=32
|
||||
exe2memfile.pl work/*/*/*.elf
|
||||
cd ../linux-testgen/linux-testvectors
|
||||
./tvLinker.sh
|
||||
cd ../../../pipelined/regression
|
||||
# cd ../../tests/imperas-riscv-tests/
|
||||
# make allclean
|
||||
# make
|
||||
# cd ../wally-riscv-arch-test
|
||||
# make allclean
|
||||
# make
|
||||
# make XLEN=32
|
||||
# exe2memfile.pl work/*/*/*.elf
|
||||
# cd ../linux-testgen/linux-testvectors
|
||||
# ./tvLinker.sh
|
||||
# cd ../../../pipelined/regression
|
||||
|
@ -40,7 +40,7 @@ configs = [
|
||||
TestCase(
|
||||
name="lints",
|
||||
variant="all",
|
||||
cmd="./lint-wally &> {}",
|
||||
cmd="./lint-wally | tee {}",
|
||||
grepstr="All lints run with no errors or warnings"
|
||||
)
|
||||
]
|
||||
|
11
pipelined/regression/sim-fp
Executable file
11
pipelined/regression/sim-fp
Executable file
@ -0,0 +1,11 @@
|
||||
|
||||
# cvtint - test integer conversion unit (fcvtint)
|
||||
# cvtfp - test floating-point conversion unit (fcvtfp)
|
||||
# cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
|
||||
# add - test addition
|
||||
# sub - test subtraction
|
||||
# div - test division
|
||||
# sqrt - test square ro
|
||||
# all - test everything
|
||||
|
||||
vsim -do "do fp.do rv64fp cmp"
|
10
pipelined/regression/sim-fp-batch
Executable file
10
pipelined/regression/sim-fp-batch
Executable file
@ -0,0 +1,10 @@
|
||||
# cvtint - test integer conversion unit (fcvtint)
|
||||
# cvtfp - test floating-point conversion unit (fcvtfp)
|
||||
# cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
|
||||
# add - test addition
|
||||
# sub - test subtraction
|
||||
# div - test division
|
||||
# sqrt - test square root
|
||||
# all - test everything
|
||||
|
||||
vsim -c -do "do fp.do rv64fp fma"
|
@ -1,2 +1,2 @@
|
||||
vsim -do "do wally-pipelined.do rv32e wally32e"
|
||||
vsim -do "do wally-pipelined.do rv64gc imperas64f"
|
||||
|
||||
|
@ -1 +1 @@
|
||||
vsim -c -do "do wally-pipelined-batch.do rv32e wally32e"
|
||||
vsim -c -do "do wally-pipelined-batch.do rv64gc imperas64f"
|
||||
|
@ -8,7 +8,7 @@ if not os.path.isfile(sys.path[0]+'/slack-webhook-url.txt'):
|
||||
print('slack-notifier.py can help let you know when your sim is done.')
|
||||
print('To make it work, please supply your Slack bot webhook URL in:')
|
||||
print(sys.path[0]+'/slack-webhook-url.txt')
|
||||
print('Ask Ben for the Tera Slack Notifier Tutorial for more details.')
|
||||
print('Tutorial for slack webhook urls: https://bit.ly/BenSlackNotifier')
|
||||
print('==============================================================')
|
||||
else:
|
||||
urlFile = open(sys.path[0]+'/slack-webhook-url.txt','r')
|
||||
|
@ -35,7 +35,7 @@ vlib wkdir/work_${1}_${2}
|
||||
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt
|
||||
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G DEBUG_TRACE=1 -o testbenchopt
|
||||
vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084
|
||||
|
||||
run -all
|
||||
|
@ -34,7 +34,7 @@ vlib work
|
||||
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G DEBUG_TRACE=1 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
|
||||
|
||||
#-- Run the Simulation
|
||||
@ -48,7 +48,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
} elseif {$2 eq "buildroot-no-trace"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -o testbenchopt
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -G DEBUG_TRACE=0 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
|
||||
|
||||
#-- Run the Simulation
|
||||
|
102
pipelined/regression/wave-fpu.do
Normal file
102
pipelined/regression/wave-fpu.do
Normal file
@ -0,0 +1,102 @@
|
||||
|
||||
add wave -noupdate /testbenchfp/clk
|
||||
add wave -noupdate -radix decimal /testbenchfp/VectorNum
|
||||
add wave -group Other -noupdate /testbenchfp/FrmNum
|
||||
add wave -group Other -noupdate /testbenchfp/X
|
||||
add wave -group Other -noupdate /testbenchfp/Y
|
||||
add wave -group Other -noupdate /testbenchfp/Z
|
||||
add wave -group Other -noupdate /testbenchfp/Res
|
||||
add wave -group Other -noupdate /testbenchfp/Ans
|
||||
|
||||
add wave -group Rne -noupdate /testbenchfp/FmaRneX
|
||||
add wave -group Rne -noupdate /testbenchfp/FmaRneY
|
||||
add wave -group Rne -noupdate /testbenchfp/FmaRneZ
|
||||
add wave -group Rne -noupdate /testbenchfp/FmaRneRes
|
||||
add wave -group Rne -noupdate /testbenchfp/FmaRneAns
|
||||
add wave -group Rz -noupdate /testbenchfp/FmaRzX
|
||||
add wave -group Rz -noupdate /testbenchfp/FmaRzY
|
||||
add wave -group Rz -noupdate /testbenchfp/FmaRzZ
|
||||
add wave -group Rz -noupdate /testbenchfp/FmaRzRes
|
||||
add wave -group Rz -noupdate /testbenchfp/FmaRzAns
|
||||
add wave -group Ru -noupdate /testbenchfp/FmaRuX
|
||||
add wave -group Ru -noupdate /testbenchfp/FmaRuY
|
||||
add wave -group Ru -noupdate /testbenchfp/FmaRuZ
|
||||
add wave -group Ru -noupdate /testbenchfp/FmaRuRes
|
||||
add wave -group Ru -noupdate /testbenchfp/FmaRuAns
|
||||
add wave -group Rd -noupdate /testbenchfp/FmaRdX
|
||||
add wave -group Rd -noupdate /testbenchfp/FmaRdY
|
||||
add wave -group Rd -noupdate /testbenchfp/FmaRdZ
|
||||
add wave -group Rd -noupdate /testbenchfp/FmaRdRes
|
||||
add wave -group Rd -noupdate /testbenchfp/FmaRdAns
|
||||
add wave -group Rnm -noupdate /testbenchfp/FmaRnmX
|
||||
add wave -group Rnm -noupdate /testbenchfp/FmaRnmY
|
||||
add wave -group Rnm -noupdate /testbenchfp/FmaRnmZ
|
||||
add wave -group Rnm -noupdate /testbenchfp/FmaRnmRes
|
||||
add wave -group Rnm -noupdate /testbenchfp/FmaRnmAns
|
||||
add wave -group AllSignals -noupdate /*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rne/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rne/expadd/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rne/mult/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rne/align/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rne/sign/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rne/add/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rne/loa/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rne/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rne/normalize/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rne/fmaround/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rne/resultsign/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rne/fmaflags/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rne/resultselect/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rz/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rz/expadd/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rz/mult/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rz/align/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rz/sign/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rz/add/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rz/loa/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rz/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rz/normalize/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rz/fmaround/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rz/resultsign/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rz/fmaflags/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rz/resultselect/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1ru/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1ru/expadd/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1ru/mult/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1ru/align/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1ru/sign/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1ru/add/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1ru/loa/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2ru/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2ru/normalize/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2ru/fmaround/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2ru/resultsign/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2ru/fmaflags/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2ru/resultselect/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rd/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rd/expadd/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rd/mult/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rd/align/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rd/sign/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rd/add/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rd/loa/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rd/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rd/normalize/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rd/fmaround/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rd/resultsign/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rd/fmaflags/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rd/resultselect/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/expadd/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/mult/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/align/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/sign/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/add/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/loa/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/normalize/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/fmaround/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/resultsign/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/fmaflags/*
|
||||
add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/resultselect/*
|
4
pipelined/regression/wkdir/.gitignore
vendored
Normal file
4
pipelined/regression/wkdir/.gitignore
vendored
Normal file
@ -0,0 +1,4 @@
|
||||
# Ignore everything in this directory
|
||||
*
|
||||
# Except this file
|
||||
!.gitignore
|
@ -123,6 +123,19 @@ module ahblite (
|
||||
assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
|
||||
assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize;
|
||||
assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH
|
||||
|
||||
/* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE.
|
||||
000: Single (SINGLE)
|
||||
001: Increment burst of undefined length (INCR)
|
||||
010: 4-beat wrapping burst (WRAP4) [wraps if X in 000X0000]
|
||||
011: 4-beat incrementing burst (INCR4)
|
||||
100: 8-beat wrapping burst (WRAP8) [wraps if X in 00X00000 changes]
|
||||
101: 8-beat incrementing burst (INCR8)
|
||||
110: 16-beat wrapping burst (WRAP16) [wraps if X in 0X000000]
|
||||
111: 16-beat incrementing burst (INCR16)
|
||||
*/
|
||||
|
||||
|
||||
assign HPROT = 4'b0011; // not used; see Section 3.7
|
||||
assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
|
||||
assign HMASTLOCK = 0; // no locking supported
|
||||
|
@ -10,20 +10,21 @@
|
||||
|
||||
|
||||
module fcmp (
|
||||
input logic FmtE, // precision 1 = double 0 = single
|
||||
input logic [2:0] FOpCtrlE, // see above table
|
||||
input logic XSgnE, YSgnE, // input signs
|
||||
input logic [`NE-1:0] XExpE, YExpE, // input exponents
|
||||
input logic [`NF:0] XManE, YManE, // input mantissa
|
||||
input logic XZeroE, YZeroE, // is zero
|
||||
input logic XNaNE, YNaNE, // is NaN
|
||||
input logic XSNaNE, YSNaNE, // is signaling NaN
|
||||
input logic [`FLEN-1:0] FSrcXE, FSrcYE, // original, non-converted to double, inputs
|
||||
output logic CmpNVE, // invalid flag
|
||||
output logic [`FLEN-1:0] CmpResE // compare resilt
|
||||
input logic [`FPSIZES/3:0] FmtE, // precision 1 = double 0 = single
|
||||
input logic [2:0] FOpCtrlE, // see above table
|
||||
input logic XSgnE, YSgnE, // input signs
|
||||
input logic [`NE-1:0] XExpE, YExpE, // input exponents
|
||||
input logic [`NF:0] XManE, YManE, // input mantissa
|
||||
input logic XZeroE, YZeroE, // is zero
|
||||
input logic XNaNE, YNaNE, // is NaN
|
||||
input logic XSNaNE, YSNaNE, // is signaling NaN
|
||||
input logic [`FLEN-1:0] FSrcXE, FSrcYE, // original, non-converted to double, inputs
|
||||
output logic CmpNVE, // invalid flag
|
||||
output logic [`FLEN-1:0] CmpResE // compare resilt
|
||||
);
|
||||
|
||||
logic LTabs, LT, EQ; // is X < or > or = Y
|
||||
logic [`FLEN-1:0] NaNRes;
|
||||
logic BothZeroE, EitherNaNE, EitherSNaNE;
|
||||
|
||||
assign LTabs= {1'b0, XExpE, XManE} < {1'b0, YExpE, YManE}; // unsigned comparison, treating FP as integers
|
||||
@ -65,26 +66,62 @@ module fcmp (
|
||||
// - inf = inf and -inf = -inf
|
||||
// - return 0 if comparison with NaN (unordered)
|
||||
|
||||
logic [`FLEN-1:0] QNaN;
|
||||
// fmin/fmax of two NaNs returns a quiet NaN of the appropriate size
|
||||
// for IEEE, return the payload of X
|
||||
// for RISC-V, return the canonical NaN
|
||||
if(`IEEE754) assign QNaN = FmtE ? {XSgnE, XExpE, 1'b1, XManE[`NF-2:0]} : {{32{1'b1}}, XSgnE, XExpE[7:0], 1'b1, XManE[50:29]};
|
||||
else assign QNaN = FmtE ? {1'b0, XExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpE[7:0], 1'b1, 22'b0};
|
||||
|
||||
// when one input is a NaN -output the non-NaN
|
||||
always_comb begin
|
||||
case (FOpCtrlE[2:0])
|
||||
3'b111: CmpResE = XNaNE ? YNaNE ? QNaN : FSrcYE // Min
|
||||
: YNaNE ? FSrcXE : LT ? FSrcXE : FSrcYE;
|
||||
3'b101: CmpResE = XNaNE ? YNaNE ? QNaN : FSrcYE // Max
|
||||
: YNaNE ? FSrcXE : LT ? FSrcYE : FSrcXE;
|
||||
3'b010: CmpResE = {63'b0, (EQ|BothZeroE) & ~EitherNaNE}; // Equal
|
||||
3'b001: CmpResE = {63'b0, LT & ~BothZeroE & ~EitherNaNE}; // Less than
|
||||
3'b011: CmpResE = {63'b0, (LT|EQ|BothZeroE) & ~EitherNaNE}; // Less than or equal
|
||||
default: CmpResE = 64'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
if (`FPSIZES == 1)
|
||||
if(`IEEE754) assign NaNRes = {XSgnE, {`NE{1'b1}}, 1'b1, XManE[`NF-2:0]};
|
||||
else assign NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
|
||||
else if (`FPSIZES == 2)
|
||||
if(`IEEE754) assign NaNRes = FmtE ? {XSgnE, {`NE{1'b1}}, 1'b1, XManE[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, XSgnE, {`NE1{1'b1}}, 1'b1, XManE[`NF-2:`NF-`NF1]};
|
||||
else assign NaNRes = FmtE ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
|
||||
|
||||
else if (`FPSIZES == 3)
|
||||
always_comb
|
||||
case (FmtE)
|
||||
`FMT:
|
||||
if(`IEEE754) NaNRes = {XSgnE, {`NE{1'b1}}, 1'b1, XManE[`NF-2:0]};
|
||||
else NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
`FMT1:
|
||||
if(`IEEE754) NaNRes = {{`FLEN-`LEN1{1'b1}}, XSgnE, {`NE1{1'b1}}, 1'b1, XManE[`NF-2:`NF-`NF1]};
|
||||
else NaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
|
||||
`FMT2:
|
||||
if(`IEEE754) NaNRes = {{`FLEN-`LEN2{1'b1}}, XSgnE, {`NE2{1'b1}}, 1'b1, XManE[`NF-2:`NF-`NF2]};
|
||||
else NaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
|
||||
default: NaNRes = (`FLEN)'(0);
|
||||
endcase
|
||||
|
||||
else if (`FPSIZES == 4)
|
||||
always_comb
|
||||
case (FmtE)
|
||||
2'h3:
|
||||
if(`IEEE754) NaNRes = {XSgnE, {`NE{1'b1}}, 1'b1, XManE[`NF-2:0]};
|
||||
else NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
2'h1:
|
||||
if(`IEEE754) NaNRes = {{`FLEN-`D_LEN{1'b1}}, XSgnE, {`D_NE{1'b1}}, 1'b1, XManE[`NF-2:`NF-`D_NF]};
|
||||
else NaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
|
||||
2'h0:
|
||||
if(`IEEE754) NaNRes = {{`FLEN-`S_LEN{1'b1}}, XSgnE, {`S_NE{1'b1}}, 1'b1, XManE[`NF-2:`NF-`S_NF]};
|
||||
else NaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
|
||||
2'h2:
|
||||
if(`IEEE754) NaNRes = {{`FLEN-`H_LEN{1'b1}}, XSgnE, {`H_NE{1'b1}}, 1'b1, XManE[`NF-2:`NF-`H_NF]};
|
||||
else NaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)};
|
||||
endcase
|
||||
|
||||
// when one input is a NaN -output the non-NaN
|
||||
always_comb
|
||||
case (FOpCtrlE[2:0])
|
||||
3'b111: CmpResE = XNaNE ? YNaNE ? NaNRes : FSrcYE // Min
|
||||
: YNaNE ? FSrcXE : LT ? FSrcXE : FSrcYE;
|
||||
3'b101: CmpResE = XNaNE ? YNaNE ? NaNRes : FSrcYE // Max
|
||||
: YNaNE ? FSrcXE : LT ? FSrcYE : FSrcXE;
|
||||
3'b010: CmpResE = {(`FLEN-1)'(0), (EQ|BothZeroE) & ~EitherNaNE}; // Equal
|
||||
3'b001: CmpResE = {(`FLEN-1)'(0), LT & ~BothZeroE & ~EitherNaNE}; // Less than
|
||||
3'b011: CmpResE = {(`FLEN-1)'(0), (LT|EQ|BothZeroE) & ~EitherNaNE}; // Less than or equal
|
||||
default: CmpResE = (`FLEN)'(0);
|
||||
endcase
|
||||
|
||||
endmodule
|
||||
|
@ -1,6 +1,6 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
module cvtfp (
|
||||
module fcvtfp (
|
||||
input logic [10:0] XExpE, // input's exponent
|
||||
input logic [52:0] XManE, // input's mantissa
|
||||
input logic XSgnE, // input's sign
|
||||
|
@ -2,7 +2,7 @@
|
||||
`include "wally-config.vh"
|
||||
// `include "../../config/rv64icfd/wally-config.vh"
|
||||
// `define XLEN 64
|
||||
module fcvt (
|
||||
module fcvtint (
|
||||
input logic XSgnE, // X's sign
|
||||
input logic [10:0] XExpE, // X's exponent
|
||||
input logic [52:0] XManE, // X's fraction
|
||||
|
@ -43,6 +43,7 @@ module fma(
|
||||
input logic XSgnM, YSgnM, // input signs - memory stage
|
||||
input logic [`NE-1:0] ZExpM, // input exponents - memory stage
|
||||
input logic [`NF:0] XManM, YManM, ZManM, // input mantissa - memory stage
|
||||
input logic ZOrigDenormE, // is the original precision denormalized
|
||||
input logic XDenormE, YDenormE, ZDenormE, // is denorm
|
||||
input logic XZeroE, YZeroE, ZZeroE, // is zero - execute stage
|
||||
input logic XNaNM, YNaNM, ZNaNM, // is NaN
|
||||
@ -72,6 +73,7 @@ module fma(
|
||||
logic PSgnE, PSgnM;
|
||||
logic [$clog2(3*`NF+7)-1:0] NormCntE, NormCntM;
|
||||
logic Mult;
|
||||
logic ZOrigDenormM;
|
||||
|
||||
fma1 fma1 (.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
|
||||
.XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE,
|
||||
@ -81,11 +83,11 @@ module fma(
|
||||
// E/M pipeline registers
|
||||
flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SumE, SumM);
|
||||
flopenrc #(13) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM);
|
||||
flopenrc #($clog2(3*`NF+7)+7) EMRegFma4(clk, reset, FlushM, ~StallM,
|
||||
{AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE, FOpCtrlE[2]&~FOpCtrlE[1]&~FOpCtrlE[0]},
|
||||
{AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM, Mult});
|
||||
flopenrc #($clog2(3*`NF+7)+8) EMRegFma4(clk, reset, FlushM, ~StallM,
|
||||
{AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE, FOpCtrlE[2]&~FOpCtrlE[1]&~FOpCtrlE[0], ZOrigDenormE},
|
||||
{AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM, Mult, ZOrigDenormM});
|
||||
|
||||
fma2 fma2(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM,
|
||||
fma2 fma2(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .ZOrigDenormM,
|
||||
.FrmM, .FmtM, .ProdExpM, .AddendStickyM, .KillProdM, .SumM, .NegSumM, .InvZM, .NormCntM, .ZSgnEffM, .PSgnM,
|
||||
.XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .XSNaNM, .YSNaNM, .ZSNaNM, .Mult,
|
||||
.FMAResM, .FMAFlgM);
|
||||
@ -448,6 +450,7 @@ module fma2(
|
||||
input logic [3*`NF+5:0] SumM, // the positive sum
|
||||
input logic NegSumM, // was the sum negitive
|
||||
input logic InvZM, // do you invert Z
|
||||
input logic ZOrigDenormM, // is the original precision denormalized
|
||||
input logic ZSgnEffM, // the modified Z sign - depends on instruction
|
||||
input logic PSgnM, // the product's sign
|
||||
input logic Mult, // multiply opperation
|
||||
@ -483,7 +486,7 @@ module fma2(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum,
|
||||
.SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm);
|
||||
.ZOrigDenormM, .SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm);
|
||||
|
||||
|
||||
|
||||
@ -530,7 +533,7 @@ module fma2(
|
||||
// Select the result
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
resultselect resultselect(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM,
|
||||
resultselect resultselect(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .ZOrigDenormM,
|
||||
.FrmM, .FmtM, .AddendStickyM, .KillProdM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .RoundAdd,
|
||||
.ZSgnEffM, .PSgnM, .ResultSgn, .CalcPlus1, .Invalid, .Overflow, .Underflow,
|
||||
.ResultDenorm, .ResultExp, .ResultFrac, .FMAResM);
|
||||
@ -577,6 +580,7 @@ module normalize(
|
||||
input logic [$clog2(3*`NF+7)-1:0] NormCntM, // normalization shift count
|
||||
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single
|
||||
input logic KillProdM, // is the product set to zero
|
||||
input logic ZOrigDenormM,
|
||||
input logic AddendStickyM, // the sticky bit caclulated from the aligned addend
|
||||
output logic [`NF+2:0] NormSum, // normalized sum
|
||||
output logic SumZero, // is the sum zero
|
||||
@ -600,7 +604,7 @@ module normalize(
|
||||
assign SumZero = ~(|SumM);
|
||||
|
||||
// calculate the sum's exponent
|
||||
assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4));
|
||||
assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM[`NE-1:1], ZExpM[0]&~ZOrigDenormM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4));
|
||||
|
||||
//convert the sum's exponent into the propper percision
|
||||
if (`FPSIZES == 1) begin
|
||||
@ -1080,6 +1084,7 @@ module fmaflags(
|
||||
// - Don't set the underflow flag if the result is exact
|
||||
|
||||
assign Underflow = (SumExp[`NE+1] | ((SumExp == 0) & (Round|Guard|Sticky)))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
|
||||
// exp is negitive result is denorm exp was denorm but rounded to norm and if given an unbounded exponent it would stay denormal
|
||||
assign UnderflowFlag = (FullResultExp[`NE+1] | ((FullResultExp == 0) | ((FullResultExp == 1) & (SumExp == 0) & ~(UfPlus1&UfLSBNormSum)))&(Round|Guard|Sticky))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
|
||||
// Set Inexact flag if the result is diffrent from what would be outputed given infinite precision
|
||||
// - Don't set the underflow flag if an underflowed result isn't outputed
|
||||
@ -1103,6 +1108,7 @@ module resultselect(
|
||||
input logic KillProdM, // set the product to zero before addition if the product is too small to matter
|
||||
input logic XInfM, YInfM, ZInfM, // inputs are infinity
|
||||
input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN
|
||||
input logic ZOrigDenormM, // is the original precision denormalized
|
||||
input logic ZSgnEffM, // the modified Z sign - depends on instruction
|
||||
input logic PSgnM, // the product's sign
|
||||
input logic ResultSgn, // the result's sign
|
||||
@ -1122,7 +1128,7 @@ module resultselect(
|
||||
assign XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]};
|
||||
assign YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]};
|
||||
assign ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]};
|
||||
assign InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
assign InvalidResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
end else begin
|
||||
assign XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
end
|
||||
@ -1138,7 +1144,7 @@ module resultselect(
|
||||
assign XNaNResult = FmtM ? {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, XSgnM, {`NE1{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF1]};
|
||||
assign YNaNResult = FmtM ? {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, YSgnM, {`NE1{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF1]};
|
||||
assign ZNaNResult = FmtM ? {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, ZSgnEffM, {`NE1{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF1]};
|
||||
assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
|
||||
assign InvalidResult = FmtM ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
|
||||
end else begin
|
||||
assign XNaNResult = FmtM ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
|
||||
end
|
||||
@ -1147,7 +1153,7 @@ module resultselect(
|
||||
{ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} :
|
||||
((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} :
|
||||
{{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, (`NF1)'(0)};
|
||||
assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:0], ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})};
|
||||
assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})};
|
||||
assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))} : {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}};
|
||||
assign InfResult = FmtM ? {InfSgn, {`NE{1'b1}}, (`NF)'(0)} : {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)};
|
||||
assign NormResult = FmtM ? {ResultSgn, ResultExp, ResultFrac} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]};
|
||||
@ -1160,7 +1166,7 @@ module resultselect(
|
||||
XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]};
|
||||
YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]};
|
||||
ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]};
|
||||
InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
InvalidResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
end else begin
|
||||
XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
end
|
||||
@ -1177,13 +1183,13 @@ module resultselect(
|
||||
XNaNResult = {{`FLEN-`LEN1{1'b1}}, XSgnM, {`NE1{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF1]};
|
||||
YNaNResult = {{`FLEN-`LEN1{1'b1}}, YSgnM, {`NE1{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF1]};
|
||||
ZNaNResult = {{`FLEN-`LEN1{1'b1}}, ZSgnEffM, {`NE1{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF1]};
|
||||
InvalidResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
|
||||
InvalidResult = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
|
||||
end else begin
|
||||
XNaNResult = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
|
||||
end
|
||||
OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} :
|
||||
{{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, (`NF1)'(0)};
|
||||
KillProdResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:0], ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})};
|
||||
KillProdResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})};
|
||||
UnderflowResult = {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}};
|
||||
InfResult = {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)};
|
||||
NormResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]};
|
||||
@ -1193,14 +1199,14 @@ module resultselect(
|
||||
XNaNResult = {{`FLEN-`LEN2{1'b1}}, XSgnM, {`NE2{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF2]};
|
||||
YNaNResult = {{`FLEN-`LEN2{1'b1}}, YSgnM, {`NE2{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF2]};
|
||||
ZNaNResult = {{`FLEN-`LEN2{1'b1}}, ZSgnEffM, {`NE2{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF2]};
|
||||
InvalidResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
|
||||
InvalidResult = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
|
||||
end else begin
|
||||
XNaNResult = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
|
||||
end
|
||||
|
||||
OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2-1{1'b1}}, 1'b0, {`NF2{1'b1}}} :
|
||||
{{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, (`NF2)'(0)};
|
||||
KillProdResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`NF2]} + (RoundAdd[`NF-`NF2+`LEN2-2:`NF-`NF2]&{`LEN2-1{AddendStickyM}})};
|
||||
KillProdResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`NF2]} + (RoundAdd[`NF-`NF2+`LEN2-2:`NF-`NF2]&{`LEN2-1{AddendStickyM}})};
|
||||
UnderflowResult = {{`FLEN-`LEN2{1'b1}}, {ResultSgn, (`LEN2-1)'(0)} + {(`LEN2-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}};
|
||||
InfResult = {{`FLEN-`LEN2{1'b1}}, InfSgn, {`NE2{1'b1}}, (`NF2)'(0)};
|
||||
NormResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, ResultExp[`NE2-1:0], ResultFrac[`NF-1:`NF-`NF2]};
|
||||
@ -1231,7 +1237,7 @@ module resultselect(
|
||||
XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]};
|
||||
YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]};
|
||||
ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]};
|
||||
InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
InvalidResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
end else begin
|
||||
XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
end
|
||||
@ -1248,13 +1254,13 @@ module resultselect(
|
||||
XNaNResult = {{`FLEN-`D_LEN{1'b1}}, XSgnM, {`D_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`D_NF]};
|
||||
YNaNResult = {{`FLEN-`D_LEN{1'b1}}, YSgnM, {`D_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`D_NF]};
|
||||
ZNaNResult = {{`FLEN-`D_LEN{1'b1}}, ZSgnEffM, {`D_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`D_NF]};
|
||||
InvalidResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
|
||||
InvalidResult = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
|
||||
end else begin
|
||||
XNaNResult = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
|
||||
end
|
||||
OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE-1{1'b1}}, 1'b0, {`D_NF{1'b1}}} :
|
||||
{{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, (`D_NF)'(0)};
|
||||
KillProdResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`D_NE-2:0], ZManM[`NF-1:`NF-`D_NF]} + (RoundAdd[`NF-`D_NF+`D_LEN-2:`NF-`D_NF]&{`D_LEN-1{AddendStickyM}})};
|
||||
KillProdResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`D_NE-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`D_NF]} + (RoundAdd[`NF-`D_NF+`D_LEN-2:`NF-`D_NF]&{`D_LEN-1{AddendStickyM}})};
|
||||
UnderflowResult = {{`FLEN-`D_LEN{1'b1}}, {ResultSgn, (`D_LEN-1)'(0)} + {(`D_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}};
|
||||
InfResult = {{`FLEN-`D_LEN{1'b1}}, InfSgn, {`D_NE{1'b1}}, (`D_NF)'(0)};
|
||||
NormResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, ResultExp[`D_NE-1:0], ResultFrac[`NF-1:`NF-`D_NF]};
|
||||
@ -1264,14 +1270,14 @@ module resultselect(
|
||||
XNaNResult = {{`FLEN-`S_LEN{1'b1}}, XSgnM, {`S_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`S_NF]};
|
||||
YNaNResult = {{`FLEN-`S_LEN{1'b1}}, YSgnM, {`S_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`S_NF]};
|
||||
ZNaNResult = {{`FLEN-`S_LEN{1'b1}}, ZSgnEffM, {`S_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`S_NF]};
|
||||
InvalidResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
|
||||
InvalidResult = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
|
||||
end else begin
|
||||
XNaNResult = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
|
||||
end
|
||||
|
||||
OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE-1{1'b1}}, 1'b0, {`S_NF{1'b1}}} :
|
||||
{{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, (`S_NF)'(0)};
|
||||
KillProdResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`S_NF]} + (RoundAdd[`NF-`S_NF+`S_LEN-2:`NF-`S_NF]&{`S_LEN-1{AddendStickyM}})};
|
||||
KillProdResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`S_NE-2:1], ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`S_NF]} + (RoundAdd[`NF-`S_NF+`S_LEN-2:`NF-`S_NF]&{`S_LEN-1{AddendStickyM}})};
|
||||
UnderflowResult = {{`FLEN-`S_LEN{1'b1}}, {ResultSgn, (`S_LEN-1)'(0)} + {(`S_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}};
|
||||
InfResult = {{`FLEN-`S_LEN{1'b1}}, InfSgn, {`S_NE{1'b1}}, (`S_NF)'(0)};
|
||||
NormResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, ResultExp[`S_NE-1:0], ResultFrac[`NF-1:`NF-`S_NF]};
|
||||
@ -1289,7 +1295,7 @@ module resultselect(
|
||||
OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} :
|
||||
{{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE{1'b1}}, (`H_NF)'(0)};
|
||||
|
||||
KillProdResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`H_NE-2:0], ZManM[`NF-1:`NF-`H_NF]} + (RoundAdd[`NF-`H_NF+`H_LEN-2:`NF-`H_NF]&{`H_LEN-1{AddendStickyM}})};
|
||||
KillProdResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`H_NE-2:1],ZExpM[0]&~ZOrigDenormM, ZManM[`NF-1:`NF-`H_NF]} + (RoundAdd[`NF-`H_NF+`H_LEN-2:`NF-`H_NF]&{`H_LEN-1{AddendStickyM}})};
|
||||
UnderflowResult = {{`FLEN-`H_LEN{1'b1}}, {ResultSgn, (`H_LEN-1)'(0)} + {(`H_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}};
|
||||
InfResult = {{`FLEN-`H_LEN{1'b1}}, InfSgn, {`H_NE{1'b1}}, (`H_NF)'(0)};
|
||||
NormResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, ResultExp[`H_NE-1:0], ResultFrac[`NF-1:`NF-`H_NF]};
|
||||
|
@ -104,6 +104,7 @@ module fpu (
|
||||
logic XInfQ, YInfQ; // is the input infinity - divide
|
||||
logic XExpMaxE; // is the exponent all ones (max value)
|
||||
logic XNormE; // is normal
|
||||
logic ZOrigDenormE;
|
||||
logic FmtQ;
|
||||
logic FOpCtrlQ;
|
||||
|
||||
@ -176,7 +177,7 @@ module fpu (
|
||||
// unpack unit
|
||||
// - splits FP inputs into their various parts
|
||||
// - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity)
|
||||
unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FmtE,
|
||||
unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FmtE, .ZOrigDenormE,
|
||||
.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
|
||||
.XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE,
|
||||
.XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
|
||||
@ -192,7 +193,7 @@ module fpu (
|
||||
.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM,
|
||||
.XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM,
|
||||
.XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM,
|
||||
.FOpCtrlE,
|
||||
.FOpCtrlE, .ZOrigDenormE,
|
||||
.FmtE, .FmtM, .FrmM,
|
||||
.FMAFlgM, .FMAResM);
|
||||
|
||||
@ -213,12 +214,12 @@ module fpu (
|
||||
.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
|
||||
|
||||
// other FP execution units
|
||||
cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);
|
||||
fcvtfp fcvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);
|
||||
fcmp fcmp (.FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .XExpE, .YExpE, .XManE, .YManE,
|
||||
.XZeroE, .YZeroE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, .FSrcXE, .FSrcYE, .CmpNVE, .CmpResE);
|
||||
fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .SgnResE);
|
||||
fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE);
|
||||
fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE,
|
||||
fcvtint fcvtint (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE,
|
||||
.CvtResE, .CvtFlgE);
|
||||
|
||||
// data to be stored in memory - to IEU
|
||||
|
@ -2,7 +2,7 @@
|
||||
|
||||
module unpack (
|
||||
input logic [`FLEN-1:0] X, Y, Z, // inputs from register file
|
||||
input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 10 - double 11 - quad 10 - half
|
||||
input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half
|
||||
output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ
|
||||
output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision)
|
||||
output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision)
|
||||
@ -12,6 +12,7 @@ module unpack (
|
||||
output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized
|
||||
output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero
|
||||
output logic XInfE, YInfE, ZInfE, // is XYZ infinity
|
||||
output logic ZOrigDenormE, // is the original precision denormalized
|
||||
output logic XExpMaxE // does X have the maximum exponent (NaN or Inf)
|
||||
);
|
||||
|
||||
@ -47,10 +48,11 @@ module unpack (
|
||||
assign XExpMaxE = &XExpE;
|
||||
assign YExpMaxE = &YExpE;
|
||||
assign ZExpMaxE = &ZExpE;
|
||||
|
||||
assign ZOrigDenormE = 1'b0;
|
||||
|
||||
|
||||
end else if (`FPSIZES == 2) begin // if there are 2 floating point formats supported
|
||||
|
||||
//***need better names for these constants
|
||||
// largest format | smaller format
|
||||
//----------------------------------
|
||||
@ -70,7 +72,8 @@ module unpack (
|
||||
// quad and half
|
||||
// double and half
|
||||
|
||||
logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed
|
||||
logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed
|
||||
logic XOrigDenormE, YOrigDenormE; // the original value of XYZ is denormalized
|
||||
|
||||
// Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN
|
||||
assign XLen1 = &X[`FLEN-1:`LEN1] ? X[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)};
|
||||
@ -91,9 +94,15 @@ module unpack (
|
||||
// also need to take into account possible zero/denorm/inf/NaN values
|
||||
|
||||
// extract the exponent, converting the smaller exponent into the larger precision if nessisary
|
||||
assign XExpE = FmtE ? X[`FLEN-2:`NF] : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]};
|
||||
assign YExpE = FmtE ? Y[`FLEN-2:`NF] : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]};
|
||||
assign ZExpE = FmtE ? Z[`FLEN-2:`NF] : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]};
|
||||
// - if the original precision had a denormal number convert the exponent value 1
|
||||
assign XExpE = FmtE ? X[`FLEN-2:`NF] : XOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]};
|
||||
assign YExpE = FmtE ? Y[`FLEN-2:`NF] : YOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]};
|
||||
assign ZExpE = FmtE ? Z[`FLEN-2:`NF] : ZOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]};
|
||||
|
||||
// is the input (in it's original format) denormalized
|
||||
assign XOrigDenormE = FmtE ? 0 : ~|XLen1[`LEN1-2:`NF1] & ~XFracZero;
|
||||
assign YOrigDenormE = FmtE ? 0 : ~|YLen1[`LEN1-2:`NF1] & ~YFracZero;
|
||||
assign ZOrigDenormE = FmtE ? 0 : ~|ZLen1[`LEN1-2:`NF1] & ~ZFracZero;
|
||||
|
||||
// extract the fraction, add trailing zeroes to the mantissa if nessisary
|
||||
assign XFracE = FmtE ? X[`NF-1:0] : {XLen1[`NF1-1:0], (`NF-`NF1)'(0)};
|
||||
@ -130,8 +139,9 @@ module unpack (
|
||||
// quad and double and half
|
||||
// quad and single and half
|
||||
|
||||
logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for larger percision
|
||||
logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for smallest precision
|
||||
logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for larger percision
|
||||
logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for smallest precision
|
||||
logic XOrigDenormE, YOrigDenormE; // the original value of XYZ is denormalized
|
||||
|
||||
// Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for larger precision
|
||||
assign XLen1 = &X[`FLEN-1:`LEN1] ? X[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)};
|
||||
@ -143,6 +153,75 @@ module unpack (
|
||||
assign YLen2 = &Y[`FLEN-1:`LEN2] ? Y[`LEN2-1:0] : {1'b0, {`NE2+1{1'b1}}, (`NF2-1)'(0)};
|
||||
assign ZLen2 = &Z[`FLEN-1:`LEN2] ? Z[`LEN2-1:0] : {1'b0, {`NE2+1{1'b1}}, (`NF2-1)'(0)};
|
||||
|
||||
// There are 2 case statements
|
||||
// - one for other singals and one for sgn/exp/frac
|
||||
// - need two for the dependencies in the expoenent calculation
|
||||
always_comb begin
|
||||
case (FmtE)
|
||||
`FMT: begin // if input is largest precision (`FLEN - ie quad or double)
|
||||
|
||||
// This is the original format so set OrigDenorm to 0
|
||||
XOrigDenormE = 1'b0;
|
||||
YOrigDenormE = 1'b0;
|
||||
ZOrigDenormE = 1'b0;
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |X[`FLEN-2:`NF];
|
||||
YExpNonzero = |Y[`FLEN-2:`NF];
|
||||
ZExpNonzero = |Z[`FLEN-2:`NF];
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &X[`FLEN-2:`NF];
|
||||
YExpMaxE = &Y[`FLEN-2:`NF];
|
||||
ZExpMaxE = &Z[`FLEN-2:`NF];
|
||||
end
|
||||
`FMT1: begin // if input is larger precsion (`LEN1 - double or single)
|
||||
|
||||
// is the input (in it's original format) denormalized
|
||||
XOrigDenormE = ~|XLen1[`LEN1-2:`NF1] & ~XFracZero;
|
||||
YOrigDenormE = ~|YLen1[`LEN1-2:`NF1] & ~YFracZero;
|
||||
ZOrigDenormE = ~|ZLen1[`LEN1-2:`NF1] & ~ZFracZero;
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |XLen1[`LEN1-2:`NF1];
|
||||
YExpNonzero = |YLen1[`LEN1-2:`NF1];
|
||||
ZExpNonzero = |ZLen1[`LEN1-2:`NF1];
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &XLen1[`LEN1-2:`NF1];
|
||||
YExpMaxE = &YLen1[`LEN1-2:`NF1];
|
||||
ZExpMaxE = &ZLen1[`LEN1-2:`NF1];
|
||||
end
|
||||
`FMT2: begin // if input is smallest precsion (`LEN2 - single or half)
|
||||
|
||||
// is the input (in it's original format) denormalized
|
||||
XOrigDenormE = ~|XLen2[`LEN2-2:`NF2] & ~XFracZero;
|
||||
YOrigDenormE = ~|YLen2[`LEN2-2:`NF2] & ~YFracZero;
|
||||
ZOrigDenormE = ~|ZLen2[`LEN2-2:`NF2] & ~ZFracZero;
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |XLen2[`LEN2-2:`NF2];
|
||||
YExpNonzero = |YLen2[`LEN2-2:`NF2];
|
||||
ZExpNonzero = |ZLen2[`LEN2-2:`NF2];
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &XLen2[`LEN2-2:`NF2];
|
||||
YExpMaxE = &YLen2[`LEN2-2:`NF2];
|
||||
ZExpMaxE = &ZLen2[`LEN2-2:`NF2];
|
||||
end
|
||||
default: begin
|
||||
XOrigDenormE = 0;
|
||||
YOrigDenormE = 0;
|
||||
ZOrigDenormE = 0;
|
||||
XExpNonzero = 0;
|
||||
YExpNonzero = 0;
|
||||
ZExpNonzero = 0;
|
||||
XExpMaxE = 0;
|
||||
YExpMaxE = 0;
|
||||
ZExpMaxE = 0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
always_comb begin
|
||||
case (FmtE)
|
||||
`FMT: begin // if input is largest precision (`FLEN - ie quad or double)
|
||||
@ -160,16 +239,6 @@ module unpack (
|
||||
XFracE = X[`NF-1:0];
|
||||
YFracE = Y[`NF-1:0];
|
||||
ZFracE = Z[`NF-1:0];
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |X[`FLEN-2:`NF];
|
||||
YExpNonzero = |Y[`FLEN-2:`NF];
|
||||
ZExpNonzero = |Z[`FLEN-2:`NF];
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &X[`FLEN-2:`NF];
|
||||
YExpMaxE = &Y[`FLEN-2:`NF];
|
||||
ZExpMaxE = &Z[`FLEN-2:`NF];
|
||||
end
|
||||
`FMT1: begin // if input is larger precsion (`LEN1 - double or single)
|
||||
|
||||
@ -187,24 +256,14 @@ module unpack (
|
||||
// also need to take into account possible zero/denorm/inf/NaN values
|
||||
|
||||
// convert the larger precision's exponent to use the largest precision's bias
|
||||
XExpE = {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]};
|
||||
YExpE = {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]};
|
||||
ZExpE = {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]};
|
||||
XExpE = XOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]};
|
||||
YExpE = YOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]};
|
||||
ZExpE = ZOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]};
|
||||
|
||||
// extract the fraction and add the nessesary trailing zeros
|
||||
XFracE = {XLen1[`NF1-1:0], (`NF-`NF1)'(0)};
|
||||
YFracE = {YLen1[`NF1-1:0], (`NF-`NF1)'(0)};
|
||||
ZFracE = {ZLen1[`NF1-1:0], (`NF-`NF1)'(0)};
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |XLen1[`LEN1-2:`NF1];
|
||||
YExpNonzero = |YLen1[`LEN1-2:`NF1];
|
||||
ZExpNonzero = |ZLen1[`LEN1-2:`NF1];
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &XLen1[`LEN1-2:`NF1];
|
||||
YExpMaxE = &YLen1[`LEN1-2:`NF1];
|
||||
ZExpMaxE = &ZLen1[`LEN1-2:`NF1];
|
||||
end
|
||||
`FMT2: begin // if input is smallest precsion (`LEN2 - single or half)
|
||||
|
||||
@ -222,24 +281,14 @@ module unpack (
|
||||
// also need to take into account possible zero/denorm/inf/NaN values
|
||||
|
||||
// convert the smallest precision's exponent to use the largest precision's bias
|
||||
XExpE = {XLen2[`LEN2-2], {`NE-`NE2{~XLen2[`LEN2-2]&~XExpZero|XExpMaxE}}, XLen2[`LEN2-3:`NF2]};
|
||||
YExpE = {YLen2[`LEN2-2], {`NE-`NE2{~YLen2[`LEN2-2]&~YExpZero|YExpMaxE}}, YLen2[`LEN2-3:`NF2]};
|
||||
ZExpE = {ZLen2[`LEN2-2], {`NE-`NE2{~ZLen2[`LEN2-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`LEN2-3:`NF2]};
|
||||
XExpE = XOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {XLen2[`LEN2-2], {`NE-`NE2{~XLen2[`LEN2-2]&~XExpZero|XExpMaxE}}, XLen2[`LEN2-3:`NF2]};
|
||||
YExpE = YOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {YLen2[`LEN2-2], {`NE-`NE2{~YLen2[`LEN2-2]&~YExpZero|YExpMaxE}}, YLen2[`LEN2-3:`NF2]};
|
||||
ZExpE = ZOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {ZLen2[`LEN2-2], {`NE-`NE2{~ZLen2[`LEN2-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`LEN2-3:`NF2]};
|
||||
|
||||
// extract the fraction and add the nessesary trailing zeros
|
||||
XFracE = {XLen2[`NF2-1:0], (`NF-`NF2)'(0)};
|
||||
YFracE = {YLen2[`NF2-1:0], (`NF-`NF2)'(0)};
|
||||
ZFracE = {ZLen2[`NF2-1:0], (`NF-`NF2)'(0)};
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |XLen2[`LEN2-2:`NF2];
|
||||
YExpNonzero = |YLen2[`LEN2-2:`NF2];
|
||||
ZExpNonzero = |ZLen2[`LEN2-2:`NF2];
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &XLen2[`LEN2-2:`NF2];
|
||||
YExpMaxE = &YLen2[`LEN2-2:`NF2];
|
||||
ZExpMaxE = &ZLen2[`LEN2-2:`NF2];
|
||||
end
|
||||
default: begin
|
||||
XSgnE = 0;
|
||||
@ -251,12 +300,6 @@ module unpack (
|
||||
XFracE = 0;
|
||||
YFracE = 0;
|
||||
ZFracE = 0;
|
||||
XExpNonzero = 0;
|
||||
YExpNonzero = 0;
|
||||
ZExpNonzero = 0;
|
||||
XExpMaxE = 0;
|
||||
YExpMaxE = 0;
|
||||
ZExpMaxE = 0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
@ -272,9 +315,10 @@ module unpack (
|
||||
// `Q_FMT | `D_FMT | `S_FMT | `H_FMT precision's format value - Q=11 D=01 S=00 H=10
|
||||
|
||||
|
||||
logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for double percision
|
||||
logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for single percision
|
||||
logic [`LEN2-1:0] XLen3, YLen3, ZLen3; // Remove NaN boxing or NaN, if not properly NaN boxed for half percision
|
||||
logic [`D_LEN-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for double percision
|
||||
logic [`S_LEN-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for single percision
|
||||
logic [`H_LEN-1:0] XLen3, YLen3, ZLen3; // Remove NaN boxing or NaN, if not properly NaN boxed for half percision
|
||||
logic XOrigDenormE, YOrigDenormE; // the original value of XYZ is denormalized
|
||||
|
||||
// Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for double precision
|
||||
assign XLen1 = &X[`Q_LEN-1:`D_LEN] ? X[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)};
|
||||
@ -291,6 +335,83 @@ module unpack (
|
||||
assign YLen3 = &Y[`Q_LEN-1:`H_LEN] ? Y[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)};
|
||||
assign ZLen3 = &Z[`Q_LEN-1:`H_LEN] ? Z[`H_LEN-1:0] : {1'b0, {`H_NE+1{1'b1}}, (`H_NF-1)'(0)};
|
||||
|
||||
|
||||
// There are 2 case statements
|
||||
// - one for other singals and one for sgn/exp/frac
|
||||
// - need two for the dependencies in the expoenent calculation
|
||||
always_comb begin
|
||||
case (FmtE)
|
||||
2'b11: begin // if input is quad percision
|
||||
|
||||
// This is the original format so set OrigDenorm to 0
|
||||
XOrigDenormE = 1'b0;
|
||||
YOrigDenormE = 1'b0;
|
||||
ZOrigDenormE = 1'b0;
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |X[`Q_LEN-2:`Q_NF];
|
||||
YExpNonzero = |Y[`Q_LEN-2:`Q_NF];
|
||||
ZExpNonzero = |Z[`Q_LEN-2:`Q_NF];
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &X[`Q_LEN-2:`Q_NF];
|
||||
YExpMaxE = &Y[`Q_LEN-2:`Q_NF];
|
||||
ZExpMaxE = &Z[`Q_LEN-2:`Q_NF];
|
||||
end
|
||||
2'b01: begin // if input is double percision
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &XLen1[`D_LEN-2:`D_NF];
|
||||
YExpMaxE = &YLen1[`D_LEN-2:`D_NF];
|
||||
ZExpMaxE = &ZLen1[`D_LEN-2:`D_NF];
|
||||
|
||||
// is the input (in it's original format) denormalized
|
||||
XOrigDenormE = ~|XLen1[`D_LEN-2:`D_NF] & ~XFracZero;
|
||||
YOrigDenormE = ~|YLen1[`D_LEN-2:`D_NF] & ~YFracZero;
|
||||
ZOrigDenormE = ~|ZLen1[`D_LEN-2:`D_NF] & ~ZFracZero;
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |XLen1[`D_LEN-2:`D_NF];
|
||||
YExpNonzero = |YLen1[`D_LEN-2:`D_NF];
|
||||
ZExpNonzero = |ZLen1[`D_LEN-2:`D_NF];
|
||||
end
|
||||
2'b00: begin // if input is single percision
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &XLen2[`S_LEN-2:`S_NF];
|
||||
YExpMaxE = &YLen2[`S_LEN-2:`S_NF];
|
||||
ZExpMaxE = &ZLen2[`S_LEN-2:`S_NF];
|
||||
|
||||
// is the input (in it's original format) denormalized
|
||||
XOrigDenormE = ~|XLen2[`S_LEN-2:`S_NF] & ~XFracZero;
|
||||
YOrigDenormE = ~|YLen2[`S_LEN-2:`S_NF] & ~YFracZero;
|
||||
ZOrigDenormE = ~|ZLen2[`S_LEN-2:`S_NF] & ~ZFracZero;
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |XLen2[`S_LEN-2:`S_NF];
|
||||
YExpNonzero = |YLen2[`S_LEN-2:`S_NF];
|
||||
ZExpNonzero = |ZLen2[`S_LEN-2:`S_NF];
|
||||
end
|
||||
2'b10: begin // if input is half percision
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &XLen3[`H_LEN-2:`H_NF];
|
||||
YExpMaxE = &YLen3[`H_LEN-2:`H_NF];
|
||||
ZExpMaxE = &ZLen3[`H_LEN-2:`H_NF];
|
||||
|
||||
// is the input (in it's original format) denormalized
|
||||
XOrigDenormE = ~|XLen3[`H_LEN-2:`H_NF] & ~XFracZero;
|
||||
YOrigDenormE = ~|YLen3[`H_LEN-2:`H_NF] & ~YFracZero;
|
||||
ZOrigDenormE = ~|ZLen3[`H_LEN-2:`H_NF] & ~ZFracZero;
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |XLen3[`H_LEN-2:`H_NF];
|
||||
YExpNonzero = |YLen3[`H_LEN-2:`H_NF];
|
||||
ZExpNonzero = |ZLen3[`H_LEN-2:`H_NF];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
case (FmtE)
|
||||
2'b11: begin // if input is quad percision
|
||||
@ -308,16 +429,6 @@ module unpack (
|
||||
XFracE = X[`Q_NF-1:0];
|
||||
YFracE = Y[`Q_NF-1:0];
|
||||
ZFracE = Z[`Q_NF-1:0];
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |X[`Q_LEN-2:`Q_NF];
|
||||
YExpNonzero = |Y[`Q_LEN-2:`Q_NF];
|
||||
ZExpNonzero = |Z[`Q_LEN-2:`Q_NF];
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &X[`Q_LEN-2:`Q_NF];
|
||||
YExpMaxE = &Y[`Q_LEN-2:`Q_NF];
|
||||
ZExpMaxE = &Z[`Q_LEN-2:`Q_NF];
|
||||
end
|
||||
2'b01: begin // if input is double percision
|
||||
// extract sign bit
|
||||
@ -334,24 +445,15 @@ module unpack (
|
||||
// also need to take into account possible zero/denorm/inf/NaN values
|
||||
|
||||
// convert the double precsion exponent into quad precsion
|
||||
XExpE = {XLen1[`D_LEN-2], {`Q_NE-`D_NE{~XLen1[`D_LEN-2]&~XExpZero|XExpMaxE}}, XLen1[`D_LEN-3:`D_NF]};
|
||||
YExpE = {YLen1[`D_LEN-2], {`Q_NE-`D_NE{~YLen1[`D_LEN-2]&~YExpZero|YExpMaxE}}, YLen1[`D_LEN-3:`D_NF]};
|
||||
ZExpE = {ZLen1[`D_LEN-2], {`Q_NE-`D_NE{~ZLen1[`D_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`D_LEN-3:`D_NF]};
|
||||
|
||||
XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {XLen1[`D_LEN-2], {`Q_NE-`D_NE{~XLen1[`D_LEN-2]&~XExpZero|XExpMaxE}}, XLen1[`D_LEN-3:`D_NF]};
|
||||
YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {YLen1[`D_LEN-2], {`Q_NE-`D_NE{~YLen1[`D_LEN-2]&~YExpZero|YExpMaxE}}, YLen1[`D_LEN-3:`D_NF]};
|
||||
ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {ZLen1[`D_LEN-2], {`Q_NE-`D_NE{~ZLen1[`D_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`D_LEN-3:`D_NF]};
|
||||
|
||||
// extract the fraction and add the nessesary trailing zeros
|
||||
XFracE = {XLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)};
|
||||
YFracE = {YLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)};
|
||||
ZFracE = {ZLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)};
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |XLen1[`D_LEN-2:`D_NE];
|
||||
YExpNonzero = |YLen1[`D_LEN-2:`D_NE];
|
||||
ZExpNonzero = |ZLen1[`D_LEN-2:`D_NE];
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &XLen1[`D_LEN-2:`D_NE];
|
||||
YExpMaxE = &YLen1[`D_LEN-2:`D_NE];
|
||||
ZExpMaxE = &ZLen1[`D_LEN-2:`D_NE];
|
||||
XFracE = {XLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)};
|
||||
YFracE = {YLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)};
|
||||
ZFracE = {ZLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)};
|
||||
end
|
||||
2'b00: begin // if input is single percision
|
||||
// extract sign bit
|
||||
@ -368,24 +470,14 @@ module unpack (
|
||||
// also need to take into account possible zero/denorm/inf/NaN values
|
||||
|
||||
// convert the single precsion exponent into quad precsion
|
||||
XExpE = {XLen2[`S_LEN-2], {`Q_NE-`S_NE{~XLen2[`S_LEN-2]&~XExpZero|XExpMaxE}}, XLen2[`S_LEN-3:`S_NF]};
|
||||
YExpE = {YLen2[`S_LEN-2], {`Q_NE-`S_NE{~YLen2[`S_LEN-2]&~YExpZero|YExpMaxE}}, YLen2[`S_LEN-3:`S_NF]};
|
||||
ZExpE = {ZLen2[`S_LEN-2], {`Q_NE-`S_NE{~ZLen2[`S_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`S_LEN-3:`S_NF]};
|
||||
XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {XLen2[`S_LEN-2], {`Q_NE-`S_NE{~XLen2[`S_LEN-2]&~XExpZero|XExpMaxE}}, XLen2[`S_LEN-3:`S_NF]};
|
||||
YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {YLen2[`S_LEN-2], {`Q_NE-`S_NE{~YLen2[`S_LEN-2]&~YExpZero|YExpMaxE}}, YLen2[`S_LEN-3:`S_NF]};
|
||||
ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {ZLen2[`S_LEN-2], {`Q_NE-`S_NE{~ZLen2[`S_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`S_LEN-3:`S_NF]};
|
||||
|
||||
// extract the fraction and add the nessesary trailing zeros
|
||||
XFracE = {XLen2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)};
|
||||
YFracE = {YLen2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)};
|
||||
ZFracE = {ZLen2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)};
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |XLen2[`S_LEN-2:`S_NF];
|
||||
YExpNonzero = |YLen2[`S_LEN-2:`S_NF];
|
||||
ZExpNonzero = |ZLen2[`S_LEN-2:`S_NF];
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &XLen2[`S_LEN-2:`S_NF];
|
||||
YExpMaxE = &YLen2[`S_LEN-2:`S_NF];
|
||||
ZExpMaxE = &ZLen2[`S_LEN-2:`S_NF];
|
||||
end
|
||||
2'b10: begin // if input is half percision
|
||||
// extract sign bit
|
||||
@ -400,26 +492,16 @@ module unpack (
|
||||
// sexp = 0000 bbbb bbbb (add this) b = bit d = ~b
|
||||
// dexp = 0bdd dbbb bbbb
|
||||
// also need to take into account possible zero/denorm/inf/NaN values
|
||||
|
||||
|
||||
// convert the half precsion exponent into quad precsion
|
||||
XExpE = {XLen3[`H_LEN-2], {`Q_NE-`H_NE{~XLen3[`H_LEN-2]&~XExpZero|XExpMaxE}}, XLen3[`H_LEN-3:`H_NF]};
|
||||
YExpE = {YLen3[`H_LEN-2], {`Q_NE-`H_NE{~YLen3[`H_LEN-2]&~YExpZero|YExpMaxE}}, YLen3[`H_LEN-3:`H_NF]};
|
||||
ZExpE = {ZLen3[`H_LEN-2], {`Q_NE-`H_NE{~ZLen3[`H_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen3[`H_LEN-3:`H_NF]};
|
||||
XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {XLen3[`H_LEN-2], {`Q_NE-`H_NE{~XLen3[`H_LEN-2]&~XExpZero|XExpMaxE}}, XLen3[`H_LEN-3:`H_NF]};
|
||||
YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {YLen3[`H_LEN-2], {`Q_NE-`H_NE{~YLen3[`H_LEN-2]&~YExpZero|YExpMaxE}}, YLen3[`H_LEN-3:`H_NF]};
|
||||
ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {ZLen3[`H_LEN-2], {`Q_NE-`H_NE{~ZLen3[`H_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen3[`H_LEN-3:`H_NF]};
|
||||
|
||||
// extract the fraction and add the nessesary trailing zeros
|
||||
XFracE = {XLen3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)};
|
||||
YFracE = {YLen3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)};
|
||||
ZFracE = {ZLen3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)};
|
||||
|
||||
// is the exponent non-zero
|
||||
XExpNonzero = |XLen3[`H_LEN-2:`H_NF];
|
||||
YExpNonzero = |YLen3[`H_LEN-2:`H_NF];
|
||||
ZExpNonzero = |ZLen3[`H_LEN-2:`H_NF];
|
||||
|
||||
// is the exponent all 1's
|
||||
XExpMaxE = &XLen3[`H_LEN-2:`H_NF];
|
||||
YExpMaxE = &YLen3[`H_LEN-2:`H_NF];
|
||||
ZExpMaxE = &ZLen3[`H_LEN-2:`H_NF];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
@ -116,7 +116,7 @@ module bpred
|
||||
|
||||
// this predictor will have two pieces of data,
|
||||
// 1) A direction (1 = Taken, 0 = Not Taken)
|
||||
// 2) Any information which is necessary for the predictor to built it's next state.
|
||||
// 2) Any information which is necessary for the predictor to build its next state.
|
||||
// For a 2 bit table this is the prediction count.
|
||||
|
||||
assign SelBPPredF = ((BPInstrClassF[0] & BPPredF[1] & BTBValidF) |
|
||||
|
@ -3,6 +3,14 @@
|
||||
// & mmasserfrye@hmc.edu
|
||||
// Measure PPA of various building blocks
|
||||
|
||||
module ppa_comparator_8 #(parameter WIDTH=8) (
|
||||
input logic [WIDTH-1:0] a, b,
|
||||
input logic sgnd,
|
||||
output logic [1:0] flags);
|
||||
|
||||
ppa_comparator #(WIDTH) comp (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_comparator_16 #(parameter WIDTH=16) (
|
||||
input logic [WIDTH-1:0] a, b,
|
||||
input logic sgnd,
|
||||
@ -27,6 +35,14 @@ module ppa_comparator_64 #(parameter WIDTH=64) (
|
||||
ppa_comparator #(WIDTH) comp (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_comparator_128 #(parameter WIDTH=128) (
|
||||
input logic [WIDTH-1:0] a, b,
|
||||
input logic sgnd,
|
||||
output logic [1:0] flags);
|
||||
|
||||
ppa_comparator #(WIDTH) comp (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_comparator #(parameter WIDTH=16) (
|
||||
input logic [WIDTH-1:0] a, b,
|
||||
input logic sgnd,
|
||||
@ -45,6 +61,13 @@ module ppa_comparator #(parameter WIDTH=16) (
|
||||
assign flags = {eq, lt};
|
||||
endmodule
|
||||
|
||||
module ppa_add_8 #(parameter WIDTH=8) (
|
||||
input logic [WIDTH-1:0] a, b,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = a + b;
|
||||
endmodule
|
||||
|
||||
module ppa_add_16 #(parameter WIDTH=16) (
|
||||
input logic [WIDTH-1:0] a, b,
|
||||
output logic [WIDTH-1:0] y);
|
||||
@ -66,6 +89,19 @@ module ppa_add_64 #(parameter WIDTH=64) (
|
||||
assign y = a + b;
|
||||
endmodule
|
||||
|
||||
module ppa_add_128 #(parameter WIDTH=128) (
|
||||
input logic [WIDTH-1:0] a, b,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = a + b;
|
||||
endmodule
|
||||
|
||||
module ppa_mult_8 #(parameter WIDTH=8) (
|
||||
input logic [WIDTH-1:0] a, b,
|
||||
output logic [WIDTH*2-1:0] y); //is this right width
|
||||
assign y = a * b;
|
||||
endmodule
|
||||
|
||||
module ppa_mult_16 #(parameter WIDTH=16) (
|
||||
input logic [WIDTH-1:0] a, b,
|
||||
output logic [WIDTH*2-1:0] y); //is this right width
|
||||
@ -84,6 +120,12 @@ module ppa_mult_64 #(parameter WIDTH=64) (
|
||||
assign y = a * b;
|
||||
endmodule
|
||||
|
||||
module ppa_mult_128 #(parameter WIDTH=128) (
|
||||
input logic [WIDTH-1:0] a, b,
|
||||
output logic [WIDTH*2-1:0] y); //is this right width
|
||||
assign y = a * b;
|
||||
endmodule
|
||||
|
||||
module ppa_alu_16 #(parameter WIDTH=16) (
|
||||
input logic [WIDTH-1:0] A, B,
|
||||
input logic [2:0] ALUControl,
|
||||
@ -172,7 +214,7 @@ module ppa_alu #(parameter WIDTH=32) (
|
||||
else assign Result = FullResult;
|
||||
endmodule
|
||||
|
||||
module ppa_shiftleft #(parameter WIDTH=32) (
|
||||
module ppa_shiftleft_8 #(parameter WIDTH=8) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
input logic [$clog2(WIDTH)-1:0] amt,
|
||||
output logic [WIDTH-1:0] y);
|
||||
@ -180,12 +222,89 @@ module ppa_shiftleft #(parameter WIDTH=32) (
|
||||
assign y = a << amt;
|
||||
endmodule
|
||||
|
||||
module ppa_shiftleft_16 #(parameter WIDTH=16) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
input logic [$clog2(WIDTH)-1:0] amt,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = a << amt;
|
||||
endmodule
|
||||
|
||||
module ppa_shiftleft_32 #(parameter WIDTH=32) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
input logic [$clog2(WIDTH)-1:0] amt,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = a << amt;
|
||||
endmodule
|
||||
|
||||
module ppa_shiftleft_64 #(parameter WIDTH=64) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
input logic [$clog2(WIDTH)-1:0] amt,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = a << amt;
|
||||
endmodule
|
||||
|
||||
module ppa_shiftleft_128 #(parameter WIDTH=128) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
input logic [$clog2(WIDTH)-1:0] amt,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = a << amt;
|
||||
endmodule
|
||||
|
||||
module ppa_shifter_8 #(parameter WIDTH=8) (
|
||||
input logic [WIDTH-1:0] A,
|
||||
input logic [$clog2(WIDTH)-1:0] Amt,
|
||||
input logic Right, Arith, W64,
|
||||
output logic [WIDTH-1:0] Y);
|
||||
|
||||
ppa_shifter #(WIDTH) sh (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_shifter_16 #(parameter WIDTH=16) (
|
||||
input logic [WIDTH-1:0] A,
|
||||
input logic [$clog2(WIDTH)-1:0] Amt,
|
||||
input logic Right, Arith, W64,
|
||||
output logic [WIDTH-1:0] Y);
|
||||
|
||||
ppa_shifter #(WIDTH) sh (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_shifter_32 #(parameter WIDTH=32) (
|
||||
input logic [WIDTH-1:0] A,
|
||||
input logic [$clog2(WIDTH)-1:0] Amt,
|
||||
input logic Right, Arith, W64,
|
||||
output logic [WIDTH-1:0] Y);
|
||||
|
||||
ppa_shifter #(WIDTH) sh (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_shifter_64 #(parameter WIDTH=64) (
|
||||
input logic [WIDTH-1:0] A,
|
||||
input logic [$clog2(WIDTH)-1:0] Amt,
|
||||
input logic Right, Arith, W64,
|
||||
output logic [WIDTH-1:0] Y);
|
||||
|
||||
ppa_shifter #(WIDTH) sh (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_shifter_128 #(parameter WIDTH=128) (
|
||||
input logic [WIDTH-1:0] A,
|
||||
input logic [$clog2(WIDTH)-1:0] Amt,
|
||||
input logic Right, Arith, W64,
|
||||
output logic [WIDTH-1:0] Y);
|
||||
|
||||
ppa_shifter #(WIDTH) sh (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_shifter #(parameter WIDTH=32) (
|
||||
input logic [WIDTH-1:0] A,
|
||||
input logic [$clog2(WIDTH)-1:0] Amt,
|
||||
input logic Right, Arith, W64,
|
||||
output logic [WIDTH-1:0] Y);
|
||||
|
||||
logic [2*WIDTH-2:0] z, zshift;
|
||||
logic [$clog2(WIDTH)-1:0] amttrunc, offset;
|
||||
|
||||
@ -194,28 +313,29 @@ module ppa_shifter_32 #(parameter WIDTH=32) (
|
||||
// For RV64, 32 and 64-bit shifts are needed, with sign extension.
|
||||
|
||||
// funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
|
||||
if (WIDTH==32) begin:shifter // RV32
|
||||
always_comb // funnel mux
|
||||
if (Right)
|
||||
if (Arith) z = {{31{A[31]}}, A};
|
||||
else z = {31'b0, A};
|
||||
else z = {A, 31'b0};
|
||||
assign amttrunc = Amt; // shift amount
|
||||
end else begin:shifter // RV64
|
||||
if (WIDTH == 64 | WIDTH ==128) begin:shifter // RV64 or 128
|
||||
always_comb // funnel mux
|
||||
if (W64) begin // 32-bit shifts
|
||||
if (Right)
|
||||
if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]};
|
||||
else z = {95'b0, A[31:0]};
|
||||
else z = {32'b0, A[31:0], 63'b0};
|
||||
if (Arith) z = {{WIDTH{1'b0}}, {WIDTH/2 -1{A[WIDTH/2 -1]}}, A[WIDTH/2 -1:0]};
|
||||
else z = {{WIDTH*3/2-1{1'b0}}, A[WIDTH/2 -1:0]};
|
||||
else z = {{WIDTH/2{1'b0}}, A[WIDTH/2 -1:0], {WIDTH-1{1'b0}}};
|
||||
end else begin
|
||||
if (Right)
|
||||
if (Arith) z = {{63{A[63]}}, A};
|
||||
else z = {63'b0, A};
|
||||
else z = {A, 63'b0};
|
||||
if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A};
|
||||
else z = {{WIDTH-1{1'b0}}, A};
|
||||
else z = {A, {WIDTH-1{1'b0}}};
|
||||
end
|
||||
assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift
|
||||
end
|
||||
assign amttrunc = W64 ? {1'b0, Amt[$clog2(WIDTH)-2:0]} : Amt; // 32 or 64-bit shift
|
||||
end else begin:shifter // RV32 or less
|
||||
always_comb // funnel mux
|
||||
if (Right)
|
||||
if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A};
|
||||
else z = {{WIDTH-1{1'b0}}, A};
|
||||
else z = {A, {WIDTH-1{1'b0}}};
|
||||
assign amttrunc = Amt; // shift amount
|
||||
end
|
||||
|
||||
|
||||
// opposite offset for right shfits
|
||||
assign offset = Right ? amttrunc : ~amttrunc;
|
||||
@ -225,6 +345,7 @@ module ppa_shifter_32 #(parameter WIDTH=32) (
|
||||
assign Y = zshift[WIDTH-1:0];
|
||||
endmodule
|
||||
|
||||
// just report one hot
|
||||
module ppa_prioritythermometer #(parameter N = 8) (
|
||||
input logic [N-1:0] a,
|
||||
output logic [N-1:0] y);
|
||||
@ -240,30 +361,132 @@ module ppa_prioritythermometer #(parameter N = 8) (
|
||||
end
|
||||
endmodule
|
||||
|
||||
module ppa_priorityonehot #(parameter N = 8) (
|
||||
input logic [N-1:0] a,
|
||||
output logic [N-1:0] y);
|
||||
logic [N-1:0] nolower;
|
||||
module ppa_priorityonehot #(parameter WIDTH = 8) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
output logic [WIDTH-1:0] y);
|
||||
logic [WIDTH-1:0] nolower;
|
||||
|
||||
// create thermometer code mask
|
||||
ppa_prioritythermometer #(N) maskgen(.a({a[N-2:0], 1'b0}), .y(nolower));
|
||||
ppa_prioritythermometer #(WIDTH) maskgen(.a({a[WIDTH-2:0], 1'b0}), .y(nolower));
|
||||
assign y = a & nolower;
|
||||
endmodule
|
||||
|
||||
module ppa_prioriyencoder #(parameter N = 8) (
|
||||
input logic [N-1:0] a,
|
||||
output logic [$clog2(N)-1:0] y);
|
||||
// Carefully crafted so design compiler will synthesize into a fast tree structure
|
||||
// Rather than linear.
|
||||
module ppa_priorityonehot_8 #(parameter WIDTH = 8) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
output logic [WIDTH-1:0] y);
|
||||
logic [WIDTH-1:0] nolower;
|
||||
|
||||
// create thermometer code mask
|
||||
ppa_priorityonehot #(WIDTH) poh (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_priorityonehot_16 #(parameter WIDTH = 16) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
output logic [WIDTH-1:0] y);
|
||||
logic [WIDTH-1:0] nolower;
|
||||
|
||||
// create thermometer code mask
|
||||
ppa_priorityonehot #(WIDTH) poh (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_priorityonehot_32 #(parameter WIDTH = 32) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
output logic [WIDTH-1:0] y);
|
||||
logic [WIDTH-1:0] nolower;
|
||||
|
||||
// create thermometer code mask
|
||||
ppa_priorityonehot #(WIDTH) poh (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_priorityonehot_64 #(parameter WIDTH = 64) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
output logic [WIDTH-1:0] y);
|
||||
logic [WIDTH-1:0] nolower;
|
||||
|
||||
// create thermometer code mask
|
||||
ppa_priorityonehot #(WIDTH) poh (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_priorityonehot_128 #(parameter WIDTH = 128) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
output logic [WIDTH-1:0] y);
|
||||
logic [WIDTH-1:0] nolower;
|
||||
|
||||
// create thermometer code mask
|
||||
ppa_priorityonehot #(WIDTH) poh (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_priorityencoder_8 #(parameter WIDTH = 8) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
output logic [$clog2(WIDTH)-1:0] y);
|
||||
ppa_priorityencoder #(WIDTH) pe (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_priorityencoder_16 #(parameter WIDTH = 16) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
output logic [$clog2(WIDTH)-1:0] y);
|
||||
ppa_priorityencoder #(WIDTH) pe (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_priorityencoder_32 #(parameter WIDTH = 32) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
output logic [$clog2(WIDTH)-1:0] y);
|
||||
ppa_priorityencoder #(WIDTH) pe (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_priorityencoder_64 #(parameter WIDTH = 64) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
output logic [$clog2(WIDTH)-1:0] y);
|
||||
ppa_priorityencoder #(WIDTH) pe (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_priorityencoder_128 #(parameter WIDTH = 128) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
output logic [$clog2(WIDTH)-1:0] y);
|
||||
ppa_priorityencoder #(WIDTH) pe (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_priorityencoder #(parameter WIDTH = 8) (
|
||||
input logic [WIDTH-1:0] a,
|
||||
output logic [$clog2(WIDTH)-1:0] y);
|
||||
|
||||
int i;
|
||||
always_comb
|
||||
for (i=0; i<N; i++) begin:pri
|
||||
for (i=0; i<WIDTH; i++) begin:pri
|
||||
if (a[i]) y= i;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module ppa_decoder_8 #(parameter WIDTH = 8) (
|
||||
input logic [$clog2(WIDTH)-1:0] a,
|
||||
output logic [WIDTH-1:0] y);
|
||||
ppa_decoder #(WIDTH) dec (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_decoder_16 #(parameter WIDTH = 16) (
|
||||
input logic [$clog2(WIDTH)-1:0] a,
|
||||
output logic [WIDTH-1:0] y);
|
||||
ppa_decoder #(WIDTH) dec (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_decoder_32 #(parameter WIDTH = 32) (
|
||||
input logic [$clog2(WIDTH)-1:0] a,
|
||||
output logic [WIDTH-1:0] y);
|
||||
ppa_decoder #(WIDTH) dec (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_decoder_64 #(parameter WIDTH = 64) (
|
||||
input logic [$clog2(WIDTH)-1:0] a,
|
||||
output logic [WIDTH-1:0] y);
|
||||
ppa_decoder #(WIDTH) dec (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_decoder_128 #(parameter WIDTH = 128) (
|
||||
input logic [$clog2(WIDTH)-1:0] a,
|
||||
output logic [WIDTH-1:0] y);
|
||||
ppa_decoder #(WIDTH) dec (.*);
|
||||
endmodule
|
||||
|
||||
module ppa_decoder #(parameter WIDTH = 8) (
|
||||
input logic [$clog2(WIDTH)-1:0] a,
|
||||
output logic [WIDTH-1:0] y);
|
||||
@ -273,7 +496,7 @@ module ppa_decoder #(parameter WIDTH = 8) (
|
||||
end
|
||||
endmodule
|
||||
|
||||
module ppa_mux2 #(parameter WIDTH = 8) (
|
||||
module ppa_mux2_8 #(parameter WIDTH = 8) (
|
||||
input logic [WIDTH-1:0] d0, d1,
|
||||
input logic s,
|
||||
output logic [WIDTH-1:0] y);
|
||||
@ -315,7 +538,7 @@ endmodule
|
||||
|
||||
// *** some way to express data-critical inputs
|
||||
|
||||
module ppa_flop #(parameter WIDTH = 8) (
|
||||
module ppa_flop_8 #(parameter WIDTH = 8) (
|
||||
input logic clk,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
@ -324,7 +547,43 @@ module ppa_flop #(parameter WIDTH = 8) (
|
||||
q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flopr #(parameter WIDTH = 8) (
|
||||
module ppa_flop_16 #(parameter WIDTH = 16) (
|
||||
input logic clk,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flop_32 #(parameter WIDTH = 32) (
|
||||
input logic clk,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flop_64 #(parameter WIDTH = 64) (
|
||||
input logic clk,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flop_128 #(parameter WIDTH = 128) (
|
||||
input logic clk,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flopr_8 #(parameter WIDTH = 8) (
|
||||
input logic clk, reset,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
@ -334,7 +593,47 @@ module ppa_flopr #(parameter WIDTH = 8) (
|
||||
else q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_floprasynnc #(parameter WIDTH = 8) (
|
||||
module ppa_flopr_16 #(parameter WIDTH = 16) (
|
||||
input logic clk, reset,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) q <= #1 0;
|
||||
else q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flopr_32 #(parameter WIDTH = 32) (
|
||||
input logic clk, reset,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) q <= #1 0;
|
||||
else q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flopr_64 #(parameter WIDTH = 64) (
|
||||
input logic clk, reset,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) q <= #1 0;
|
||||
else q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flopr_128 #(parameter WIDTH = 128) (
|
||||
input logic clk, reset,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) q <= #1 0;
|
||||
else q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_floprasync_8 #(parameter WIDTH = 8) (
|
||||
input logic clk, reset,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
@ -344,7 +643,47 @@ module ppa_floprasynnc #(parameter WIDTH = 8) (
|
||||
else q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flopenr #(parameter WIDTH = 8) (
|
||||
module ppa_floprasync_16 #(parameter WIDTH = 16) (
|
||||
input logic clk, reset,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
if (reset) q <= #1 0;
|
||||
else q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_floprasync_32 #(parameter WIDTH = 32) (
|
||||
input logic clk, reset,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
if (reset) q <= #1 0;
|
||||
else q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_floprasync_64 #(parameter WIDTH = 64) (
|
||||
input logic clk, reset,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
if (reset) q <= #1 0;
|
||||
else q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_floprasync_128 #(parameter WIDTH = 128) (
|
||||
input logic clk, reset,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
if (reset) q <= #1 0;
|
||||
else q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flopenr_8 #(parameter WIDTH = 8) (
|
||||
input logic clk, reset, en,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
@ -353,3 +692,52 @@ module ppa_flopenr #(parameter WIDTH = 8) (
|
||||
if (reset) q <= #1 0;
|
||||
else if (en) q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flopenr_16 #(parameter WIDTH = 16) (
|
||||
input logic clk, reset, en,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) q <= #1 0;
|
||||
else if (en) q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flopenr_32 #(parameter WIDTH = 32) (
|
||||
input logic clk, reset, en,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) q <= #1 0;
|
||||
else if (en) q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flopenr_64 #(parameter WIDTH = 64) (
|
||||
input logic clk, reset, en,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) q <= #1 0;
|
||||
else if (en) q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module ppa_flopenr_128 #(parameter WIDTH = 128) (
|
||||
input logic clk, reset, en,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) q <= #1 0;
|
||||
else if (en) q <= #1 d;
|
||||
endmodule
|
||||
|
||||
module csa #(parameter WIDTH=8) (
|
||||
input logic [WIDTH-1:0] a, b, c,
|
||||
output logic [WIDTH-1:0] sum, carry);
|
||||
|
||||
assign sum = a ^ b ^ c;
|
||||
assign carry = (a & (b | c)) | (b & c);
|
||||
|
||||
endmodule // csa
|
@ -3,5 +3,5 @@ all: sqrttestgen testgen
|
||||
sqrttestgen: sqrttestgen.c
|
||||
gcc sqrttestgen.c -lm -o sqrttestgen
|
||||
|
||||
testgen: exptestgen.c
|
||||
gcc exptestgen.c -lm -o exptestgen
|
||||
testgen: testgen.c
|
||||
gcc testgen.c -lm -o testgen
|
||||
|
Binary file not shown.
@ -1,2 +1 @@
|
||||
verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv
|
||||
verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpacking.sv
|
||||
|
@ -17,7 +17,7 @@ if [file exists work] {
|
||||
}
|
||||
vlib work
|
||||
|
||||
vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpacking.sv
|
||||
vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv
|
||||
vopt +acc work.testbench -o workopt
|
||||
vsim workopt
|
||||
|
||||
|
@ -37,8 +37,6 @@ module srt #(parameter Nf=52) (
|
||||
input logic Flush, // *** multiple pipe stages
|
||||
// Floating Point Inputs
|
||||
// later add exponents, signs, special cases
|
||||
input logic [10:0] SrcXExpE, SrcYExpE, // exponents, for double precision exponents are 11 bits
|
||||
// end of floating point inputs
|
||||
input logic [Nf-1:0] SrcXFrac, SrcYFrac,
|
||||
input logic [`XLEN-1:0] SrcA, SrcB,
|
||||
input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
|
||||
@ -47,7 +45,6 @@ module srt #(parameter Nf=52) (
|
||||
input logic Int, // Choose integer inputss
|
||||
input logic Sqrt, // perform square root, not divide
|
||||
output logic [Nf-1:0] Quot, Rem, // *** later handle integers
|
||||
output logic [10:0] Exp, // output exponent is hardcoded for 11 bits for double precision
|
||||
output logic [3:0] Flags
|
||||
);
|
||||
|
||||
@ -81,9 +78,6 @@ module srt #(parameter Nf=52) (
|
||||
// Partial Product Generation
|
||||
csa csa(WS, WC, Dsel, qp, WSA, WCA);
|
||||
|
||||
// Exponent division
|
||||
exp exp(SrcXExpE, SrcYExpE, Exp);
|
||||
|
||||
srtpostproc postproc(rp, rm, Quot);
|
||||
endmodule
|
||||
|
||||
@ -253,14 +247,6 @@ module csa #(parameter N=56) (
|
||||
(in2[54:0] & in3[54:0]), cin};
|
||||
endmodule
|
||||
|
||||
//////////////
|
||||
// exponent //
|
||||
//////////////
|
||||
module exp(input [10:0] e1, e2,
|
||||
output [10:0] e); // for double precision, exponent is 11 bits
|
||||
assign e = (e1 - e2) + 11'd1023; // bias is hardcoded
|
||||
endmodule
|
||||
|
||||
//////////////
|
||||
// finaladd //
|
||||
//////////////
|
||||
|
@ -11,9 +11,7 @@
|
||||
// This Verilog file models a radix 2 SRT divider which
|
||||
// produces one quotient digit per cycle. The divider
|
||||
// keeps the partial remainder in carry-save form.
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
|
||||
/////////
|
||||
// srt //
|
||||
/////////
|
||||
@ -328,9 +326,7 @@ module testbench;
|
||||
begin
|
||||
req <= #5 1;
|
||||
$display("result was %h, should be %h\n", r, correctr);
|
||||
//if (abs(correctr - r) > 1) // check if accurate to 1 ulp
|
||||
// giving error "srt_stanford.sv(395): (vopt-7063) Failed to find 'abs' in hierarchical name 'abs'."
|
||||
if (correctr - r > 1) // check if accurate to 1 ulp
|
||||
if ((correctr - r) > 1) // check if accurate to 1 ulp
|
||||
begin
|
||||
errors = errors+1;
|
||||
$display("failed\n");
|
||||
|
@ -40,66 +40,33 @@ module testbench;
|
||||
logic clk;
|
||||
logic req;
|
||||
logic done;
|
||||
logic [63:0] a;
|
||||
logic [63:0] b;
|
||||
logic [63:0] result;
|
||||
logic [51:0] r;
|
||||
logic [51:0] a;
|
||||
logic [51:0] b;
|
||||
logic [51:0] r;
|
||||
logic [54:0] rp, rm; // positive quotient digits
|
||||
logic [10:0] e; // output exponent
|
||||
|
||||
// input logic for Unpacker
|
||||
// input logic [63:0] X, Y, Z, - numbers
|
||||
// input logic FmtE, ---- format, 1 is for double precision, 0 is single
|
||||
// input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide
|
||||
// all variables are commented in fpu.sv
|
||||
|
||||
// output logic from Unpacker
|
||||
logic XSgnE, YSgnE, ZSgnE;
|
||||
logic [10:0] XExpE, YExpE, ZExpE; // exponent
|
||||
logic [52:0] XManE, YManE, ZManE;
|
||||
logic XNormE;
|
||||
logic XNaNE, YNaNE, ZNaNE;
|
||||
logic XSNaNE, YSNaNE, ZSNaNE;
|
||||
logic XDenormE, YDenormE, ZDenormE; // denormals
|
||||
logic XZeroE, YZeroE, ZZeroE;
|
||||
logic [10:0] BiasE; // currrently hardcoded, will probs be removed
|
||||
logic XInfE, YInfE, ZInfE;
|
||||
logic XExpMaxE; // says exponent is all ones, can ignore
|
||||
|
||||
// Test parameters
|
||||
parameter MEM_SIZE = 60000;
|
||||
parameter MEM_WIDTH = 64+64+64;
|
||||
parameter MEM_SIZE = 40000;
|
||||
parameter MEM_WIDTH = 52+52+52;
|
||||
|
||||
`define memr 63:0
|
||||
`define memb 127:64
|
||||
`define mema 191:128
|
||||
`define memr 51:0
|
||||
`define memb 103:52
|
||||
`define mema 155:104
|
||||
|
||||
// Test logicisters
|
||||
logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
|
||||
logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a
|
||||
// bit field of an array
|
||||
logic [63:0] correctr, nextr, diffn, diffp;
|
||||
logic [51:0] correctr, nextr, diffn, diffp;
|
||||
integer testnum, errors;
|
||||
|
||||
// Unpacker
|
||||
// Note: BiasE will probably get taken out eventually
|
||||
unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0),
|
||||
.XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE),
|
||||
.XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE),
|
||||
.XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE),
|
||||
.XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .BiasE(BiasE),
|
||||
.XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE));
|
||||
|
||||
// Divider
|
||||
srt #(52) srt(.clk, .Start(req),
|
||||
.Stall(1'b0), .Flush(1'b0),
|
||||
.SrcXExpE(XExpE), .SrcYExpE(YExpE),
|
||||
.SrcXFrac(XManE[51:0]), .SrcYFrac(YManE[51:0]),
|
||||
.SrcXFrac(a), .SrcYFrac(b),
|
||||
.SrcA('0), .SrcB('0), .Fmt(2'b00),
|
||||
.W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0),
|
||||
.Quot(r), .Rem(), .Exp(e), .Flags());
|
||||
|
||||
assign result = {1'b0, e, r};
|
||||
.Quot(r), .Rem(), .Flags());
|
||||
|
||||
// Counter
|
||||
counter counter(clk, req, done);
|
||||
@ -133,18 +100,16 @@ module testbench;
|
||||
if (done)
|
||||
begin
|
||||
req <= #5 1;
|
||||
diffp = correctr - result;
|
||||
diffn = result - correctr;
|
||||
diffp = correctr - r;
|
||||
diffn = r - correctr;
|
||||
if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
|
||||
begin
|
||||
errors = errors+1;
|
||||
$display("a = %h b = %h result = %h",a,b,correctr);
|
||||
$display("result was %h, should be %h %h %h\n", result, correctr, diffn, diffp);
|
||||
$display("at fail");
|
||||
$display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp);
|
||||
$display("failed\n");
|
||||
$stop;
|
||||
end
|
||||
if (a === 64'hxxxxxxxxxxxxxxxx)
|
||||
if (a === 52'hxxxxxxxxxxxxx)
|
||||
begin
|
||||
$display("%d Tests completed successfully", testnum);
|
||||
$stop;
|
||||
@ -154,14 +119,12 @@ module testbench;
|
||||
begin
|
||||
req <= #5 0;
|
||||
correctr = nextr;
|
||||
$display("pre increment");
|
||||
testnum = testnum+1;
|
||||
a = Vec[`mema];
|
||||
b = Vec[`memb];
|
||||
Vec = Tests[testnum];
|
||||
$display("a = %h b = %h result = %h",a,b,nextr);
|
||||
$display("a = %h b = %h",a,b);
|
||||
a = Vec[`mema];
|
||||
b = Vec[`memb];
|
||||
nextr = Vec[`memr];
|
||||
$display("after increment");
|
||||
end
|
||||
end
|
||||
|
||||
|
@ -28,7 +28,7 @@ double random_input(void);
|
||||
void main(void)
|
||||
{
|
||||
FILE *fptr;
|
||||
double x1, x2, a, b, r;
|
||||
double a, b, r;
|
||||
double list[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625,
|
||||
1.75, 1.875, 1.99999,
|
||||
1.1, 1.2, 1.01, 1.001, 1.0001,
|
||||
@ -63,7 +63,6 @@ void main(void)
|
||||
|
||||
void output(FILE *fptr, double a, double b, double r)
|
||||
{
|
||||
|
||||
printhex(fptr, a);
|
||||
fprintf(fptr, "_");
|
||||
printhex(fptr, b);
|
||||
|
File diff suppressed because it is too large
Load Diff
1561
pipelined/testbench/testbench-fp.sv
Normal file
1561
pipelined/testbench/testbench-fp.sv
Normal file
File diff suppressed because it is too large
Load Diff
@ -27,15 +27,6 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
`define DEBUG_TRACE 0
|
||||
// Debug Levels
|
||||
// 0: don't check against QEMU
|
||||
// 1: print disagreements with QEMU, but only halt on PCW disagreements
|
||||
// 2: halt on any disagreement with QEMU except CSRs
|
||||
// 3: halt on all disagreements with QEMU
|
||||
// 4: print memory accesses whenever they happen
|
||||
// 5: print everything
|
||||
|
||||
module testbench;
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////// CONFIG ////////////////////////////////////
|
||||
@ -45,8 +36,15 @@ module testbench;
|
||||
parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim
|
||||
parameter CHECKPOINT = 0;
|
||||
parameter RISCV_DIR = "/opt/riscv";
|
||||
parameter NO_IE_MTIME_CHECKPOINT = 0;
|
||||
|
||||
parameter NO_SPOOFING = 0;
|
||||
parameter DEBUG_TRACE = 0;
|
||||
// Debug Levels
|
||||
// 0: don't check against QEMU
|
||||
// 1: print disagreements with QEMU, but only halt on PCW disagreements
|
||||
// 2: halt on any disagreement with QEMU except CSRs
|
||||
// 3: halt on all disagreements with QEMU
|
||||
// 4: print memory accesses whenever they happen
|
||||
// 5: print everything
|
||||
|
||||
|
||||
|
||||
@ -95,7 +93,7 @@ module testbench;
|
||||
logic [`XLEN-1:0] ExpectedRegValue``STAGE; \
|
||||
logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
|
||||
string ExpectedCSRArray``STAGE[10:0]; \
|
||||
logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0];
|
||||
logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant?
|
||||
`DECLARE_TRACE_SCANNER_SIGNALS(E)
|
||||
`DECLARE_TRACE_SCANNER_SIGNALS(M)
|
||||
// M-stage expected values
|
||||
@ -218,7 +216,7 @@ module testbench;
|
||||
/////////////////////////////// Cache Issue ///////////////////////////////////
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
logic probe;
|
||||
if (NO_IE_MTIME_CHECKPOINT)
|
||||
if (NO_SPOOFING)
|
||||
assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c
|
||||
& testbench.dut.core.InstrM != 32'h14021273
|
||||
& testbench.dut.core.InstrValidM;
|
||||
@ -358,7 +356,7 @@ module testbench;
|
||||
`INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]);
|
||||
if(!NO_IE_MTIME_CHECKPOINT) begin
|
||||
if(!NO_SPOOFING) begin
|
||||
`INIT_CHECKPOINT_VAL(MIE, [11:0]);
|
||||
`INIT_CHECKPOINT_VAL(MIP, [11:0]);
|
||||
end
|
||||
@ -395,7 +393,7 @@ module testbench;
|
||||
|
||||
// ========== INITIALIZATION ==========
|
||||
initial begin
|
||||
if(!NO_IE_MTIME_CHECKPOINT) begin
|
||||
if(!NO_SPOOFING) begin
|
||||
force `MEIP = 0;
|
||||
force `SEIP = 0;
|
||||
force `UART_IP = 0;
|
||||
@ -405,7 +403,7 @@ module testbench;
|
||||
$sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR);
|
||||
if (CHECKPOINT!=0)
|
||||
$sformat(checkpointDir,"%s/linux-testvectors/checkpoint%0d/",RISCV_DIR,CHECKPOINT);
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); // *** initialize these using zeroes rather than reading from files, see testbench.sv
|
||||
$readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
|
||||
ProgramAddrMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.addr"};
|
||||
ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"};
|
||||
@ -462,7 +460,7 @@ module testbench;
|
||||
release `INSTRET;
|
||||
end
|
||||
// Get the E-stage trace reader ahead of the M-stage trace reader
|
||||
matchCountE = $fgets(lineE,traceFileE);
|
||||
matchCountE = $fgets(lineE,traceFileE); // *** look at removing?
|
||||
end
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
@ -482,7 +480,7 @@ module testbench;
|
||||
if (checkInstrM) begin \
|
||||
// read 1 line of the trace file \
|
||||
matchCount``STAGE = $fgets(line``STAGE, traceFile``STAGE); \
|
||||
if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \
|
||||
if(DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \
|
||||
// extract PC, Instr \
|
||||
matchCount``STAGE = $sscanf(line``STAGE, "%x %x %s", ExpectedPC``STAGE, ExpectedInstr``STAGE, text``STAGE); \
|
||||
if (`"STAGE`"=="M") begin \
|
||||
@ -547,16 +545,16 @@ module testbench;
|
||||
if(`"STAGE`"=="M") begin \
|
||||
// override on special conditions \
|
||||
if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) begin \
|
||||
if(!NO_IE_MTIME_CHECKPOINT) begin \
|
||||
$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, AttemptedInstructionCount); \
|
||||
if(!NO_SPOOFING) begin \
|
||||
$display("%tns, %d instrs: Overwrite UART's Register in memory stage.", $time, AttemptedInstructionCount); \
|
||||
force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
|
||||
end \
|
||||
end else \
|
||||
if(!NO_IE_MTIME_CHECKPOINT) \
|
||||
if(!NO_SPOOFING) \
|
||||
release dut.core.ieu.dp.ReadDataM; \
|
||||
if(textM.substr(0,5) == "rdtime") begin \
|
||||
//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
|
||||
if(!NO_IE_MTIME_CHECKPOINT) \
|
||||
if(!NO_SPOOFING) \
|
||||
force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
|
||||
end \
|
||||
end \
|
||||
@ -566,14 +564,14 @@ module testbench;
|
||||
`define checkEQ(NAME, VAL, EXPECTED) \
|
||||
if(VAL != EXPECTED) begin \
|
||||
$display("%tns, %d instrs: %s %x differs from expected %x", $time, AttemptedInstructionCount, NAME, VAL, EXPECTED); \
|
||||
if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \
|
||||
if ((NAME == "PCW") | (DEBUG_TRACE >= 2)) fault = 1; \
|
||||
end
|
||||
|
||||
`define checkCSR(CSR) \
|
||||
begin \
|
||||
if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \
|
||||
$display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
|
||||
if(`DEBUG_TRACE >= 3) fault = 1; \
|
||||
if(DEBUG_TRACE >= 3) fault = 1; \
|
||||
end \
|
||||
end
|
||||
|
||||
@ -633,7 +631,7 @@ module testbench;
|
||||
if(~dut.core.StallW) begin
|
||||
if(textW.substr(0,5) == "rdtime") begin
|
||||
//$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount);
|
||||
if(!NO_IE_MTIME_CHECKPOINT)
|
||||
if(!NO_SPOOFING)
|
||||
release dut.uncore.clint.clint.MTIME;
|
||||
end
|
||||
//if (ExpectedIEUAdrM == 'h10000005) begin
|
||||
@ -656,15 +654,15 @@ module testbench;
|
||||
// turn on waves
|
||||
if (AttemptedInstructionCount == INSTR_WAVEON) $stop;
|
||||
// end sim
|
||||
if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop;
|
||||
if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
|
||||
fault = 0;
|
||||
if (`DEBUG_TRACE >= 1) begin
|
||||
if (DEBUG_TRACE >= 1) begin
|
||||
`checkEQ("PCW",PCW,ExpectedPCW)
|
||||
//`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of
|
||||
// compressed to uncompressed conversion
|
||||
`checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW)
|
||||
#2; // delay 2 ns.
|
||||
if(`DEBUG_TRACE >= 5) begin
|
||||
if(DEBUG_TRACE >= 5) begin
|
||||
$display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW);
|
||||
$display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
|
||||
end
|
||||
@ -674,13 +672,13 @@ module testbench;
|
||||
`checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW)
|
||||
end
|
||||
if (MemOpW.substr(0,2) == "Mem") begin
|
||||
if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW);
|
||||
if(DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW);
|
||||
`checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW)
|
||||
if(MemOpW == "MemR" | MemOpW == "MemRW") begin
|
||||
if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW);
|
||||
if(DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW);
|
||||
`checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW)
|
||||
end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin
|
||||
if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
|
||||
if(DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
|
||||
`checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW)
|
||||
end
|
||||
end
|
||||
@ -702,7 +700,7 @@ module testbench;
|
||||
"stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW)
|
||||
"mip": begin
|
||||
`checkCSR(`CSR_BASE.csrm.MIP_REGW)
|
||||
if(!NO_IE_MTIME_CHECKPOINT) begin
|
||||
if(!NO_SPOOFING) begin
|
||||
if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<11) == 0)
|
||||
force `MEIP = 0;
|
||||
if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<09) == 0)
|
||||
@ -718,9 +716,9 @@ module testbench;
|
||||
if (fault == 1) begin
|
||||
errorCount +=1;
|
||||
$display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount);
|
||||
$stop;
|
||||
$stop; $stop;
|
||||
end
|
||||
end // if (`DEBUG_TRACE >= 1)
|
||||
end // if (DEBUG_TRACE >= 1)
|
||||
end // if (checkInstrW)
|
||||
end // always @ (negedge clk)
|
||||
|
||||
@ -734,7 +732,7 @@ module testbench;
|
||||
always @(negedge clk) begin
|
||||
if(checkInterruptM) begin
|
||||
if((interruptInstrCount+1) == AttemptedInstructionCount) begin
|
||||
if(!NO_IE_MTIME_CHECKPOINT) begin
|
||||
if(!NO_SPOOFING) begin
|
||||
case (interruptCauseVal)
|
||||
11: begin
|
||||
force `MEIP = 1;
|
||||
@ -765,7 +763,7 @@ module testbench;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
@ -327,11 +327,21 @@ logic [3:0] dummy;
|
||||
.done(DCacheFlushDone));
|
||||
|
||||
// initialize the branch predictor
|
||||
if (`BPRED_ENABLED == 1)
|
||||
initial begin
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
|
||||
$readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
|
||||
end
|
||||
if (`BPRED_ENABLED == 1)
|
||||
begin
|
||||
genvar adrindex;
|
||||
|
||||
// Initializing all zeroes into the branch predictor memory.
|
||||
for(adrindex = 0; adrindex < 1024; adrindex++) begin
|
||||
initial begin
|
||||
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
|
||||
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
|
||||
#1;
|
||||
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
|
||||
release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module riscvassertions;
|
||||
|
587
pipelined/testbench/tests-fp.vh
Normal file
587
pipelined/testbench/tests-fp.vh
Normal file
@ -0,0 +1,587 @@
|
||||
///////////////////////////////////////////
|
||||
// tests.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 7 October 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: List of tests to apply
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
|
||||
`define PATH "../../tests/fp/vectors/"
|
||||
`define ADD_OPCTRL 3'b110
|
||||
`define MUL_OPCTRL 3'b100
|
||||
`define SUB_OPCTRL 3'b111
|
||||
`define FADD_OPCTRL 3'b000
|
||||
`define DIV_OPCTRL 3'b000
|
||||
`define SQRT_OPCTRL 3'b001
|
||||
`define LE_OPCTRL 3'b011
|
||||
`define LT_OPCTRL 3'b001
|
||||
`define EQ_OPCTRL 3'b010
|
||||
`define TO_UI_OPCTRL 3'b011
|
||||
`define TO_I_OPCTRL 3'b001
|
||||
`define TO_UL_OPCTRL 3'b111
|
||||
`define TO_L_OPCTRL 3'b101
|
||||
`define FROM_UI_OPCTRL 3'b010
|
||||
`define FROM_I_OPCTRL 3'b000
|
||||
`define FROM_UL_OPCTRL 3'b110
|
||||
`define FROM_L_OPCTRL 3'b100
|
||||
`define RNE 3'b000
|
||||
`define RZ 3'b001
|
||||
`define RU 3'b011
|
||||
`define RD 3'b010
|
||||
`define RNM 3'b100
|
||||
`define FMAUNIT 0
|
||||
`define DIVUNIT 1
|
||||
`define CVTINTUNIT 2
|
||||
`define CVTFPUNIT 3
|
||||
`define CMPUNIT 4
|
||||
|
||||
string f16rv32cvtint[] = '{
|
||||
"f16_to_i32_rne.tv",
|
||||
"f16_to_i32_rz.tv",
|
||||
"f16_to_i32_ru.tv",
|
||||
"f16_to_i32_rd.tv",
|
||||
"f16_to_i32_rnm.tv",
|
||||
"f16_to_ui32_rne.tv",
|
||||
"f16_to_ui32_rz.tv",
|
||||
"f16_to_ui32_ru.tv",
|
||||
"f16_to_ui32_rd.tv",
|
||||
"f16_to_ui32_rnm.tv",
|
||||
"ui32_to_f16_rne.tv",
|
||||
"ui32_to_f16_rz.tv",
|
||||
"ui32_to_f16_ru.tv",
|
||||
"ui32_to_f16_rd.tv",
|
||||
"ui32_to_f16_rnm.tv",
|
||||
"i32_to_f16_rne.tv",
|
||||
"i32_to_f16_rz.tv",
|
||||
"i32_to_f16_ru.tv",
|
||||
"i32_to_f16_rd.tv",
|
||||
"i32_to_f16_rnm.tv"
|
||||
};
|
||||
|
||||
string f16rv64cvtint[] = '{
|
||||
"f16_to_ui64_rne.tv",
|
||||
"f16_to_ui64_rz.tv",
|
||||
"f16_to_ui64_ru.tv",
|
||||
"f16_to_ui64_rd.tv",
|
||||
"f16_to_ui64_rnm.tv",
|
||||
"f16_to_i64_rne.tv",
|
||||
"f16_to_i64_rz.tv",
|
||||
"f16_to_i64_ru.tv",
|
||||
"f16_to_i64_rd.tv",
|
||||
"f16_to_i64_rnm.tv",
|
||||
"ui64_to_f16_rne.tv",
|
||||
"ui64_to_f16_rz.tv",
|
||||
"ui64_to_f16_ru.tv",
|
||||
"ui64_to_f16_rd.tv",
|
||||
"ui64_to_f16_rnm.tv",
|
||||
"i64_to_f16_rne.tv",
|
||||
"i64_to_f16_rz.tv",
|
||||
"i64_to_f16_ru.tv",
|
||||
"i64_to_f16_rd.tv",
|
||||
"i64_to_f16_rnm.tv"
|
||||
};
|
||||
|
||||
string f32rv32cvtint[] = '{
|
||||
"ui32_to_f32_rne.tv",
|
||||
"ui32_to_f32_rz.tv",
|
||||
"ui32_to_f32_ru.tv",
|
||||
"ui32_to_f32_rd.tv",
|
||||
"ui32_to_f32_rnm.tv",
|
||||
"i32_to_f32_rne.tv",
|
||||
"i32_to_f32_rz.tv",
|
||||
"i32_to_f32_ru.tv",
|
||||
"i32_to_f32_rd.tv",
|
||||
"i32_to_f32_rnm.tv",
|
||||
"f32_to_ui32_rne.tv",
|
||||
"f32_to_ui32_rz.tv",
|
||||
"f32_to_ui32_ru.tv",
|
||||
"f32_to_ui32_rd.tv",
|
||||
"f32_to_ui32_rnm.tv",
|
||||
"f32_to_i32_rne.tv",
|
||||
"f32_to_i32_rz.tv",
|
||||
"f32_to_i32_ru.tv",
|
||||
"f32_to_i32_rd.tv",
|
||||
"f32_to_i32_rnm.tv"
|
||||
};
|
||||
|
||||
string f32rv64cvtint[] = '{
|
||||
"ui64_to_f32_rne.tv",
|
||||
"ui64_to_f32_rz.tv",
|
||||
"ui64_to_f32_ru.tv",
|
||||
"ui64_to_f32_rd.tv",
|
||||
"ui64_to_f32_rnm.tv",
|
||||
"i64_to_f32_rne.tv",
|
||||
"i64_to_f32_rz.tv",
|
||||
"i64_to_f32_ru.tv",
|
||||
"i64_to_f32_rd.tv",
|
||||
"i64_to_f32_rnm.tv",
|
||||
"f32_to_ui64_rne.tv",
|
||||
"f32_to_ui64_rz.tv",
|
||||
"f32_to_ui64_ru.tv",
|
||||
"f32_to_ui64_rd.tv",
|
||||
"f32_to_ui64_rnm.tv",
|
||||
"f32_to_i64_rne.tv",
|
||||
"f32_to_i64_rz.tv",
|
||||
"f32_to_i64_ru.tv",
|
||||
"f32_to_i64_rd.tv",
|
||||
"f32_to_i64_rnm.tv"
|
||||
};
|
||||
|
||||
|
||||
string f64rv32cvtint[] = '{
|
||||
"ui32_to_f64_rne.tv",
|
||||
"ui32_to_f64_rz.tv",
|
||||
"ui32_to_f64_ru.tv",
|
||||
"ui32_to_f64_rd.tv",
|
||||
"ui32_to_f64_rnm.tv",
|
||||
"i32_to_f64_rne.tv",
|
||||
"i32_to_f64_rz.tv",
|
||||
"i32_to_f64_ru.tv",
|
||||
"i32_to_f64_rd.tv",
|
||||
"i32_to_f64_rnm.tv",
|
||||
"f64_to_ui32_rne.tv",
|
||||
"f64_to_ui32_rz.tv",
|
||||
"f64_to_ui32_ru.tv",
|
||||
"f64_to_ui32_rd.tv",
|
||||
"f64_to_ui32_rnm.tv",
|
||||
"f64_to_i32_rne.tv",
|
||||
"f64_to_i32_rz.tv",
|
||||
"f64_to_i32_ru.tv",
|
||||
"f64_to_i32_rd.tv",
|
||||
"f64_to_i32_rnm.tv"
|
||||
};
|
||||
|
||||
string f64rv64cvtint[] = '{
|
||||
"ui64_to_f64_rne.tv",
|
||||
"ui64_to_f64_rz.tv",
|
||||
"ui64_to_f64_ru.tv",
|
||||
"ui64_to_f64_rd.tv",
|
||||
"ui64_to_f64_rnm.tv",
|
||||
"i64_to_f64_rne.tv",
|
||||
"i64_to_f64_rz.tv",
|
||||
"i64_to_f64_ru.tv",
|
||||
"i64_to_f64_rd.tv",
|
||||
"i64_to_f64_rnm.tv",
|
||||
"f64_to_ui64_rne.tv",
|
||||
"f64_to_ui64_rz.tv",
|
||||
"f64_to_ui64_ru.tv",
|
||||
"f64_to_ui64_rd.tv",
|
||||
"f64_to_ui64_rnm.tv",
|
||||
"f64_to_i64_rne.tv",
|
||||
"f64_to_i64_rz.tv",
|
||||
"f64_to_i64_ru.tv",
|
||||
"f64_to_i64_rd.tv",
|
||||
"f64_to_i64_rnm.tv"
|
||||
};
|
||||
|
||||
string f128rv64cvtint[] = '{
|
||||
"ui64_to_f128_rne.tv",
|
||||
"ui64_to_f128_rz.tv",
|
||||
"ui64_to_f128_ru.tv",
|
||||
"ui64_to_f128_rd.tv",
|
||||
"ui64_to_f128_rnm.tv",
|
||||
"i64_to_f128_rne.tv",
|
||||
"i64_to_f128_rz.tv",
|
||||
"i64_to_f128_ru.tv",
|
||||
"i64_to_f128_rd.tv",
|
||||
"i64_to_f128_rnm.tv",
|
||||
"f128_to_ui64_rne.tv",
|
||||
"f128_to_ui64_rz.tv",
|
||||
"f128_to_ui64_ru.tv",
|
||||
"f128_to_ui64_rd.tv",
|
||||
"f128_to_ui64_rnm.tv",
|
||||
"f128_to_i64_rne.tv",
|
||||
"f128_to_i64_rz.tv",
|
||||
"f128_to_i64_ru.tv",
|
||||
"f128_to_i64_rd.tv",
|
||||
"f128_to_i64_rnm.tv"
|
||||
};
|
||||
|
||||
string f128rv32cvtint[] = '{
|
||||
"ui32_to_f128_rne.tv",
|
||||
"ui32_to_f128_rz.tv",
|
||||
"ui32_to_f128_ru.tv",
|
||||
"ui32_to_f128_rd.tv",
|
||||
"ui32_to_f128_rnm.tv",
|
||||
"i32_to_f128_rne.tv",
|
||||
"i32_to_f128_rz.tv",
|
||||
"i32_to_f128_ru.tv",
|
||||
"i32_to_f128_rd.tv",
|
||||
"i32_to_f128_rnm.tv",
|
||||
"f128_to_ui32_rne.tv",
|
||||
"f128_to_ui32_rz.tv",
|
||||
"f128_to_ui32_ru.tv",
|
||||
"f128_to_ui32_rd.tv",
|
||||
"f128_to_ui32_rnm.tv",
|
||||
"f128_to_i32_rne.tv",
|
||||
"f128_to_i32_rz.tv",
|
||||
"f128_to_i32_ru.tv",
|
||||
"f128_to_i32_rd.tv",
|
||||
"f128_to_i32_rnm.tv"
|
||||
};
|
||||
|
||||
|
||||
string f32f16cvt[] = '{
|
||||
"f32_to_f16_rne.tv",
|
||||
"f32_to_f16_rz.tv",
|
||||
"f32_to_f16_ru.tv",
|
||||
"f32_to_f16_rd.tv",
|
||||
"f32_to_f16_rnm.tv",
|
||||
"f16_to_f32_rne.tv",
|
||||
"f16_to_f32_rz.tv",
|
||||
"f16_to_f32_ru.tv",
|
||||
"f16_to_f32_rd.tv",
|
||||
"f16_to_f32_rnm.tv"
|
||||
};
|
||||
|
||||
string f64f16cvt[] = '{
|
||||
"f64_to_f16_rne.tv",
|
||||
"f64_to_f16_rz.tv",
|
||||
"f64_to_f16_ru.tv",
|
||||
"f64_to_f16_rd.tv",
|
||||
"f64_to_f16_rnm.tv",
|
||||
"f16_to_f64_rne.tv",
|
||||
"f16_to_f64_rz.tv",
|
||||
"f16_to_f64_ru.tv",
|
||||
"f16_to_f64_rd.tv",
|
||||
"f16_to_f64_rnm.tv"
|
||||
};
|
||||
|
||||
string f128f16cvt[] = '{
|
||||
"f128_to_f16_rne.tv",
|
||||
"f128_to_f16_rz.tv",
|
||||
"f128_to_f16_ru.tv",
|
||||
"f128_to_f16_rd.tv",
|
||||
"f128_to_f16_rnm.tv",
|
||||
"f16_to_f128_rne.tv",
|
||||
"f16_to_f128_rz.tv",
|
||||
"f16_to_f128_ru.tv",
|
||||
"f16_to_f128_rd.tv",
|
||||
"f16_to_f128_rnm.tv"
|
||||
};
|
||||
|
||||
string f64f32cvt[] = '{
|
||||
"f64_to_f32_rne.tv",
|
||||
"f64_to_f32_rz.tv",
|
||||
"f64_to_f32_ru.tv",
|
||||
"f64_to_f32_rd.tv",
|
||||
"f64_to_f32_rnm.tv",
|
||||
"f32_to_f64_rne.tv",
|
||||
"f32_to_f64_rz.tv",
|
||||
"f32_to_f64_ru.tv",
|
||||
"f32_to_f64_rd.tv",
|
||||
"f32_to_f64_rnm.tv"
|
||||
};
|
||||
|
||||
|
||||
string f128f32cvt[] = '{
|
||||
"f128_to_f32_rne.tv",
|
||||
"f128_to_f32_rz.tv",
|
||||
"f128_to_f32_ru.tv",
|
||||
"f128_to_f32_rd.tv",
|
||||
"f128_to_f32_rnm.tv",
|
||||
"f32_to_f128_rne.tv",
|
||||
"f32_to_f128_rz.tv",
|
||||
"f32_to_f128_ru.tv",
|
||||
"f32_to_f128_rd.tv",
|
||||
"f32_to_f128_rnm.tv"
|
||||
};
|
||||
|
||||
|
||||
string f128f64cvt[] = '{
|
||||
"f64_to_f128_rne.tv",
|
||||
"f64_to_f128_rz.tv",
|
||||
"f64_to_f128_ru.tv",
|
||||
"f64_to_f128_rd.tv",
|
||||
"f64_to_f128_rnm.tv",
|
||||
"f128_to_f64_rne.tv",
|
||||
"f128_to_f64_rz.tv",
|
||||
"f128_to_f64_ru.tv",
|
||||
"f128_to_f64_rd.tv",
|
||||
"f128_to_f64_rnm.tv"
|
||||
};
|
||||
|
||||
string f16add[] = '{
|
||||
"f16_add_rne.tv",
|
||||
"f16_add_rz.tv",
|
||||
"f16_add_ru.tv",
|
||||
"f16_add_rd.tv",
|
||||
"f16_add_rnm.tv"
|
||||
};
|
||||
|
||||
string f32add[] = '{
|
||||
"f32_add_rne.tv",
|
||||
"f32_add_rz.tv",
|
||||
"f32_add_ru.tv",
|
||||
"f32_add_rd.tv",
|
||||
"f32_add_rnm.tv"
|
||||
};
|
||||
|
||||
string f64add[] = '{
|
||||
"f64_add_rne.tv",
|
||||
"f64_add_rz.tv",
|
||||
"f64_add_ru.tv",
|
||||
"f64_add_rd.tv",
|
||||
"f64_add_rnm.tv"
|
||||
};
|
||||
|
||||
string f128add[] = '{
|
||||
"f128_add_rne.tv",
|
||||
"f128_add_rz.tv",
|
||||
"f128_add_ru.tv",
|
||||
"f128_add_rd.tv",
|
||||
"f128_add_rnm.tv"
|
||||
};
|
||||
|
||||
string f16sub[] = '{
|
||||
"f16_sub_rne.tv",
|
||||
"f16_sub_rz.tv",
|
||||
"f16_sub_ru.tv",
|
||||
"f16_sub_rd.tv",
|
||||
"f16_sub_rnm.tv"
|
||||
};
|
||||
|
||||
string f32sub[] = '{
|
||||
"f32_sub_rne.tv",
|
||||
"f32_sub_rz.tv",
|
||||
"f32_sub_ru.tv",
|
||||
"f32_sub_rd.tv",
|
||||
"f32_sub_rnm.tv"
|
||||
};
|
||||
|
||||
string f64sub[] = '{
|
||||
"f64_sub_rne.tv",
|
||||
"f64_sub_rz.tv",
|
||||
"f64_sub_ru.tv",
|
||||
"f64_sub_rd.tv",
|
||||
"f64_sub_rnm.tv"
|
||||
};
|
||||
|
||||
string f128sub[] = '{
|
||||
"f128_sub_rne.tv",
|
||||
"f128_sub_rz.tv",
|
||||
"f128_sub_ru.tv",
|
||||
"f128_sub_rd.tv",
|
||||
"f128_sub_rnm.tv"
|
||||
};
|
||||
|
||||
string f16mul[] = '{
|
||||
"f16_mul_rne.tv",
|
||||
"f16_mul_rz.tv",
|
||||
"f16_mul_ru.tv",
|
||||
"f16_mul_rd.tv",
|
||||
"f16_mul_rnm.tv"
|
||||
};
|
||||
|
||||
string f32mul[] = '{
|
||||
"f32_mul_rne.tv",
|
||||
"f32_mul_rz.tv",
|
||||
"f32_mul_ru.tv",
|
||||
"f32_mul_rd.tv",
|
||||
"f32_mul_rnm.tv"
|
||||
};
|
||||
|
||||
string f64mul[] = '{
|
||||
"f64_mul_rne.tv",
|
||||
"f64_mul_rz.tv",
|
||||
"f64_mul_ru.tv",
|
||||
"f64_mul_rd.tv",
|
||||
"f64_mul_rnm.tv"
|
||||
};
|
||||
|
||||
string f128mul[] = '{
|
||||
"f128_mul_rne.tv",
|
||||
"f128_mul_rz.tv",
|
||||
"f128_mul_ru.tv",
|
||||
"f128_mul_rd.tv",
|
||||
"f128_mul_rnm.tv"
|
||||
};
|
||||
|
||||
string f16div[] = '{
|
||||
"f16_div_rne.tv",
|
||||
"f16_div_rz.tv",
|
||||
"f16_div_ru.tv",
|
||||
"f16_div_rd.tv",
|
||||
"f16_div_rnm.tv"
|
||||
};
|
||||
|
||||
string f32div[] = '{
|
||||
"f32_div_rne.tv",
|
||||
"f32_div_rz.tv",
|
||||
"f32_div_ru.tv",
|
||||
"f32_div_rd.tv",
|
||||
"f32_div_rnm.tv"
|
||||
};
|
||||
|
||||
string f64div[] = '{
|
||||
"f64_div_rne.tv",
|
||||
"f64_div_rz.tv",
|
||||
"f64_div_ru.tv",
|
||||
"f64_div_rd.tv",
|
||||
"f64_div_rnm.tv"
|
||||
};
|
||||
|
||||
string f128div[] = '{
|
||||
"f128_div_rne.tv",
|
||||
"f128_div_rz.tv",
|
||||
"f128_div_ru.tv",
|
||||
"f128_div_rd.tv",
|
||||
"f128_div_rnm.tv"
|
||||
};
|
||||
|
||||
string f16sqrt[] = '{
|
||||
"f16_sqrt_rne.tv",
|
||||
"f16_sqrt_rz.tv",
|
||||
"f16_sqrt_ru.tv",
|
||||
"f16_sqrt_rd.tv",
|
||||
"f16_sqrt_rnm.tv"
|
||||
};
|
||||
|
||||
string f32sqrt[] = '{
|
||||
"f32_sqrt_rne.tv",
|
||||
"f32_sqrt_rz.tv",
|
||||
"f32_sqrt_ru.tv",
|
||||
"f32_sqrt_rd.tv",
|
||||
"f32_sqrt_rnm.tv"
|
||||
};
|
||||
|
||||
string f64sqrt[] = '{
|
||||
"f64_sqrt_rne.tv",
|
||||
"f64_sqrt_rz.tv",
|
||||
"f64_sqrt_ru.tv",
|
||||
"f64_sqrt_rd.tv",
|
||||
"f64_sqrt_rnm.tv"
|
||||
};
|
||||
|
||||
string f128sqrt[] = '{
|
||||
"f128_sqrt_rne.tv",
|
||||
"f128_sqrt_rz.tv",
|
||||
"f128_sqrt_ru.tv",
|
||||
"f128_sqrt_rd.tv",
|
||||
"f128_sqrt_rnm.tv"
|
||||
};
|
||||
|
||||
string f16cmp[] = '{
|
||||
"f16_eq_rne.tv",
|
||||
"f16_eq_rz.tv",
|
||||
"f16_eq_ru.tv",
|
||||
"f16_eq_rd.tv",
|
||||
"f16_eq_rnm.tv",
|
||||
"f16_le_rne.tv",
|
||||
"f16_le_rz.tv",
|
||||
"f16_le_ru.tv",
|
||||
"f16_le_rd.tv",
|
||||
"f16_le_rnm.tv",
|
||||
"f16_lt_rne.tv",
|
||||
"f16_lt_rz.tv",
|
||||
"f16_lt_ru.tv",
|
||||
"f16_lt_rd.tv",
|
||||
"f16_lt_rnm.tv"
|
||||
};
|
||||
|
||||
string f32cmp[] = '{
|
||||
"f32_eq_rne.tv",
|
||||
"f32_eq_rz.tv",
|
||||
"f32_eq_ru.tv",
|
||||
"f32_eq_rd.tv",
|
||||
"f32_eq_rnm.tv",
|
||||
"f32_le_rne.tv",
|
||||
"f32_le_rz.tv",
|
||||
"f32_le_ru.tv",
|
||||
"f32_le_rd.tv",
|
||||
"f32_le_rnm.tv",
|
||||
"f32_lt_rne.tv",
|
||||
"f32_lt_rz.tv",
|
||||
"f32_lt_ru.tv",
|
||||
"f32_lt_rd.tv",
|
||||
"f32_lt_rnm.tv"
|
||||
};
|
||||
|
||||
string f64cmp[] = '{
|
||||
"f64_eq_rne.tv",
|
||||
"f64_eq_rz.tv",
|
||||
"f64_eq_ru.tv",
|
||||
"f64_eq_rd.tv",
|
||||
"f64_eq_rnm.tv",
|
||||
"f64_le_rne.tv",
|
||||
"f64_le_rz.tv",
|
||||
"f64_le_ru.tv",
|
||||
"f64_le_rd.tv",
|
||||
"f64_le_rnm.tv",
|
||||
"f64_lt_rne.tv",
|
||||
"f64_lt_rz.tv",
|
||||
"f64_lt_ru.tv",
|
||||
"f64_lt_rd.tv",
|
||||
"f64_lt_rnm.tv"
|
||||
};
|
||||
|
||||
string f128cmp[] = '{
|
||||
"f128_eq_rne.tv",
|
||||
"f128_eq_rz.tv",
|
||||
"f128_eq_ru.tv",
|
||||
"f128_eq_rd.tv",
|
||||
"f128_eq_rnm.tv",
|
||||
"f128_le_rne.tv",
|
||||
"f128_le_rz.tv",
|
||||
"f128_le_ru.tv",
|
||||
"f128_le_rd.tv",
|
||||
"f128_le_rnm.tv",
|
||||
"f128_lt_rne.tv",
|
||||
"f128_lt_rz.tv",
|
||||
"f128_lt_ru.tv",
|
||||
"f128_lt_rd.tv",
|
||||
"f128_lt_rnm.tv"
|
||||
};
|
||||
|
||||
string f16fma[] = '{
|
||||
"f16_mulAdd_rne.tv",
|
||||
"f16_mulAdd_rz.tv",
|
||||
"f16_mulAdd_ru.tv",
|
||||
"f16_mulAdd_rd.tv",
|
||||
"f16_mulAdd_rnm.tv"
|
||||
};
|
||||
|
||||
string f32fma[] = '{
|
||||
"f32_mulAdd_rne.tv",
|
||||
"f32_mulAdd_rz.tv",
|
||||
"f32_mulAdd_ru.tv",
|
||||
"f32_mulAdd_rd.tv",
|
||||
"f32_mulAdd_rnm.tv"
|
||||
};
|
||||
|
||||
string f64fma[] = '{
|
||||
"f64_mulAdd_rne.tv",
|
||||
"f64_mulAdd_rz.tv",
|
||||
"f64_mulAdd_ru.tv",
|
||||
"f64_mulAdd_rd.tv",
|
||||
"f64_mulAdd_rnm.tv"
|
||||
};
|
||||
|
||||
string f128fma[] = '{
|
||||
"f128_mulAdd_rne.tv",
|
||||
"f128_mulAdd_rz.tv",
|
||||
"f128_mulAdd_ru.tv",
|
||||
"f128_mulAdd_rd.tv",
|
||||
"f128_mulAdd_rnm.tv"
|
||||
};
|
||||
|
||||
|
||||
|
@ -962,7 +962,7 @@ string imperas32f[] = '{
|
||||
"rv64i_m/I/andi-01", "6010",
|
||||
"rv64i_m/I/auipc-01", "2010",
|
||||
"rv64i_m/I/beq-01", "47010",
|
||||
"rv64i_m/I/bge-01", "46010",
|
||||
"rv64i_m/I/bge-01", "47010",
|
||||
"rv64i_m/I/bgeu-01", "56010",
|
||||
"rv64i_m/I/blt-01", "4d010",
|
||||
"rv64i_m/I/bltu-01", "57010",
|
||||
|
17
synthDC/Synopsys_stack_trace_12580.txt
Normal file
17
synthDC/Synopsys_stack_trace_12580.txt
Normal file
@ -0,0 +1,17 @@
|
||||
GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
|
||||
This is free software: you are free to change and redistribute it.
|
||||
There is NO WARRANTY, to the extent permitted by law.
|
||||
Type "show copying" and "show warranty" for details.
|
||||
This GDB was configured as "x86_64-redhat-linux-gnu".
|
||||
Type "show configuration" for configuration details.
|
||||
For bug reporting instructions, please see:
|
||||
<http://www.gnu.org/software/gdb/bugs/>.
|
||||
Find the GDB manual and other documentation resources online at:
|
||||
<http://www.gnu.org/software/gdb/documentation/>.
|
||||
|
||||
For help, type "help".
|
||||
Type "apropos word" to search for commands related to "word".
|
||||
Attaching to process 12580
|
||||
(gdb) (gdb) (gdb) (gdb)
|
17
synthDC/Synopsys_stack_trace_32764.txt
Normal file
17
synthDC/Synopsys_stack_trace_32764.txt
Normal file
@ -0,0 +1,17 @@
|
||||
GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
|
||||
This is free software: you are free to change and redistribute it.
|
||||
There is NO WARRANTY, to the extent permitted by law.
|
||||
Type "show copying" and "show warranty" for details.
|
||||
This GDB was configured as "x86_64-redhat-linux-gnu".
|
||||
Type "show configuration" for configuration details.
|
||||
For bug reporting instructions, please see:
|
||||
<http://www.gnu.org/software/gdb/bugs/>.
|
||||
Find the GDB manual and other documentation resources online at:
|
||||
<http://www.gnu.org/software/gdb/documentation/>.
|
||||
|
||||
For help, type "help".
|
||||
Type "apropos word" to search for commands related to "word".
|
||||
Attaching to process 32764
|
||||
(gdb) (gdb) (gdb) (gdb)
|
17
synthDC/Synopsys_stack_trace_52064.txt
Normal file
17
synthDC/Synopsys_stack_trace_52064.txt
Normal file
@ -0,0 +1,17 @@
|
||||
GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
|
||||
This is free software: you are free to change and redistribute it.
|
||||
There is NO WARRANTY, to the extent permitted by law.
|
||||
Type "show copying" and "show warranty" for details.
|
||||
This GDB was configured as "x86_64-redhat-linux-gnu".
|
||||
Type "show configuration" for configuration details.
|
||||
For bug reporting instructions, please see:
|
||||
<http://www.gnu.org/software/gdb/bugs/>.
|
||||
Find the GDB manual and other documentation resources online at:
|
||||
<http://www.gnu.org/software/gdb/documentation/>.
|
||||
|
||||
For help, type "help".
|
||||
Type "apropos word" to search for commands related to "word".
|
||||
Attaching to process 52064
|
||||
(gdb) (gdb) (gdb) (gdb)
|
17
synthDC/Synopsys_stack_trace_55441.txt
Normal file
17
synthDC/Synopsys_stack_trace_55441.txt
Normal file
@ -0,0 +1,17 @@
|
||||
GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
|
||||
This is free software: you are free to change and redistribute it.
|
||||
There is NO WARRANTY, to the extent permitted by law.
|
||||
Type "show copying" and "show warranty" for details.
|
||||
This GDB was configured as "x86_64-redhat-linux-gnu".
|
||||
Type "show configuration" for configuration details.
|
||||
For bug reporting instructions, please see:
|
||||
<http://www.gnu.org/software/gdb/bugs/>.
|
||||
Find the GDB manual and other documentation resources online at:
|
||||
<http://www.gnu.org/software/gdb/documentation/>.
|
||||
|
||||
For help, type "help".
|
||||
Type "apropos word" to search for commands related to "word".
|
||||
Attaching to process 55441
|
||||
(gdb) (gdb) (gdb) (gdb)
|
17
synthDC/Synopsys_stack_trace_57184.txt
Normal file
17
synthDC/Synopsys_stack_trace_57184.txt
Normal file
@ -0,0 +1,17 @@
|
||||
GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
|
||||
This is free software: you are free to change and redistribute it.
|
||||
There is NO WARRANTY, to the extent permitted by law.
|
||||
Type "show copying" and "show warranty" for details.
|
||||
This GDB was configured as "x86_64-redhat-linux-gnu".
|
||||
Type "show configuration" for configuration details.
|
||||
For bug reporting instructions, please see:
|
||||
<http://www.gnu.org/software/gdb/bugs/>.
|
||||
Find the GDB manual and other documentation resources online at:
|
||||
<http://www.gnu.org/software/gdb/documentation/>.
|
||||
|
||||
For help, type "help".
|
||||
Type "apropos word" to search for commands related to "word".
|
||||
Attaching to process 57184
|
||||
(gdb) (gdb) (gdb) (gdb)
|
17
synthDC/Synopsys_stack_trace_57185.txt
Normal file
17
synthDC/Synopsys_stack_trace_57185.txt
Normal file
@ -0,0 +1,17 @@
|
||||
GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
|
||||
This is free software: you are free to change and redistribute it.
|
||||
There is NO WARRANTY, to the extent permitted by law.
|
||||
Type "show copying" and "show warranty" for details.
|
||||
This GDB was configured as "x86_64-redhat-linux-gnu".
|
||||
Type "show configuration" for configuration details.
|
||||
For bug reporting instructions, please see:
|
||||
<http://www.gnu.org/software/gdb/bugs/>.
|
||||
Find the GDB manual and other documentation resources online at:
|
||||
<http://www.gnu.org/software/gdb/documentation/>.
|
||||
|
||||
For help, type "help".
|
||||
Type "apropos word" to search for commands related to "word".
|
||||
Attaching to process 57185
|
||||
(gdb) (gdb) (gdb) (gdb)
|
67
synthDC/crte_000012580.txt
Normal file
67
synthDC/crte_000012580.txt
Normal file
@ -0,0 +1,67 @@
|
||||
CRTE_SNAPSHOT_START
|
||||
|
||||
SECTION_CRTE_VERSION
|
||||
3.0
|
||||
|
||||
SECTION_PID
|
||||
12580
|
||||
|
||||
SECTION_POLLING_INTERVAL
|
||||
5
|
||||
|
||||
SECTION_DATE_TIME
|
||||
Mon May 16 23:44:09 UTC 2022 (1652744649)
|
||||
|
||||
SECTION_OS_VERSION
|
||||
osname: Linux
|
||||
hostname: tera
|
||||
arch: x86_64
|
||||
release_version: 5.4.157-1-pve
|
||||
|
||||
SECTION_IPC_INFO
|
||||
|
||||
------ Message Queues --------
|
||||
key msqid owner perms used-bytes messages
|
||||
|
||||
------ Shared Memory Segments --------
|
||||
key shmid owner perms bytes nattch status
|
||||
0x00000000 15859713 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 360451 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 65540 kkim 600 134217728 2 dest
|
||||
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
|
||||
0x00000000 6 harris 600 524288 2 dest
|
||||
0x00000000 7 harris 600 524288 2 dest
|
||||
0x00000000 5275656 harris 600 2097152 2 dest
|
||||
0x00000000 11993097 kkim 600 524288 2 dest
|
||||
0x00000000 15892490 kkim 600 524288 2 dest
|
||||
0x00000000 11 harris 600 524288 2 SECTION_ULIMIT
|
||||
core file size (blocks, -c) 0
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 515072
|
||||
max locked memory (kbytes, -l) 64
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 524288
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) unlimited
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 515072
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
|
||||
SECTION_SYSCONF
|
||||
_SC_THREAD_SAFE_FUNCTIONS= 200809
|
||||
_SC_CLK_TCK= 100
|
||||
_SC_OPEN_MAX= 524288
|
||||
_SC_PAGE_SIZE= 4096
|
||||
_SC_ARG_MAX= 4611686018427387903
|
||||
_SC_CHILD_MAX= 515072
|
||||
_SC_LINE_MAX= 2048
|
||||
|
||||
SECTION_FULL_COMMAND
|
||||
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
|
||||
|
||||
SECTION_CPUINFO
|
67
synthDC/crte_000032764.txt
Normal file
67
synthDC/crte_000032764.txt
Normal file
@ -0,0 +1,67 @@
|
||||
CRTE_SNAPSHOT_START
|
||||
|
||||
SECTION_CRTE_VERSION
|
||||
3.0
|
||||
|
||||
SECTION_PID
|
||||
32764
|
||||
|
||||
SECTION_POLLING_INTERVAL
|
||||
5
|
||||
|
||||
SECTION_DATE_TIME
|
||||
Tue May 17 00:05:18 UTC 2022 (1652745918)
|
||||
|
||||
SECTION_OS_VERSION
|
||||
osname: Linux
|
||||
hostname: tera
|
||||
arch: x86_64
|
||||
release_version: 5.4.157-1-pve
|
||||
|
||||
SECTION_IPC_INFO
|
||||
|
||||
------ Message Queues --------
|
||||
key msqid owner perms used-bytes messages
|
||||
|
||||
------ Shared Memory Segments --------
|
||||
key shmid owner perms bytes nattch status
|
||||
0x00000000 360451 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 65540 kkim 600 134217728 2 dest
|
||||
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
|
||||
0x00000000 6 harris 600 524288 2 dest
|
||||
0x00000000 7 harris 600 524288 2 dest
|
||||
0x00000000 5275656 harris 600 2097152 2 dest
|
||||
0x00000000 11993097 kkim 600 524288 2 dest
|
||||
0x00000000 15892490 kkim 600 524288 2 dest
|
||||
0x00000000 11 harris 600 524288 2 dest
|
||||
0x00000000 15204364 harris 644 790528 3 SECTION_ULIMIT
|
||||
core file size (blocks, -c) 0
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 515072
|
||||
max locked memory (kbytes, -l) 64
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 524288
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) unlimited
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 515072
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
|
||||
SECTION_SYSCONF
|
||||
_SC_THREAD_SAFE_FUNCTIONS= 200809
|
||||
_SC_CLK_TCK= 100
|
||||
_SC_OPEN_MAX= 524288
|
||||
_SC_PAGE_SIZE= 4096
|
||||
_SC_ARG_MAX= 4611686018427387903
|
||||
_SC_CHILD_MAX= 515072
|
||||
_SC_LINE_MAX= 2048
|
||||
|
||||
SECTION_FULL_COMMAND
|
||||
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
|
||||
|
||||
SECTION_CPUINFO
|
67
synthDC/crte_000052064.txt
Normal file
67
synthDC/crte_000052064.txt
Normal file
@ -0,0 +1,67 @@
|
||||
CRTE_SNAPSHOT_START
|
||||
|
||||
SECTION_CRTE_VERSION
|
||||
3.0
|
||||
|
||||
SECTION_PID
|
||||
52064
|
||||
|
||||
SECTION_POLLING_INTERVAL
|
||||
5
|
||||
|
||||
SECTION_DATE_TIME
|
||||
Thu May 12 21:44:48 UTC 2022 (1652391888)
|
||||
|
||||
SECTION_OS_VERSION
|
||||
osname: Linux
|
||||
hostname: tera
|
||||
arch: x86_64
|
||||
release_version: 5.4.157-1-pve
|
||||
|
||||
SECTION_IPC_INFO
|
||||
|
||||
------ Message Queues --------
|
||||
key msqid owner perms used-bytes messages
|
||||
|
||||
------ Shared Memory Segments --------
|
||||
key shmid owner perms bytes nattch status
|
||||
0x00000000 360451 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 65540 kkim 600 134217728 2 dest
|
||||
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
|
||||
0x00000000 6 harris 600 524288 2 dest
|
||||
0x00000000 7 harris 600 524288 2 dest
|
||||
0x00000000 5275656 harris 600 2097152 2 dest
|
||||
0x00000000 11993097 kkim 600 524288 2 dest
|
||||
0x00000000 11 harris 600 524288 2 dest
|
||||
0x00000000 15204364 harris 644 790528 2 dest
|
||||
0x00000000 7372813 chuang 600 524288 2 SECTION_ULIMIT
|
||||
core file size (blocks, -c) 0
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 515072
|
||||
max locked memory (kbytes, -l) 64
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 524288
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) unlimited
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 515072
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
|
||||
SECTION_SYSCONF
|
||||
_SC_THREAD_SAFE_FUNCTIONS= 200809
|
||||
_SC_CLK_TCK= 100
|
||||
_SC_OPEN_MAX= 524288
|
||||
_SC_PAGE_SIZE= 4096
|
||||
_SC_ARG_MAX= 4611686018427387903
|
||||
_SC_CHILD_MAX= 515072
|
||||
_SC_LINE_MAX= 2048
|
||||
|
||||
SECTION_FULL_COMMAND
|
||||
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
|
||||
|
||||
SECTION_CPUINFO
|
67
synthDC/crte_000055441.txt
Normal file
67
synthDC/crte_000055441.txt
Normal file
@ -0,0 +1,67 @@
|
||||
CRTE_SNAPSHOT_START
|
||||
|
||||
SECTION_CRTE_VERSION
|
||||
3.0
|
||||
|
||||
SECTION_PID
|
||||
55441
|
||||
|
||||
SECTION_POLLING_INTERVAL
|
||||
5
|
||||
|
||||
SECTION_DATE_TIME
|
||||
Thu May 12 21:47:47 UTC 2022 (1652392067)
|
||||
|
||||
SECTION_OS_VERSION
|
||||
osname: Linux
|
||||
hostname: tera
|
||||
arch: x86_64
|
||||
release_version: 5.4.157-1-pve
|
||||
|
||||
SECTION_IPC_INFO
|
||||
|
||||
------ Message Queues --------
|
||||
key msqid owner perms used-bytes messages
|
||||
|
||||
------ Shared Memory Segments --------
|
||||
key shmid owner perms bytes nattch status
|
||||
0x00000000 360451 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 65540 kkim 600 134217728 2 dest
|
||||
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
|
||||
0x00000000 6 harris 600 524288 2 dest
|
||||
0x00000000 7 harris 600 524288 2 dest
|
||||
0x00000000 5275656 harris 600 2097152 2 dest
|
||||
0x00000000 11993097 kkim 600 524288 2 dest
|
||||
0x00000000 11 harris 600 524288 2 dest
|
||||
0x00000000 15204364 harris 644 790528 2 dest
|
||||
0x00000000 7372813 chuang 600 524288 2 SECTION_ULIMIT
|
||||
core file size (blocks, -c) 0
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 515072
|
||||
max locked memory (kbytes, -l) 64
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 524288
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) unlimited
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 515072
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
|
||||
SECTION_SYSCONF
|
||||
_SC_THREAD_SAFE_FUNCTIONS= 200809
|
||||
_SC_CLK_TCK= 100
|
||||
_SC_OPEN_MAX= 524288
|
||||
_SC_PAGE_SIZE= 4096
|
||||
_SC_ARG_MAX= 4611686018427387903
|
||||
_SC_CHILD_MAX= 515072
|
||||
_SC_LINE_MAX= 2048
|
||||
|
||||
SECTION_FULL_COMMAND
|
||||
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
|
||||
|
||||
SECTION_CPUINFO
|
67
synthDC/crte_000057184.txt
Normal file
67
synthDC/crte_000057184.txt
Normal file
@ -0,0 +1,67 @@
|
||||
CRTE_SNAPSHOT_START
|
||||
|
||||
SECTION_CRTE_VERSION
|
||||
3.0
|
||||
|
||||
SECTION_PID
|
||||
57184
|
||||
|
||||
SECTION_POLLING_INTERVAL
|
||||
5
|
||||
|
||||
SECTION_DATE_TIME
|
||||
Mon May 16 22:54:26 UTC 2022 (1652741666)
|
||||
|
||||
SECTION_OS_VERSION
|
||||
osname: Linux
|
||||
hostname: tera
|
||||
arch: x86_64
|
||||
release_version: 5.4.157-1-pve
|
||||
|
||||
SECTION_IPC_INFO
|
||||
|
||||
------ Message Queues --------
|
||||
key msqid owner perms used-bytes messages
|
||||
|
||||
------ Shared Memory Segments --------
|
||||
key shmid owner perms bytes nattch status
|
||||
0x00000000 15859713 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 360451 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 65540 kkim 600 134217728 2 dest
|
||||
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
|
||||
0x00000000 6 harris 600 524288 2 dest
|
||||
0x00000000 7 harris 600 524288 2 dest
|
||||
0x00000000 5275656 harris 600 2097152 2 dest
|
||||
0x00000000 11993097 kkim 600 524288 2 dest
|
||||
0x00000000 15892490 kkim 600 524288 2 dest
|
||||
0x00000000 11 harris 600 524288 2 SECTION_ULIMIT
|
||||
core file size (blocks, -c) 0
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 515072
|
||||
max locked memory (kbytes, -l) 64
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 524288
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) unlimited
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 515072
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
|
||||
SECTION_SYSCONF
|
||||
_SC_THREAD_SAFE_FUNCTIONS= 200809
|
||||
_SC_CLK_TCK= 100
|
||||
_SC_OPEN_MAX= 524288
|
||||
_SC_PAGE_SIZE= 4096
|
||||
_SC_ARG_MAX= 4611686018427387903
|
||||
_SC_CHILD_MAX= 515072
|
||||
_SC_LINE_MAX= 2048
|
||||
|
||||
SECTION_FULL_COMMAND
|
||||
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
|
||||
|
||||
SECTION_CPUINFO
|
67
synthDC/crte_000057185.txt
Normal file
67
synthDC/crte_000057185.txt
Normal file
@ -0,0 +1,67 @@
|
||||
CRTE_SNAPSHOT_START
|
||||
|
||||
SECTION_CRTE_VERSION
|
||||
3.0
|
||||
|
||||
SECTION_PID
|
||||
57185
|
||||
|
||||
SECTION_POLLING_INTERVAL
|
||||
5
|
||||
|
||||
SECTION_DATE_TIME
|
||||
Mon May 16 22:54:26 UTC 2022 (1652741666)
|
||||
|
||||
SECTION_OS_VERSION
|
||||
osname: Linux
|
||||
hostname: tera
|
||||
arch: x86_64
|
||||
release_version: 5.4.157-1-pve
|
||||
|
||||
SECTION_IPC_INFO
|
||||
|
||||
------ Message Queues --------
|
||||
key msqid owner perms used-bytes messages
|
||||
|
||||
------ Shared Memory Segments --------
|
||||
key shmid owner perms bytes nattch status
|
||||
0x00000000 15859713 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 360451 nwhyte-agu 600 524288 2 dest
|
||||
0x00000000 65540 kkim 600 134217728 2 dest
|
||||
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
|
||||
0x00000000 6 harris 600 524288 2 dest
|
||||
0x00000000 7 harris 600 524288 2 dest
|
||||
0x00000000 5275656 harris 600 2097152 2 dest
|
||||
0x00000000 11993097 kkim 600 524288 2 dest
|
||||
0x00000000 15892490 kkim 600 524288 2 dest
|
||||
0x00000000 11 harris 600 524288 2 SECTION_ULIMIT
|
||||
core file size (blocks, -c) 0
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 515072
|
||||
max locked memory (kbytes, -l) 64
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 524288
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) unlimited
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 515072
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
|
||||
SECTION_SYSCONF
|
||||
_SC_THREAD_SAFE_FUNCTIONS= 200809
|
||||
_SC_CLK_TCK= 100
|
||||
_SC_OPEN_MAX= 524288
|
||||
_SC_PAGE_SIZE= 4096
|
||||
_SC_ARG_MAX= 4611686018427387903
|
||||
_SC_CHILD_MAX= 515072
|
||||
_SC_LINE_MAX= 2048
|
||||
|
||||
SECTION_FULL_COMMAND
|
||||
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
|
||||
|
||||
SECTION_CPUINFO
|
@ -1,61 +0,0 @@
|
||||
#!/usr/bin/python3
|
||||
# from msilib.schema import File
|
||||
import subprocess
|
||||
from multiprocessing import Pool
|
||||
import csv
|
||||
import re
|
||||
import matplotlib.pyplot as plt
|
||||
import numpy as np
|
||||
|
||||
|
||||
def run_command(module, width, freq):
|
||||
command = "make synth DESIGN=ppa_{}_{} TECH=sky90 DRIVE=INV FREQ={} MAXOPT=1".format(module, width, freq)
|
||||
subprocess.Popen(command, shell=True)
|
||||
|
||||
widths = ['32']
|
||||
modules = ['shifter']
|
||||
freqs = ['10', '4000', '5000', '6000']
|
||||
|
||||
LoT = []
|
||||
for module in modules:
|
||||
for width in widths:
|
||||
for freq in freqs:
|
||||
LoT += [[module, width, freq]]
|
||||
|
||||
pool = Pool()
|
||||
pool.starmap(run_command, LoT)
|
||||
|
||||
bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*"
|
||||
outputCPL = subprocess.check_output(['bash','-c', bashCommand])
|
||||
linesCPL = outputCPL.decode("utf-8").split('\n')[:-1]
|
||||
|
||||
bashCommand = "grep 'Design Area' runs/ppa_*/reports/*qor*"
|
||||
outputDA = subprocess.check_output(['bash','-c', bashCommand])
|
||||
linesDA = outputDA.decode("utf-8").split('\n')[:-1]
|
||||
|
||||
cpl = re.compile('\d{1}\.\d{6}')
|
||||
f = re.compile('_\d*_MHz')
|
||||
wm = re.compile('ppa_\w*_\d*_qor')
|
||||
da = re.compile('\d*\.\d{6}')
|
||||
|
||||
allSynths = []
|
||||
|
||||
for i in range(len(linesCPL)):
|
||||
line = linesCPL[i]
|
||||
oneSynth = []
|
||||
mwm = wm.findall(line)[0][4:-4].split('_')
|
||||
oneSynth += [mwm[0]]
|
||||
oneSynth += [mwm[1]]
|
||||
oneSynth += [f.findall(line)[0][1:-4]]
|
||||
oneSynth += cpl.findall(line)
|
||||
oneSynth += da.findall(linesDA[i])
|
||||
allSynths += [oneSynth]
|
||||
|
||||
file = open("ppaData.csv", "w")
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area'])
|
||||
|
||||
for one in allSynths:
|
||||
writer.writerow(one)
|
||||
|
||||
file.close()
|
297
synthDC/ppaAnalyze.py
Executable file
297
synthDC/ppaAnalyze.py
Executable file
@ -0,0 +1,297 @@
|
||||
#!/usr/bin/python3
|
||||
# Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22
|
||||
|
||||
from distutils.log import error
|
||||
from statistics import median
|
||||
import subprocess
|
||||
import statistics
|
||||
import csv
|
||||
import re
|
||||
import matplotlib.pyplot as plt
|
||||
import matplotlib.lines as lines
|
||||
import numpy as np
|
||||
|
||||
|
||||
def getData(mod=None, width=None):
|
||||
specStr = ''
|
||||
if mod != None:
|
||||
specStr = mod
|
||||
if width != None:
|
||||
specStr += ('_'+str(width))
|
||||
specStr += '*'
|
||||
|
||||
bashCommand = "grep 'Critical Path Length' runs/ppa_{}/reports/*qor*".format(specStr)
|
||||
outputCPL = subprocess.check_output(['bash','-c', bashCommand])
|
||||
linesCPL = outputCPL.decode("utf-8").split('\n')[:-1]
|
||||
|
||||
bashCommand = "grep 'Design Area' runs/ppa_{}/reports/*qor*".format(specStr)
|
||||
outputDA = subprocess.check_output(['bash','-c', bashCommand])
|
||||
linesDA = outputDA.decode("utf-8").split('\n')[:-1]
|
||||
|
||||
bashCommand = "grep '100' runs/ppa_{}/reports/*power*".format(specStr)
|
||||
outputP = subprocess.check_output(['bash','-c', bashCommand])
|
||||
linesP = outputP.decode("utf-8").split('\n')[:-1]
|
||||
|
||||
cpl = re.compile('\d{1}\.\d{6}')
|
||||
f = re.compile('_\d*_MHz')
|
||||
wm = re.compile('ppa_\w*_\d*_qor')
|
||||
da = re.compile('\d*\.\d{6}')
|
||||
p = re.compile('\d+\.\d+[e-]*\d+')
|
||||
|
||||
allSynths = []
|
||||
for i in range(len(linesCPL)):
|
||||
line = linesCPL[i]
|
||||
mwm = wm.findall(line)[0][4:-4].split('_')
|
||||
freq = int(f.findall(line)[0][1:-4])
|
||||
delay = float(cpl.findall(line)[0])
|
||||
area = float(da.findall(linesDA[i])[0])
|
||||
mod = mwm[0]
|
||||
width = int(mwm[1])
|
||||
|
||||
power = p.findall(linesP[i])
|
||||
lpower = float(power[2])
|
||||
denergy = float(power[1])*delay
|
||||
|
||||
oneSynth = [mod, width, freq, delay, area, lpower, denergy]
|
||||
allSynths += [oneSynth]
|
||||
|
||||
return allSynths
|
||||
|
||||
def getVals(module, var, freq=None):
|
||||
allSynths = getData(mod=module)
|
||||
|
||||
if (var == 'delay'):
|
||||
ind = 3
|
||||
units = " (ns)"
|
||||
elif (var == 'area'):
|
||||
ind = 4
|
||||
units = " (sq microns)"
|
||||
elif (var == 'lpower'):
|
||||
ind = 5
|
||||
units = " (nW)"
|
||||
elif (var == 'denergy'):
|
||||
ind = 6
|
||||
units = " (pJ)"
|
||||
else:
|
||||
error
|
||||
|
||||
widths = []
|
||||
metric = []
|
||||
if (freq != None):
|
||||
for oneSynth in allSynths:
|
||||
if (oneSynth[2] == freq):
|
||||
widths += [oneSynth[1]]
|
||||
metric += [oneSynth[ind]]
|
||||
else:
|
||||
widths = [8, 16, 32, 64, 128]
|
||||
for w in widths:
|
||||
m = 10000 # large number to start
|
||||
for oneSynth in allSynths:
|
||||
if (oneSynth[1] == w):
|
||||
if (oneSynth[3] < m):
|
||||
m = oneSynth[3]
|
||||
met = oneSynth[ind]
|
||||
metric += [met]
|
||||
return widths, metric, units
|
||||
|
||||
def writeCSV():
|
||||
allSynths = getData()
|
||||
file = open("ppaData.csv", "w")
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (mJ)'])
|
||||
|
||||
for one in allSynths:
|
||||
writer.writerow(one)
|
||||
|
||||
file.close()
|
||||
|
||||
def genLegend(fits, coefs, module, r2):
|
||||
|
||||
coefsr = [str(round(c, 3)) for c in coefs]
|
||||
|
||||
eq = ''
|
||||
ind = 0
|
||||
if 'c' in fits:
|
||||
eq += coefsr[ind]
|
||||
ind += 1
|
||||
if 'l' in fits:
|
||||
eq += " + " + coefsr[ind] + "*N"
|
||||
ind += 1
|
||||
if 's' in fits:
|
||||
eq += " + " + coefsr[ind] + "*N^2"
|
||||
ind += 1
|
||||
if 'g' in fits:
|
||||
eq += " + " + coefsr[ind] + "*log2(N)"
|
||||
ind += 1
|
||||
if 'n' in fits:
|
||||
eq += " + " + coefsr[ind] + "*Nlog2(N)"
|
||||
ind += 1
|
||||
|
||||
legend_elements = [lines.Line2D([0], [0], color='orange', label=eq),
|
||||
lines.Line2D([0], [0], color='steelblue', ls='', marker='o', label=' R^2='+ str(round(r2, 4)))]
|
||||
return legend_elements
|
||||
|
||||
def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn'):
|
||||
'''
|
||||
module: string module name
|
||||
freq: int freq (MHz)
|
||||
var: string delay, area, lpower, or denergy
|
||||
fits: constant, linear, square, log2, Nlog2
|
||||
plots chosen variable vs width for all matching syntheses with regression
|
||||
'''
|
||||
widths, metric, units = getVals(module, var, freq=freq)
|
||||
coefs, r2, funcArr = regress(widths, metric, fits)
|
||||
|
||||
xp = np.linspace(8, 140, 200)
|
||||
pred = []
|
||||
for x in xp:
|
||||
y = [func(x) for func in funcArr]
|
||||
pred += [sum(np.multiply(coefs, y))]
|
||||
|
||||
if ax is None:
|
||||
singlePlot = True
|
||||
ax = plt.gca()
|
||||
else:
|
||||
singlePlot = False
|
||||
|
||||
ax.scatter(widths, metric)
|
||||
ax.plot(xp, pred, color='orange')
|
||||
|
||||
legend_elements = genLegend(fits, coefs, module, r2)
|
||||
ax.legend(handles=legend_elements)
|
||||
|
||||
ax.set_xticks(widths)
|
||||
ax.set_xlabel("Width (bits)")
|
||||
ax.set_ylabel(str.title(var) + units)
|
||||
|
||||
if singlePlot:
|
||||
ax.set_title(module + " (target " + str(freq) + "MHz)")
|
||||
plt.show()
|
||||
|
||||
def regress(widths, var, fits='clsgn'):
|
||||
|
||||
funcArr = genFuncs(fits)
|
||||
|
||||
mat = []
|
||||
for w in widths:
|
||||
row = []
|
||||
for func in funcArr:
|
||||
row += [func(w)]
|
||||
mat += [row]
|
||||
|
||||
y = np.array(var, dtype=np.float)
|
||||
coefsResid = np.linalg.lstsq(mat, y, rcond=None)
|
||||
coefs = coefsResid[0]
|
||||
try:
|
||||
resid = coefsResid[1][0]
|
||||
except:
|
||||
resid = 0
|
||||
r2 = 1 - resid / (y.size * y.var())
|
||||
return coefs, r2, funcArr
|
||||
|
||||
def makeCoefTable():
|
||||
file = open("ppaFitting.csv", "w")
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(['Module', 'Metric', 'Freq', '1', 'N', 'N^2', 'log2(N)', 'Nlog2(N)', 'R^2'])
|
||||
|
||||
for mod in ['add', 'mult', 'comparator', 'shifter']:
|
||||
for comb in [['delay', 5000], ['area', 5000], ['area', 10]]:
|
||||
var = comb[0]
|
||||
freq = comb[1]
|
||||
widths, metric, units = getVals(mod, freq, var)
|
||||
coefs, r2, funcArr = regress(widths, metric)
|
||||
row = [mod] + comb + np.ndarray.tolist(coefs) + [r2]
|
||||
writer.writerow(row)
|
||||
|
||||
file.close()
|
||||
|
||||
def genFuncs(fits='clsgn'):
|
||||
funcArr = []
|
||||
if 'c' in fits:
|
||||
funcArr += [lambda x: 1]
|
||||
if 'l' in fits:
|
||||
funcArr += [lambda x: x]
|
||||
if 's' in fits:
|
||||
funcArr += [lambda x: x**2]
|
||||
if 'g' in fits:
|
||||
funcArr += [lambda x: np.log2(x)]
|
||||
if 'n' in fits:
|
||||
funcArr += [lambda x: x*np.log2(x)]
|
||||
return funcArr
|
||||
|
||||
def noOutliers(freqs, delays, areas):
|
||||
f=[]
|
||||
d=[]
|
||||
a=[]
|
||||
try:
|
||||
med = statistics.median(freqs)
|
||||
for i in range(len(freqs)):
|
||||
norm = freqs[i]/med
|
||||
if (norm > 0.25) & (norm<1.75):
|
||||
f += [freqs[i]]
|
||||
d += [delays[i]]
|
||||
a += [areas[i]]
|
||||
except: pass
|
||||
|
||||
return f, d, a
|
||||
|
||||
def freqPlot(mod, width):
|
||||
allSynths = getData(mod=mod, width=width)
|
||||
|
||||
freqsV, delaysV, areasV, freqsA, delaysA, areasA = ([] for i in range(6))
|
||||
for oneSynth in allSynths:
|
||||
if (mod == oneSynth[0]) & (width == oneSynth[1]):
|
||||
if (1000/oneSynth[3] < oneSynth[2]):
|
||||
freqsV += [oneSynth[2]]
|
||||
delaysV += [oneSynth[3]]
|
||||
areasV += [oneSynth[4]]
|
||||
else:
|
||||
freqsA += [oneSynth[2]]
|
||||
delaysA += [oneSynth[3]]
|
||||
areasA += [oneSynth[4]]
|
||||
|
||||
freqsV, delaysV, areasV = noOutliers(freqsV, delaysV, areasV)
|
||||
freqsA, delaysA, areasA = noOutliers(freqsA, delaysA, areasA)
|
||||
|
||||
adprodA = np.multiply(areasA, delaysA)
|
||||
adsqA = np.multiply(adprodA, delaysA)
|
||||
adprodV = np.multiply(areasV, delaysV)
|
||||
adsqV = np.multiply(adprodV, delaysV)
|
||||
|
||||
legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'),
|
||||
lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')]
|
||||
|
||||
f, (ax1, ax2, ax3, ax4) = plt.subplots(4, 1, sharex=True)
|
||||
ax1.scatter(freqsA, delaysA, color='green')
|
||||
ax1.scatter(freqsV, delaysV, color='blue')
|
||||
ax2.scatter(freqsA, areasA, color='green')
|
||||
ax2.scatter(freqsV, areasV, color='blue')
|
||||
ax3.scatter(freqsA, adprodA, color='green')
|
||||
ax3.scatter(freqsV, adprodV, color='blue')
|
||||
ax4.scatter(freqsA, adsqA, color='green')
|
||||
ax4.scatter(freqsV, adsqV, color='blue')
|
||||
ax1.legend(handles=legend_elements)
|
||||
ax4.set_xlabel("Target Freq (MHz)")
|
||||
ax1.set_ylabel('Delay (ns)')
|
||||
ax2.set_ylabel('Area (sq microns)')
|
||||
ax3.set_ylabel('Area * Delay')
|
||||
ax4.set_ylabel('Area * Delay^2')
|
||||
ax1.set_title(mod + '_' + str(width))
|
||||
plt.show()
|
||||
|
||||
def plotPPA(mod, freq=None):
|
||||
fig, axs = plt.subplots(2, 2)
|
||||
oneMetricPlot(mod, 'delay', ax=axs[0,0], fits='clg', freq=freq)
|
||||
oneMetricPlot(mod, 'area', ax=axs[0,1], fits='s', freq=freq)
|
||||
oneMetricPlot(mod, 'lpower', ax=axs[1,0], fits='c', freq=freq)
|
||||
oneMetricPlot(mod, 'denergy', ax=axs[1,1], fits='s', freq=freq)
|
||||
titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " min delay"
|
||||
plt.suptitle(mod + titleStr)
|
||||
plt.show()
|
||||
|
||||
# writeCSV()
|
||||
# makeCoefTable()
|
||||
|
||||
freqPlot('decoder', 8)
|
||||
|
||||
plotPPA('decoder')
|
@ -1,45 +1,803 @@
|
||||
Module,Width,Target Freq,Delay,Area
|
||||
add,16,10,2.032906,221.479998
|
||||
add,16,4000,0.249839,551.740010
|
||||
add,16,5000,0.228259,924.140017
|
||||
add,16,6000,0.225754,1120.140018
|
||||
add,32,10,4.160501,456.679995
|
||||
add,32,4000,0.280842,1730.680031
|
||||
add,32,5000,0.250500,1933.540033
|
||||
add,32,6000,0.271774,1746.360030
|
||||
add,64,10,8.474034,927.079988
|
||||
add,64,4000,0.323267,3758.300065
|
||||
add,64,5000,0.334061,3798.480071
|
||||
add,64,6000,0.328457,3749.480066
|
||||
comparator,16,10,0.576329,252.840005
|
||||
comparator,16,4000,0.249312,280.280005
|
||||
comparator,16,5000,0.199026,313.600006
|
||||
comparator,16,6000,0.166568,422.380007
|
||||
comparator,32,10,0.765874,495.880010
|
||||
comparator,32,4000,0.249950,608.580012
|
||||
comparator,32,5000,0.205372,919.240014
|
||||
comparator,32,6000,0.201200,1248.520016
|
||||
comparator,64,10,0.561562,1008.420020
|
||||
comparator,64,4000,0.249905,1437.660027
|
||||
comparator,64,5000,0.219296,2738.120023
|
||||
comparator,64,6000,0.221138,2341.220025
|
||||
mult,16,10,4.730546,3869.040009
|
||||
mult,16,4000,0.821111,9132.620147
|
||||
mult,16,5000,0.820059,9583.420143
|
||||
mult,16,6000,0.831308,8594.600132
|
||||
mult,32,10,7.575772,12412.680067
|
||||
mult,32,4000,1.091389,31262.980534
|
||||
mult,32,5000,1.092153,31497.200524
|
||||
mult,32,6000,1.084816,33519.920555
|
||||
mult,64,10,4.793300,46798.920227
|
||||
mult,64,4000,1.411752,93087.261425
|
||||
mult,64,5000,1.404875,94040.801492
|
||||
mult,64,6000,1.415466,89931.661403
|
||||
shifter,32,10,1.906335,1656.200032
|
||||
shifter,32,10,1.906335,1656.200032
|
||||
shifter,32,4000,0.260606,3490.760054
|
||||
shifter,32,4000,0.260606,3490.760054
|
||||
shifter,32,5000,0.238962,4985.260077
|
||||
shifter,32,5000,0.238962,4985.260077
|
||||
shifter,32,6000,0.241742,4312.000069
|
||||
shifter,32,6000,0.241742,4312.000069
|
||||
Module,Width,Target Freq,Delay,Area,L Power (nW),D energy (mJ)
|
||||
add,128,10,7.100851,1867.879976,465.925,0.035575263509999996
|
||||
add,128,1538,0.633294,4623.64009,632.254,0.27231642
|
||||
add,128,2051,0.486762,4951.940095,885.884,0.35630978399999996
|
||||
add,128,2359,0.423881,5520.340104,1.49,0.451433265
|
||||
add,128,2410,0.414767,5600.700103,1.57,0.456658467
|
||||
add,128,2462,0.406101,5721.240105,1.77,0.477980877
|
||||
add,128,2513,0.397913,6085.800112,2.14,0.516093161
|
||||
add,128,2564,0.436395,6456.240111,2.27,0.615753345
|
||||
add,128,2615,0.390136,6662.040117,2.45,0.6261682799999999
|
||||
add,128,2667,0.394304,7494.060127,3.58,0.76692128
|
||||
add,128,2718,0.407908,7287.280117,3.35,0.7693144879999999
|
||||
add,128,2769,0.431383,6941.340124,2.86,0.742841526
|
||||
add,128,3077,0.387515,7712.60013,2.93,0.9029099500000001
|
||||
add,128,3590,0.386891,6860.000114,2.62,0.913836542
|
||||
add,128,5000,0.389771,7007.980119,2.77,1.289752239
|
||||
add,16,10,2.032906,221.479998,55.29,0.00116892095
|
||||
add,16,2609,0.375085,405.720008,52.28,0.028731511
|
||||
add,16,3478,0.287131,443.940009,126.253,0.041921126
|
||||
add,16,4000,0.249839,551.74001,302.479,0.059711521
|
||||
add,16,4087,0.243761,503.720009,183.936,0.050946049
|
||||
add,16,4174,0.239287,549.780011,304.811,0.060061037
|
||||
add,16,4261,0.234402,607.60001,368.742,0.06680457
|
||||
add,16,4348,0.22992,610.540011,364.173,0.06575712
|
||||
add,16,4435,0.22545,666.400011,419.709,0.0789075
|
||||
add,16,4522,0.222724,820.260016,626.379,0.090871392
|
||||
add,16,4609,0.221986,815.360013,735.998,0.091680218
|
||||
add,16,4696,0.227412,866.320016,645.684,0.10392728400000001
|
||||
add,16,5000,0.228259,924.140017,641.631,0.118466421
|
||||
add,16,5217,0.22222,824.180016,601.276,0.10177676000000001
|
||||
add,16,6000,0.225754,1120.140018,1.01,0.166832206
|
||||
add,16,6087,0.226225,857.500013,678.287,0.14161685000000002
|
||||
add,32,10,4.160501,456.679995,112.161,0.00490939118
|
||||
add,32,2400,0.41509,958.440019,151.083,0.06848985
|
||||
add,32,3200,0.312424,1121.120021,296.836,0.105599312
|
||||
add,32,3680,0.271527,1465.100024,591.825,0.149882904
|
||||
add,32,3760,0.278449,1689.520028,834.387,0.18739617700000002
|
||||
add,32,3840,0.291206,1547.420027,784.112,0.177344454
|
||||
add,32,3920,0.273454,2044.280039,1.33,0.23653770999999998
|
||||
add,32,4000,0.280842,1730.680031,849.828,0.20641886999999998
|
||||
add,32,4080,0.256294,1991.360031,1.24,0.223744662
|
||||
add,32,4160,0.253175,2031.540036,1.24,0.231655125
|
||||
add,32,4240,0.268332,1829.660028,1.09,0.218958912
|
||||
add,32,4320,0.254861,1716.960028,866.723,0.199811024
|
||||
add,32,4800,0.258491,1955.100033,1.07,0.27865329800000005
|
||||
add,32,5000,0.2505,1933.540033,1.03,0.26277449999999997
|
||||
add,32,5600,0.254525,1871.800028,877.446,0.28048655
|
||||
add,32,6000,0.271774,1746.36003,955.901,0.309278812
|
||||
add,64,10,8.474034,927.079988,230.083,0.02084612364
|
||||
add,64,1818,0.538894,2114.840041,250.049,0.1347235
|
||||
add,64,2424,0.412474,2298.100044,453.413,0.175713924
|
||||
add,64,2788,0.358537,2637.180048,758.693,0.235558809
|
||||
add,64,2848,0.351091,2625.420049,698.362,0.23523097
|
||||
add,64,2909,0.343753,2800.840049,852.781,0.25368971399999996
|
||||
add,64,2970,0.337807,3412.360059,1.37,0.33003743900000004
|
||||
add,64,3030,0.331556,3202.640054,1.28,0.311331084
|
||||
add,64,3091,0.349251,3284.960053,1.35,0.34331373299999995
|
||||
add,64,3152,0.328164,3804.360061,1.89,0.39543762000000005
|
||||
add,64,3212,0.336436,3593.660062,1.72,0.38387347600000005
|
||||
add,64,3273,0.311119,3816.120062,1.96,0.39947679599999997
|
||||
add,64,3636,0.330032,3266.340054,1.22,0.407259488
|
||||
add,64,4000,0.323267,3758.300065,1.75,0.492335641
|
||||
add,64,4242,0.328234,3507.420063,1.57,0.47003108800000004
|
||||
add,64,5000,0.334061,3798.480071,2.18,0.640394937
|
||||
add,64,6000,0.328457,3749.480066,1.77,0.770560122
|
||||
add,8,10,0.940062,103.879999,24.765,0.000226554942
|
||||
add,8,5000,0.199689,197.960003,83.576,0.022564857
|
||||
comparator,128,10,0.842074,1997.240039,243.506,0.00073260438
|
||||
comparator,128,2308,0.406531,2810.640055,437.781,0.156107904
|
||||
comparator,128,3077,0.324985,2559.760047,659.43,0.17159208
|
||||
comparator,128,3538,0.282712,3158.540057,1.6,0.26490114400000003
|
||||
comparator,128,3615,0.276605,3092.880056,1.5,0.26443437999999997
|
||||
comparator,128,3692,0.270828,3380.020055,2.0,0.30170239200000004
|
||||
comparator,128,3769,0.27069,3741.640049,2.91,0.34404698999999994
|
||||
comparator,128,3846,0.273602,4038.58005,3.61,0.41751665200000004
|
||||
comparator,128,3923,0.256043,4153.240051,3.84,0.382528242
|
||||
comparator,128,4000,0.268954,4027.800041,3.66,0.44538782400000004
|
||||
comparator,128,4077,0.262622,4638.340054,5.12,0.5050221060000001
|
||||
comparator,128,4154,0.257245,4649.120047,5.1,0.5502470549999999
|
||||
comparator,128,4615,0.265848,4047.400041,3.87,0.49421143199999995
|
||||
comparator,128,5000,0.260142,5215.56005,6.0,0.964606536
|
||||
comparator,128,5385,0.267095,4787.300045,5.3,1.016830665
|
||||
comparator,16,10000,0.146177,1065.260009,1.61,0.182282719
|
||||
comparator,16,10,0.576329,252.840005,31.402,8.2991376e-05
|
||||
comparator,16,4000,0.249312,280.280005,55.248,0.0144850272
|
||||
comparator,16,5000,0.199026,313.600006,78.893,0.0170963334
|
||||
comparator,16,5333,0.186933,318.500006,100.145,0.021871161
|
||||
comparator,16,6000,0.166568,422.380007,301.506,0.04247484
|
||||
comparator,16,6133,0.16297,441.000006,363.571,0.04009062
|
||||
comparator,16,6267,0.168782,502.740008,498.843,0.053841457999999995
|
||||
comparator,16,6400,0.168782,604.660008,744.154,0.05924248199999999
|
||||
comparator,16,6533,0.152969,508.620009,432.277,0.056292591999999995
|
||||
comparator,16,6667,0.150575,691.880011,816.855,0.06911392499999999
|
||||
comparator,16,6800,0.146926,723.240009,925.474,0.08110315200000001
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||||
comparator,16,6933,0.168782,607.600006,799.51,0.065149852
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||||
comparator,16,7067,0.158772,756.56001,1.05,0.079068456
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||||
comparator,16,7200,0.15891,771.260013,1.09,0.08040846
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||||
comparator,16,8000,0.158838,801.640006,1.19,0.09959142600000001
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||||
comparator,16,9333,0.166546,695.800007,927.014,0.11258509600000001
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||||
comparator,32,10000,0.194087,1451.380013,1.85,0.47415454100000004
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||||
comparator,32,10,0.765874,495.88001,66.41,0.000173087524
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||||
comparator,32,3158,0.304333,684.040013,135.532,0.041084955000000006
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||||
comparator,32,4000,0.24995,608.580012,130.613,0.041991600000000004
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||||
comparator,32,4211,0.237004,654.640013,145.103,0.046926792
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||||
comparator,32,4842,0.206449,781.060011,485.75,0.069986211
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||||
comparator,32,4947,0.2021,882.980013,601.459,0.10488990000000001
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||||
comparator,32,5000,0.205372,919.240014,840.47,0.08830995999999999
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||||
comparator,32,5053,0.197891,805.560012,561.888,0.07302177900000001
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||||
comparator,32,5158,0.197393,1203.440015,1.31,0.14725517800000001
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||||
comparator,32,5263,0.195832,1060.360011,1.06,0.10770760000000001
|
||||
comparator,32,5368,0.199678,1110.340013,1.12,0.13638007400000002
|
||||
comparator,32,5474,0.192304,1188.740012,1.43,0.137881968
|
||||
comparator,32,5579,0.192149,1206.380012,1.44,0.172549802
|
||||
comparator,32,5684,0.203736,1218.140014,1.42,0.19762392
|
||||
comparator,32,6000,0.2012,1248.520016,1.48,0.1867136
|
||||
comparator,32,6316,0.2012,1239.700017,1.45,0.1963712
|
||||
comparator,32,7368,0.194845,1391.600021,1.66,0.34799316999999996
|
||||
comparator,64,10,0.561562,1008.42002,127.626,0.000252141338
|
||||
comparator,64,2727,0.333026,1392.580027,202.012,0.077262032
|
||||
comparator,64,3636,0.275001,1323.000026,357.28,0.09707535299999999
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||||
comparator,64,4000,0.249905,1437.660027,558.66,0.11545611
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||||
comparator,64,4182,0.239102,1454.320026,590.635,0.10974781800000001
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||||
comparator,64,4273,0.233995,1568.980027,683.786,0.14297094500000002
|
||||
comparator,64,4364,0.229142,1709.120026,1.02,0.17552277200000002
|
||||
comparator,64,4455,0.224454,1899.240032,1.34,0.20492650199999998
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||||
comparator,64,4545,0.229482,2235.380032,2.24,0.25931466
|
||||
comparator,64,4636,0.215691,2072.700029,1.84,0.210298725
|
||||
comparator,64,4727,0.225291,2499.000023,2.71,0.311352162
|
||||
comparator,64,4818,0.214579,2591.120026,2.62,0.38087772499999994
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||||
comparator,64,4909,0.213022,2891.980026,3.4,0.401972514
|
||||
comparator,64,5000,0.219296,2738.120023,2.95,0.436179744
|
||||
comparator,64,5455,0.221407,2929.220025,3.36,0.49750152899999994
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||||
comparator,64,6000,0.221138,2341.220025,2.59,0.296988334
|
||||
comparator,64,6364,0.223965,2547.020023,2.94,0.557896815
|
||||
comparator,8,10000,0.1136,496.86,810.074,0.07338560000000001
|
||||
comparator,8,10909,0.11361,387.1,565.114,0.07293762000000001
|
||||
comparator,8,10,0.29577,118.580002,16.053,2.0201091e-05
|
||||
comparator,8,12727,0.113615,488.039998,768.445,0.09202815
|
||||
comparator,8,5000,0.195502,129.360003,21.443,0.0069989716
|
||||
comparator,8,5455,0.182936,130.340003,22.567,0.0072442656
|
||||
comparator,8,7273,0.13643,147.980003,61.898,0.01459801
|
||||
comparator,8,8364,0.119528,210.700003,172.337,0.026535216
|
||||
comparator,8,8545,0.116724,205.800003,165.947,0.027897035999999997
|
||||
comparator,8,8727,0.124671,264.600002,278.768,0.038648010000000003
|
||||
comparator,8,8909,0.11208,261.660004,251.629,0.03564144
|
||||
comparator,8,9091,0.10991,297.920001,343.785,0.038798229999999996
|
||||
comparator,8,9273,0.107742,309.680003,356.05,0.041588412000000005
|
||||
comparator,8,9455,0.106411,345.94,438.668,0.045969552000000004
|
||||
comparator,8,9636,0.111488,397.88,589.556,0.06064947200000001
|
||||
comparator,8,9818,0.11361,381.219999,573.131,0.05873637
|
||||
decoder,128,11997,0.083125,926.100008,787.251,0.0482125
|
||||
decoder,128,12763,0.079353,1086.820012,959.985,0.064910754
|
||||
decoder,128,13273,0.100672,959.420012,753.194,0.074799296
|
||||
decoder,128,13784,0.080668,1300.460014,1.37,0.09180018399999999
|
||||
decoder,128,15000,0.101117,1111.320011,1.04,0.098386841
|
||||
decoder,128,15315,0.079077,1283.800018,1.26,0.100269636
|
||||
decoder,128,17868,0.101057,1072.12001,985.334,0.113588068
|
||||
decoder,128,20000,0.078354,1161.30001,1.13,0.11134103399999999
|
||||
decoder,128,7500,0.13242,552.72001,163.224,0.01694976
|
||||
decoder,128,7658,0.130462,549.78001,153.219,0.015394515999999999
|
||||
decoder,16,12005,0.08179,78.400002,12.174,0.0013904300000000002
|
||||
decoder,16,18407,0.052159,98.980002,39.072,0.0038128229
|
||||
decoder,16,20000,0.049981,94.080001,66.328,0.003348727
|
||||
decoder,16,20008,0.049718,95.060001,70.279,0.0034554010000000003
|
||||
decoder,16,21208,0.047148,119.560002,121.799,0.005940648000000001
|
||||
decoder,16,21608,0.046101,118.580002,119.754,0.005393817
|
||||
decoder,16,22809,0.04375,201.880002,199.593,0.013387499999999998
|
||||
decoder,32,10000,0.099725,147.980003,44.83,0.0032510349999999993
|
||||
decoder,32,12025,0.081513,166.600003,59.7,0.004646241000000001
|
||||
decoder,32,14430,0.068522,191.100004,82.08,0.007126288
|
||||
decoder,32,15000,0.066529,175.420003,85.153,0.0062005028
|
||||
decoder,32,15332,0.06516,314.580003,249.747,0.0172674
|
||||
decoder,32,16234,0.061497,250.880004,167.484,0.012053412000000001
|
||||
decoder,32,17000,0.06201,655.62001,900.063,0.049235940000000006
|
||||
decoder,32,18000,0.06048,825.160012,1.22,0.0671328
|
||||
decoder,32,19000,0.059976,951.580016,1.48,0.08120750400000001
|
||||
decoder,32,20000,0.060737,1096.620017,1.73,0.104042481
|
||||
decoder,32,21000,0.059192,926.100019,1.38,0.08837365600000001
|
||||
decoder,32,25000,0.058416,905.52001,1.34,0.104155728
|
||||
decoder,32,7500,0.115541,147.000003,15.758,0.0023801446
|
||||
decoder,32,9019,0.104922,155.820003,44.605,0.0071871570000000004
|
||||
decoder,64,10000,0.098226,291.060005,96.679,0.009744019199999999
|
||||
decoder,64,10511,0.094204,302.820005,116.69,0.011869704
|
||||
decoder,64,15000,0.066629,643.86001,638.115,0.038778077999999994
|
||||
decoder,64,16117,0.061996,696.780014,775.245,0.041351332000000005
|
||||
decoder,64,16467,0.060727,780.080013,923.175,0.050160502
|
||||
decoder,64,18920,0.069176,905.520014,1.07,0.081835208
|
||||
decoder,64,19270,0.055769,1076.040022,1.56,0.074228539
|
||||
decoder,64,20000,0.057083,1052.520018,1.55,0.07826079300000001
|
||||
decoder,64,7500,0.131244,264.600005,64.81,0.0040816884
|
||||
decoder,8,10000,0.085629,37.240001,2.355,0.00054203157
|
||||
decoder,8,10744,0.085629,37.240001,2.355,0.0005822771999999999
|
||||
decoder,8,11445,0.085629,37.240001,2.355,0.00061995396
|
||||
decoder,8,11678,0.085629,37.240001,2.355,0.00063279831
|
||||
decoder,8,11912,0.067612,37.240001,2.814,0.0005233168800000001
|
||||
decoder,8,12613,0.067612,37.240001,2.814,0.00055374228
|
||||
decoder,8,12846,0.067612,37.240001,2.814,0.0005638840800000001
|
||||
decoder,8,13313,0.05554,38.220001,2.007,0.00047153459999999995
|
||||
decoder,8,16350,0.05554,38.220001,2.007,0.000577616
|
||||
decoder,8,7007,0.085629,37.240001,2.355,0.00037933647
|
||||
flop,128,10000,0.067611,2132.47998,1.04,2.047734357
|
||||
flop,128,11832,0.067611,2132.47998,1.04,2.422840185
|
||||
flop,128,13903,0.067611,2132.47998,1.04,2.846963988
|
||||
flop,128,14199,0.067611,2132.47998,1.04,2.907543444
|
||||
flop,128,14495,0.067611,2132.47998,1.04,2.9681905110000004
|
||||
flop,128,14790,0.067611,2132.47998,1.04,3.0285671339999998
|
||||
flop,128,15000,0.067611,2132.47998,1.04,3.0715677300000004
|
||||
flop,128,15382,0.067611,2132.47998,1.04,3.1497936570000005
|
||||
flop,128,15678,0.067611,2132.47998,1.04,3.210440724
|
||||
flop,128,15974,0.067611,2132.47998,1.04,3.2710201800000003
|
||||
flop,128,16270,0.067611,2132.47998,1.04,3.3316672470000004
|
||||
flop,128,16861,0.067611,2132.47998,1.04,3.4526909370000003
|
||||
flop,128,17749,0.067611,2132.47998,1.04,3.6344969160000002
|
||||
flop,128,20000,0.067611,2132.47998,1.04,4.095468714
|
||||
flop,128,20707,0.067611,2132.47998,1.04,4.240223865000001
|
||||
flop,128,8874,0.067611,2132.47998,1.04,1.8171808470000002
|
||||
flop,16,10000,0.067611,266.559998,129.629,0.25597524600000005
|
||||
flop,16,11832,0.067611,266.559998,129.629,0.30289728000000005
|
||||
flop,16,13607,0.067611,266.559998,129.629,0.34833187200000004
|
||||
flop,16,13903,0.067611,266.559998,129.629,0.35590430400000006
|
||||
flop,16,14199,0.067611,266.559998,129.629,0.363476736
|
||||
flop,16,14495,0.067611,266.559998,129.629,0.37104916800000004
|
||||
flop,16,14790,0.067611,266.559998,129.629,0.3786216
|
||||
flop,16,15000,0.067611,266.559998,129.629,0.38403048
|
||||
flop,16,15086,0.067611,266.559998,129.629,0.386194032
|
||||
flop,16,15382,0.067611,266.559998,129.629,0.39376646400000004
|
||||
flop,16,15678,0.067611,266.559998,129.629,0.401338896
|
||||
flop,16,15974,0.067611,266.559998,129.629,0.408911328
|
||||
flop,16,16270,0.067611,266.559998,129.629,0.416551371
|
||||
flop,16,16861,0.067611,266.559998,129.629,0.43162862400000007
|
||||
flop,16,20000,0.067611,266.559998,129.629,0.5120181030000001
|
||||
flop,16,20707,0.067611,266.559998,129.629,0.530137851
|
||||
flop,16,8874,0.067611,266.559998,129.629,0.22717296
|
||||
flop,32,10000,0.067611,533.119995,259.258,0.5119504920000001
|
||||
flop,32,11832,0.067611,533.119995,259.258,0.6057945600000001
|
||||
flop,32,13607,0.067611,533.119995,259.258,0.6966637440000001
|
||||
flop,32,13903,0.067611,533.119995,259.258,0.7118086080000001
|
||||
flop,32,14199,0.067611,533.119995,259.258,0.726953472
|
||||
flop,32,14495,0.067611,533.119995,259.258,0.7420983360000001
|
||||
flop,32,14790,0.067611,533.119995,259.258,0.7572432
|
||||
flop,32,15000,0.067611,533.119995,259.258,0.767993349
|
||||
flop,32,15086,0.067611,533.119995,259.258,0.772388064
|
||||
flop,32,15382,0.067611,533.119995,259.258,0.7875329280000001
|
||||
flop,32,15678,0.067611,533.119995,259.258,0.802677792
|
||||
flop,32,15974,0.067611,533.119995,259.258,0.817822656
|
||||
flop,32,16270,0.067611,533.119995,259.258,0.8329675200000001
|
||||
flop,32,16861,0.067611,533.119995,259.258,0.8632572480000001
|
||||
flop,32,17749,0.067611,533.119995,259.258,0.90869184
|
||||
flop,32,20000,0.067611,533.119995,259.258,1.0239685950000001
|
||||
flop,32,20707,0.067611,533.119995,259.258,1.06014048
|
||||
flop,32,8874,0.067611,533.119995,259.258,0.45434592
|
||||
flop,64,10000,0.067611,1066.23999,518.516,1.0239009840000002
|
||||
flop,64,11832,0.067611,1066.23999,518.516,1.211453898
|
||||
flop,64,13607,0.067611,1066.23999,518.516,1.393259877
|
||||
flop,64,13903,0.067611,1066.23999,518.516,1.423549605
|
||||
flop,64,14199,0.067611,1066.23999,518.516,1.4538393330000001
|
||||
flop,64,14790,0.067611,1066.23999,518.516,1.514351178
|
||||
flop,64,15000,0.067611,1066.23999,518.516,1.5358514760000002
|
||||
flop,64,15086,0.067611,1066.23999,518.516,1.5446409060000001
|
||||
flop,64,15382,0.067611,1066.23999,518.516,1.5749982450000002
|
||||
flop,64,15974,0.067611,1066.23999,518.516,1.635577701
|
||||
flop,64,16270,0.067611,1066.23999,518.516,1.665867429
|
||||
flop,64,16861,0.067611,1066.23999,518.516,1.7263792740000001
|
||||
flop,64,17749,0.067611,1066.23999,518.516,1.8173160690000003
|
||||
flop,64,20000,0.067611,1066.23999,518.516,2.0478019680000004
|
||||
flop,64,20707,0.067611,1066.23999,518.516,2.120213349
|
||||
flop,64,8874,0.067611,1066.23999,518.516,0.9086242290000001
|
||||
flop,8,10000,0.067611,133.279999,64.814,0.12798762300000002
|
||||
flop,8,11832,0.067611,133.279999,64.814,0.15144864000000002
|
||||
flop,8,13607,0.067611,133.279999,64.814,0.17416593600000002
|
||||
flop,8,13903,0.067611,133.279999,64.814,0.17801976300000003
|
||||
flop,8,14199,0.067611,133.279999,64.814,0.181805979
|
||||
flop,8,14790,0.067611,133.279999,64.814,0.1893108
|
||||
flop,8,15000,0.067611,133.279999,64.814,0.19201524
|
||||
flop,8,15382,0.067611,133.279999,64.814,0.196950843
|
||||
flop,8,15678,0.067611,133.279999,64.814,0.200737059
|
||||
flop,8,16270,0.067611,133.279999,64.814,0.208309491
|
||||
flop,8,20000,0.067611,133.279999,64.814,0.256042857
|
||||
flopenr,128,10000,0.172806,6543.460042,3.8,10.839429156
|
||||
flopenr,128,20000,0.216852,6351.380048,2.97,26.923043208
|
||||
flopenr,128,3472,0.243217,4090.519957,839.91,2.155875488
|
||||
flopenr,128,4629,0.196289,4950.960049,2.03,3.966215534
|
||||
flopenr,128,5324,0.185184,5635.980017,2.56,6.2853301440000005
|
||||
flopenr,128,5440,0.212028,5488.000058,2.66,6.8258174039999995
|
||||
flopenr,128,5555,0.180307,5170.47998,1.93,4.730173838
|
||||
flopenr,128,5671,0.233427,5740.840082,3.05,8.013782337
|
||||
flopenr,128,5787,0.158508,5392.939968,2.19,4.578345072
|
||||
flopenr,128,5903,0.204863,5312.580023,2.48,6.196900886999999
|
||||
flopenr,128,6018,0.229543,5500.74005,2.85,7.564819108000001
|
||||
flopenr,128,6134,0.21139,5399.800032,2.6,7.055986809999999
|
||||
flopenr,128,6366,0.202213,5357.660028,2.77,6.433406595
|
||||
flopenr,128,6944,0.193452,5612.460024,2.98,7.582351140000001
|
||||
flopenr,16,10000,0.150576,864.360014,554.564,1.199940144
|
||||
flopenr,16,5313,0.173096,761.460013,502.047,0.735138712
|
||||
flopenr,16,6243,0.175796,845.740013,528.22,0.8188577680000001
|
||||
flopenr,16,6376,0.163753,774.200016,397.636,0.824332602
|
||||
flopenr,16,6508,0.156837,849.660017,412.253,0.82182588
|
||||
flopenr,16,6641,0.149304,696.780009,370.215,0.644843976
|
||||
flopenr,16,6774,0.157317,775.180016,386.651,0.8381849760000001
|
||||
flopenr,16,6907,0.157317,767.340013,356.367,0.808137429
|
||||
flopenr,16,7040,0.165641,829.080008,388.122,0.938356265
|
||||
flopenr,16,7172,0.149628,879.060014,543.145,0.9070449360000001
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floprasync,16,13718,0.011172,367.500007,163.187,0.057491112
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floprasync,16,16104,0.067064,421.400004,288.357,0.41143764
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floprasync,16,16402,0.067064,421.400004,288.357,0.419015872
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floprasync,16,16999,0.067064,421.400004,288.357,0.434306464
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floprasync,16,17893,0.067064,421.400004,288.357,0.45710822399999995
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floprasync,16,20876,0.067064,421.400004,288.357,0.5333599920000001
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floprasync,16,8947,0.067064,362.600007,161.167,0.22426201599999998
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floprasync,32,14607,0.008449,730.100014,327.985,0.09319247
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floprasync,32,16513,0.067064,782.040011,449.182,0.843061544
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||||
shifter,32,5000,0.238962,4985.260077,4.9,0.594776418
|
||||
shifter,32,6000,0.241742,4312.000069,3.71,0.582839962
|
||||
shifter,32,6000,0.241742,4312.000069,3.71,0.582839962
|
||||
shifter,32,6000,0.241742,4312.000069,3.71,0.582839962
|
||||
shifter,64,10,2.919486,4346.300085,210.734,0.008670873420000001
|
||||
shifter,64,5000,0.358993,9471.700156,6.94,1.621930374
|
||||
shifter,8,10,0.622998,244.020005,26.943,0.00011836962000000002
|
||||
shifter,8,5000,0.198885,495.88001,300.128,0.056682224999999996
|
||||
shiftleft,128,10000,0.313996,12023.620188,9.23,3.370119068
|
||||
shiftleft,128,1935,0.516184,5594.820107,768.953,0.30712947999999995
|
||||
shiftleft,128,2581,0.387267,7361.76014,2.47,0.42405736499999996
|
||||
shiftleft,128,2968,0.33687,9142.420162,5.66,0.76772673
|
||||
shiftleft,128,3032,0.329767,9579.500162,6.25,0.817492393
|
||||
shiftleft,128,3097,0.322855,8849.400141,5.95,0.731266575
|
||||
shiftleft,128,3161,0.321225,10330.180176,7.53,0.9106728749999999
|
||||
shiftleft,128,3226,0.320064,10597.720193,7.05,0.893618688
|
||||
shiftleft,128,3290,0.314992,10979.920188,8.05,0.985609968
|
||||
shiftleft,128,3355,0.309977,11750.200195,9.57,1.06012134
|
||||
shiftleft,128,3419,0.302549,10925.040179,7.55,0.99236072
|
||||
shiftleft,128,3484,0.313597,11188.660188,8.59,1.077519292
|
||||
shiftleft,128,3871,0.303026,12747.840208,1.16,1.410889056
|
||||
shiftleft,128,4516,0.309266,12621.420203,1.12,1.610038796
|
||||
shiftleft,128,5000,0.319285,11347.420196,8.66,1.5265015849999999
|
||||
shiftleft,128,7500,0.32019,11850.160206,9.18,2.42896134
|
||||
shiftleft,16,10000,0.128994,1192.660017,1.42,0.132734826
|
||||
shiftleft,16,10769,0.131174,1153.460019,1.35,0.133666306
|
||||
shiftleft,16,4615,0.215535,446.880008,113.608,0.023493315
|
||||
shiftleft,16,5000,0.198416,468.440009,148.45,0.025397248
|
||||
shiftleft,16,6154,0.162492,802.620013,641.83,0.057847152
|
||||
shiftleft,16,7077,0.141279,1079.960019,1.18,0.08321333099999999
|
||||
shiftleft,16,7231,0.138234,1233.820018,1.4,0.09773143799999999
|
||||
shiftleft,16,7385,0.135404,937.860017,965.452,0.068514424
|
||||
shiftleft,16,7500,0.133331,1031.940019,1.06,0.088265122
|
||||
shiftleft,16,7538,0.132481,971.180015,992.057,0.07418936
|
||||
shiftleft,16,7692,0.130257,1033.900012,1.06,0.08049882600000001
|
||||
shiftleft,16,7846,0.127358,935.900016,874.844,0.079344034
|
||||
shiftleft,16,8000,0.124837,968.240013,940.706,0.073029645
|
||||
shiftleft,16,8154,0.128748,1062.320016,1.07,0.086518656
|
||||
shiftleft,16,8308,0.12432,1199.520016,1.3,0.10057488
|
||||
shiftleft,16,9231,0.113513,1695.400019,2.27,0.149950673
|
||||
shiftleft,32,10000,0.15971,3675.98006,4.09,0.5206546
|
||||
shiftleft,32,3750,0.266551,1173.060021,319.774,0.059174321999999994
|
||||
shiftleft,32,5000,0.199946,2419.620024,2.11,0.21554178800000004
|
||||
shiftleft,32,5750,0.173824,2582.30004,2.29,0.204764672
|
||||
shiftleft,32,5875,0.169973,2781.240046,2.63,0.22385444100000002
|
||||
shiftleft,32,6000,0.169263,2872.380041,2.88,0.24272314199999998
|
||||
shiftleft,32,6125,0.163188,2892.960045,2.74,0.235317096
|
||||
shiftleft,32,6250,0.159977,2964.500038,3.13,0.268121452
|
||||
shiftleft,32,6375,0.159792,3330.040049,3.53,0.296573952
|
||||
shiftleft,32,6500,0.158323,3294.760046,3.49,0.29020605899999996
|
||||
shiftleft,32,6625,0.155982,3619.14005,4.14,0.331617732
|
||||
shiftleft,32,6750,0.156124,3323.180043,3.58,0.30288056
|
||||
shiftleft,32,7500,0.166296,3306.520048,3.7,0.35171604
|
||||
shiftleft,32,8750,0.164673,3752.420048,4.46,0.47178814500000005
|
||||
shiftleft,64,10000,0.23373,6486.620108,6.06,1.38251295
|
||||
shiftleft,64,2609,0.382901,2559.760048,666.022,0.14205627099999998
|
||||
shiftleft,64,3478,0.287377,3864.140062,2.25,0.304044866
|
||||
shiftleft,64,4000,0.249988,4733.400082,3.49,0.366982384
|
||||
shiftleft,64,4087,0.244635,4460.960079,2.81,0.336373125
|
||||
shiftleft,64,4174,0.239544,5090.120088,4.17,0.440281872
|
||||
shiftleft,64,4261,0.234657,5289.060089,3.95,0.45171472500000004
|
||||
shiftleft,64,4348,0.23035,5490.940094,4.5,0.49456144999999996
|
||||
shiftleft,64,4435,0.24668,5129.320094,4.03,0.4834928
|
||||
shiftleft,64,4522,0.23827,5915.280105,5.1,0.5599345
|
||||
shiftleft,64,4609,0.229176,6732.600115,6.6,0.6073164
|
||||
shiftleft,64,4696,0.2291,6340.600105,5.97,0.6313996
|
||||
shiftleft,64,5000,0.239464,5848.640098,4.78,0.610154272
|
||||
shiftleft,64,5217,0.234181,6430.760098,6.17,0.7226825659999999
|
||||
shiftleft,64,6087,0.227478,6715.940117,5.94,0.82915731
|
||||
shiftleft,64,7500,0.229635,7015.820112,6.8,1.08755136
|
||||
shiftleft,8,10000,0.100846,390.040004,479.939,0.031867336
|
||||
shiftleft,8,10222,0.097799,394.940007,435.049,0.040195389
|
||||
shiftleft,8,10444,0.095384,335.160004,328.601,0.032716712
|
||||
shiftleft,8,10667,0.093734,359.660006,404.389,0.042461502
|
||||
shiftleft,8,10889,0.098154,548.800008,801.248,0.05319946800000001
|
||||
shiftleft,8,11111,0.091007,491.960005,678.321,0.042591276000000004
|
||||
shiftleft,8,11333,0.092595,545.860006,815.115,0.06018675
|
||||
shiftleft,8,11556,0.093322,577.220004,841.762,0.056739776
|
||||
shiftleft,8,11778,0.091769,674.240011,1.04,0.064513607
|
||||
shiftleft,8,12000,0.088725,724.220008,1.1,0.06760845
|
||||
shiftleft,8,13333,0.085966,939.82001,1.56,0.106683806
|
||||
shiftleft,8,15000,0.087055,827.120012,1.35,0.09924269999999999
|
||||
shiftleft,8,15556,0.084214,738.920012,1.13,0.08665620599999999
|
||||
shiftleft,8,20000,0.100914,757.540012,1.26,0.136435728
|
||||
shiftleft,8,5000,0.198975,154.840003,31.052,0.007421767500000001
|
||||
shiftleft,8,6667,0.149837,177.380003,48.381,0.0092299592
|
||||
shiftleft,8,7500,0.132768,218.540002,147.871,0.020844576
|
||||
shiftleft,8,8889,0.112426,236.180002,193.721,0.024059163999999997
|
||||
|
|
13
synthDC/ppaFitting.csv
Normal file
13
synthDC/ppaFitting.csv
Normal file
@ -0,0 +1,13 @@
|
||||
Module,Metric,Freq,1,N,N^2,log2(N),Nlog2(N),R^2
|
||||
add,delay,5000,-0.038978555556527635,-0.08911531250030817,-0.00012953428819478948,0.2083593333340971,0.013950093750045424,1.0
|
||||
add,area,5000,-1913.1778463362505,-268.21377075092175,-0.4100347526051751,1046.9667200022955,47.59125331263557,1.0
|
||||
add,area,10,-13.720001333167332,14.700000312552621,1.3021426840869221e-09,-1.3062278840780171e-10,-9.375775472819561e-08,1.0
|
||||
mult,delay,5000,-0.2915958888891911,-0.02828693750009581,-3.445876736121953e-05,0.32169033333357117,0.0044735312500140964,1.0
|
||||
mult,area,5000,27780.605184113756,10418.196477973508,26.857274703166343,-24448.387256089416,-1468.2850310678027,1.0
|
||||
mult,area,10,-6472.791005245042,-2075.5787013197305,8.20962684330778,5345.246556351299,313.5693677823146,1.0
|
||||
comparator,delay,5000,0.1903951111111219,0.000987500000002994,3.427951388890516e-06,3.333333324460974e-06,-0.00012593750000039925,1.0
|
||||
comparator,area,5000,-508.51109056188875,-579.7924890645068,-1.0888888741341944,969.5466443383111,101.5524983752957,1.0
|
||||
comparator,area,10,-155.6022268893253,-40.3637507501383,-0.07230902908001494,132.9533363336765,8.452500156270371,1.0
|
||||
shifter,delay,5000,0.06953233333235516,-0.08957893750031035,-0.00015877864583368578,0.16727300000076853,0.014763625000045773,1.0
|
||||
shifter,area,5000,-237.48663487568587,1208.7075255666841,1.5708073263938906,-1678.7400476770383,-166.69187856311666,1.0
|
||||
shifter,area,10,-1079.4155736731122,-591.3687615645423,-0.877491337241916,1211.9333560050677,103.11437703155087,1.0
|
|
75
synthDC/ppaSynth.py
Executable file
75
synthDC/ppaSynth.py
Executable file
@ -0,0 +1,75 @@
|
||||
#!/usr/bin/python3
|
||||
# Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22
|
||||
|
||||
import subprocess
|
||||
import re
|
||||
from multiprocessing import Pool
|
||||
|
||||
|
||||
def runCommand(module, width, tech, freq):
|
||||
command = "make synth DESIGN=ppa_{}_{} TECH={} DRIVE=INV FREQ={} MAXOPT=1".format(module, width, tech, freq)
|
||||
subprocess.Popen(command, shell=True)
|
||||
|
||||
def deleteRedundant(LoT):
|
||||
'''removes any previous runs for the current synthesis specifications'''
|
||||
synthStr = "rm -rf runs/ppa_{}_{}_rv32e_{}nm_{}_*"
|
||||
for synth in LoT:
|
||||
bashCommand = synthStr.format(*synth)
|
||||
outputCPL = subprocess.check_output(['bash','-c', bashCommand])
|
||||
|
||||
def getData():
|
||||
bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*"
|
||||
outputCPL = subprocess.check_output(['bash','-c', bashCommand])
|
||||
linesCPL = outputCPL.decode("utf-8").split('\n')[:-1]
|
||||
|
||||
cpl = re.compile('\d{1}\.\d{6}')
|
||||
f = re.compile('_\d*_MHz')
|
||||
wm = re.compile('ppa_\w*_\d*_qor')
|
||||
|
||||
allSynths = []
|
||||
|
||||
for i in range(len(linesCPL)):
|
||||
line = linesCPL[i]
|
||||
mwm = wm.findall(line)[0][4:-4].split('_')
|
||||
freq = int(f.findall(line)[0][1:-4])
|
||||
delay = float(cpl.findall(line)[0])
|
||||
mod = mwm[0]
|
||||
width = int(mwm[1])
|
||||
|
||||
oneSynth = [mod, width, freq, delay]
|
||||
allSynths += [oneSynth]
|
||||
|
||||
return allSynths
|
||||
|
||||
allSynths = getData()
|
||||
arr = [-40, -20, -8, -6, -4, -2, 0, 2, 4, 6, 8, 10, 14, 20, 40]
|
||||
|
||||
widths = [8]
|
||||
modules = ['decoder']
|
||||
tech = 'sky90'
|
||||
LoT = []
|
||||
|
||||
## initial sweep to get estimate of min delay
|
||||
# freqs = ['17200']
|
||||
# for module in modules:
|
||||
# for width in widths:
|
||||
# for freq in freqs:
|
||||
# LoT += [[module, width, tech, freq]]
|
||||
|
||||
# thorough sweep based on estimate of min delay
|
||||
for m in modules:
|
||||
for w in widths:
|
||||
delays = []
|
||||
for oneSynth in allSynths:
|
||||
if (oneSynth[0] == m) & (oneSynth[1] == w):
|
||||
delays += [oneSynth[3]]
|
||||
try: f = 1000/min(delays)
|
||||
except: print(m)
|
||||
for freq in [str(round(f+f*x/100)) for x in arr]:
|
||||
LoT += [[m, w, tech, freq]]
|
||||
|
||||
deleteRedundant(LoT)
|
||||
|
||||
pool = Pool()
|
||||
pool.starmap(runCommand, LoT)
|
||||
pool.close()
|
@ -137,6 +137,10 @@ if {$tech == "sky130"} {
|
||||
# Set the wire load model
|
||||
set_wire_load_mode "top"
|
||||
|
||||
# Set switching activities
|
||||
# default activity factors are 1 for clocks, 0.1 for others
|
||||
# static probability of 0.5 is used for leakage
|
||||
|
||||
# Attempt Area Recovery - if looking for minimal area
|
||||
# set_max_area 2000
|
||||
|
||||
@ -359,4 +363,4 @@ redirect $filename { report_constraint }
|
||||
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"]
|
||||
# redirect $filename { report_hierarchy }
|
||||
|
||||
quit
|
||||
#quit
|
||||
|
Loading…
Reference in New Issue
Block a user