- created new testbench file instead of having it at the bottom of the srt file

- uses unpacker to parse 64 bit floating point numbers
- updated testbench to read from new testvectors generated by exptestbench

Notes:
MEM_WIDTH updated to be 64*3
Input numbers and output result is 64 bit number
MEM_SIZE set to 60000

pipelined/srt/testbench.sv

@@ -40,33 +40,66 @@ module testbench;
   logic         clk;
   logic        req;
   logic         done;
-  logic [51:0] a;
-  logic [51:0] b;
-  logic  [51:0] r;
+  logic [63:0] a;
+  logic [63:0] b;
+  logic [63:0] result;
+  logic [51:0] r;
   logic [54:0] rp, rm;   // positive quotient digits
+  logic [10:0] e; // output exponent
  
+  // input logic for Unpacker
+  // input logic  [63:0] X, Y, Z,  - numbers
+  // input logic         FmtE,  ---- format, 1 is for double precision, 0 is single
+  // input logic  [2:0]  FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide
+  // all variables are commented in fpu.sv
+
+  // output logic from Unpacker
+  logic        XSgnE, YSgnE, ZSgnE;
+  logic [10:0] XExpE, YExpE, ZExpE; // exponent
+  logic [52:0] XManE, YManE, ZManE;
+  logic XNormE;
+  logic XNaNE, YNaNE, ZNaNE;
+  logic XSNaNE, YSNaNE, ZSNaNE;
+  logic XDenormE, YDenormE, ZDenormE; // denormals
+  logic XZeroE, YZeroE, ZZeroE;
+  logic [10:0] BiasE; // currrently hardcoded, will probs be removed
+  logic XInfE, YInfE, ZInfE;
+  logic XExpMaxE; // says exponent is all ones, can ignore
+
   // Test parameters
-  parameter MEM_SIZE = 40000;
-  parameter MEM_WIDTH = 52+52+52;
+  parameter MEM_SIZE = 60000;
+  parameter MEM_WIDTH = 64+64+64;
  
-  `define memr  51:0
-  `define memb  103:52
-  `define mema  155:104
+  `define memr  63:0
+  `define memb  127:64
+  `define mema  191:128
 
   // Test logicisters
   logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE];  // Space for input file
   logic [MEM_WIDTH-1:0] Vec;  // Verilog doesn't allow direct access to a
                             // bit field of an array 
-  logic    [51:0] correctr, nextr, diffn, diffp;
+  logic    [63:0] correctr, nextr, diffn, diffp;
   integer testnum, errors;
 
+  // Unpacker
+  // Note: BiasE will probably get taken out eventually
+  unpacking unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0),
+                  .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE),
+                  .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE),
+                  .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE),
+                  .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .BiasE(BiasE),
+                  .XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE));
+
   // Divider
   srt  #(52) srt(.clk, .Start(req), 
                 .Stall(1'b0), .Flush(1'b0), 
-                .SrcXFrac(a), .SrcYFrac(b), 
+                .SrcXExpE(XExpE), .SrcYExpE(YExpE),
+                .SrcXFrac(XManE[51:0]), .SrcYFrac(YManE[51:0]), 
                 .SrcA('0), .SrcB('0), .Fmt(2'b00), 
                 .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), 
-                .Quot(r), .Rem(), .Flags());
+                .Quot(r), .Rem(), .Exp(e), .Flags());
+
+  assign result = {1'b0, e, r};
 
   // Counter
   counter counter(clk, req, done);
@@ -100,16 +133,17 @@ module testbench;
       if (done) 
 	begin
 	  req <= #5 1;
-    diffp = correctr - r;
-    diffn = r - correctr;
+    diffp = correctr - result;
+    diffn = result - correctr;
 	  if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
 	    begin
 	      errors = errors+1;
-	      $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp);
+	      $display("result was %h, should be %h %h %h\n", result, correctr, diffn, diffp);
 	      $display("failed\n");
+        $display(testnum);
 	      $stop;
 	    end
-	  if (a === 52'hxxxxxxxxxxxxx)
+	  if (a === 64'hxxxxxxxxxxxxxxxx)
 	    begin
  	      $display("%d Tests completed successfully", testnum);
 	      $stop;
@@ -121,7 +155,7 @@ module testbench;
 	  correctr = nextr;
 	  testnum = testnum+1;
 	  Vec = Tests[testnum];
-	  $display("a = %h  b = %h",a,b);
+	  $display("a = %h  b = %h result = %h",a,b,nextr);
 	  a = Vec[`mema];
 	  b = Vec[`memb];
 	  nextr = Vec[`memr];