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Increased uart baud rate to 230400.

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Added uart signals to debugger.
This commit is contained in:
Ross Thompson 2022-04-17 15:23:39 -05:00
parent 57358c884e
commit c16dec88de
3 changed files with 92 additions and 158 deletions
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67
fpga/constraints/debug2.xdc
View File

@ -743,3 +743,70 @@ create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe154]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154]
connect_debug_port u_ila_0/probe154 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 11 [get_debug_ports u_ila_0/probe155]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155]
connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[10]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe156]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156]
connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxparityerr} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe157]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157]
connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/rxstate[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe158]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158]
connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/txstate[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe159]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159]
connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe160]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160]
connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe161]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161]
connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe162]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162]
connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe163]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163]
connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe164]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164]
connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore/uart.uart/u/IER[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe165]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165]
connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 5 [get_debug_ports u_ila_0/probe166]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166]
connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[4]} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe167]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167]
connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[7]} ]]

153
fpga/generator/wave_config.wcfg
View File

@ -10,14 +10,14 @@
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="16385fs"></ZoomEndTime>
<Cursor1Time time="6fs"></Cursor1Time>
<ZoomEndTime time="168fs"></ZoomEndTime>
<Cursor1Time time="0fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="452"></NameColumnWidth>
<ValueColumnWidth column_width="145"></ValueColumnWidth>
<ValueColumnWidth column_width="141"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="29" />
<WVObjectSize size="11" />
<wave_markers>
</wave_markers>
<wvobject type="array" fp_name="wallypipelinedsoc/core/PCM">
@ -53,7 +53,6 @@
<wvobject type="group" fp_name="group468">
<obj_property name="label">CPU to LSU</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
@ -111,7 +110,6 @@
<wvobject type="group" fp_name="group470">
<obj_property name="label">PLIC</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/requests">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/requests[12:1]</obj_property>
@ -140,7 +138,6 @@
<wvobject type="group" fp_name="group471">
<obj_property name="label">interrupts</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
<obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
@ -178,7 +175,6 @@
<wvobject type="group" fp_name="group463">
<obj_property name="label">LSU to Bus</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUBusRead">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusRead</obj_property>
@ -312,7 +308,6 @@
<wvobject type="group" fp_name="group487">
<obj_property name="label">sdc</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q</obj_property>
@ -352,144 +347,4 @@
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11:0]</obj_property>
<obj_property name="ObjectShortName">IP_REGW_writeable[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM</obj_property>
<obj_property name="ObjectShortName">MExtIntM</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM</obj_property>
<obj_property name="ObjectShortName">SExtIntM</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM</obj_property>
<obj_property name="ObjectShortName">SwIntM</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM</obj_property>
<obj_property name="ObjectShortName">TimerIntM</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
<obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
<obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIMECMP">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63:0]</obj_property>
<obj_property name="ObjectShortName">MTIMECMP[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIME">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIME[63:0]</obj_property>
<obj_property name="ObjectShortName">MTIME[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intEn[1]__0">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10:1]</obj_property>
<obj_property name="ObjectShortName">intEn[1]__0[10:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
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</wave_config>

30
pipelined/src/uncore/uartPC16550D.sv
View File

@ -54,14 +54,22 @@ module uartPC16550D(
output logic SOUT, RTSb, DTRb, OUT1b, OUT2b
);
// signal to watch
// rxparityerr, RXBR[upper 3 bits]
// LSR bits 1 to 4 are based on parity, overrun, and framing errors
// txstate, rxstate
// loop, fifoenabled
// IER, RCR, MCR, LSR, MSR, DLL, DLM, RBR
// transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
// Registers
logic [10:0] RBR;
logic [7:0] FCR, LCR, LSR, SCR, DLL, DLM;
logic [3:0] IER, MSR;
logic [4:0] MCR;
(* mark_debug = "true" *) logic [10:0] RBR;
(* mark_debug = "true" *) logic [7:0] FCR, LCR, LSR, SCR, DLL, DLM;
(* mark_debug = "true" *) logic [3:0] IER, MSR;
(* mark_debug = "true" *) logic [4:0] MCR;
// Syncrhonized and delayed UART signals
logic SINd, DSRbd, DCDbd, CTSbd, RIbd;
@ -78,7 +86,7 @@ module uartPC16550D(
logic [16+`UART_PRESCALE-1:0] baudcount;
logic [3:0] rxoversampledcnt, txoversampledcnt; // count oversampled-by-16
logic [3:0] rxbitsreceived, txbitssent;
statetype rxstate, txstate;
(* mark_debug = "true" *) statetype rxstate, txstate;
// shift registrs and FIFOs
logic [9:0] rxshiftreg;
@ -90,11 +98,11 @@ module uartPC16550D(
logic [3:0] rxbitsexpected, txbitsexpected;
// receive data
logic [10:0] RXBR;
(* mark_debug = "true" *) logic [10:0] RXBR;
logic [6:0] rxtimeoutcnt;
logic rxcentered;
logic rxparity, rxparitybit, rxstopbit;
logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
(* mark_debug = "true" *) logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
logic rxdataready;
logic rxfifoempty, rxfifotriggered, rxfifotimeout;
logic rxfifodmaready;
@ -145,7 +153,8 @@ module uartPC16550D(
if (`FPGA) begin
//DLL <= #1 8'd38; // 35Mhz
//DLL <= #1 8'd11; // 10 Mhz
DLL <= #1 8'd33; // 30 Mhz
//DLL <= #1 8'd33; // 30 Mhz
DLL <= #1 8'd8; // 30 Mhz 230400
DLM <= #1 8'b0;
end else begin
DLL <= #1 8'd1; // this cannot be zero with DLM also zer0.
@ -162,10 +171,13 @@ module uartPC16550D(
3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0];
-----/\----- EXCLUDED -----/\----- */
// *** BUG FIX ME for now for the divider to be 38. Our clock is 35 Mhz. 35Mhz /(38 * 16) ~= 57600 baud, which is close enough to 57600 baud
// dll = freq / (baud * 16)
// 30Mhz / (57600 * 16) = 32.5
// 30Mhz / (230400 * 16) = 8.13
// freq /baud / 16 = div
//3'b000: if (DLAB) DLL <= #1 8'd38; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
//3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in
3'b000: if (DLAB) DLL <= #1 8'd33; //else TXHR <= #1 Din; // TX handled in
3'b000: if (DLAB) DLL <= #1 8'd8; //else TXHR <= #1 Din; // TX handled in
3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0];
3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing