mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-01 17:34:27 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
This commit is contained in:
Katherine Parry
commit
70d2b2fdd7
@ -11,8 +11,8 @@ sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \
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$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
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ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
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ARCH := rv$(XLEN)im
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PORT_CFLAGS = -g -march=rv$(XLEN)im -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
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-mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -funroll-all-loops -finline-functions -falign-jumps=4 \
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PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
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-mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \
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-fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \
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-funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fipa-pta \
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-nostdlib -nostartfiles -ffreestanding -mstrict-align \
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@ -4,7 +4,8 @@
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embench_dir = ../../addins/embench-iot
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all: build sim size
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all: build
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run: sim size
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allClean: clean all
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@ -49,24 +49,24 @@ string tvpaths[] = '{
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`EMBENCH,
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"bd_speedopt_speed/src/aha-mont64/aha-mont64",
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"bd_speedopt_speed/src/crc32/crc32",
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"bd_speedopt_speed/src/cubic/cubic",
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"bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
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"bd_speedopt_speed/src/edn/edn",
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"bd_speedopt_speed/src/huffbench/huffbench",
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"bd_speedopt_speed/src/matmult-int/matmult-int",
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"bd_speedopt_speed/src/md5sum/md5sum",
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// "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back
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"bd_speedopt_speed/src/minver/minver",
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"bd_speedopt_speed/src/nbody/nbody",
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"bd_speedopt_speed/src/nettle-aes/nettle-aes",
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"bd_speedopt_speed/src/nettle-sha256/nettle-sha256",
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"bd_speedopt_speed/src/nsichneu/nsichneu",
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"bd_speedopt_speed/src/picojpeg/picojpeg",
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"bd_speedopt_speed/src/primecount/primecount",
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// "bd_speedopt_speed/src/primecount/primecount",
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"bd_speedopt_speed/src/qrduino/qrduino",
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"bd_speedopt_speed/src/sglib-combined/sglib-combined",
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"bd_speedopt_speed/src/slre/slre",
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"bd_speedopt_speed/src/st/st",
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"bd_speedopt_speed/src/statemate/statemate",
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"bd_speedopt_speed/src/tarfind/tarfind",
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// "bd_speedopt_speed/src/tarfind/tarfind",
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"bd_speedopt_speed/src/ud/ud",
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"bd_speedopt_speed/src/wikisort/wikisort",
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"bd_sizeopt_speed/src/aha-mont64/aha-mont64",
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@ -75,7 +75,7 @@ string tvpaths[] = '{
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"bd_sizeopt_speed/src/edn/edn",
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"bd_sizeopt_speed/src/huffbench/huffbench",
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"bd_sizeopt_speed/src/matmult-int/matmult-int",
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"bd_sizeopt_speed/src/md5sum/md5sum",
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// "bd_sizeopt_speed/src/md5sum/md5sum",
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"bd_sizeopt_speed/src/minver/minver",
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"bd_sizeopt_speed/src/nbody/nbody",
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"bd_sizeopt_speed/src/nettle-aes/nettle-aes",
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@ -88,7 +88,7 @@ string tvpaths[] = '{
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"bd_sizeopt_speed/src/slre/slre",
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"bd_sizeopt_speed/src/st/st",
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"bd_sizeopt_speed/src/statemate/statemate",
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"bd_sizeopt_speed/src/tarfind/tarfind",
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// "bd_sizeopt_speed/src/tarfind/tarfind",
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"bd_sizeopt_speed/src/ud/ud",
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"bd_sizeopt_speed/src/wikisort/wikisort"
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};
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@ -973,6 +973,45 @@ readsip_test: // read the MIP into the signature
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addi a6, a6, 4
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j test_loop // go to next test case
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claim_m_plic_interrupts: // clears one non-pending PLIC interrupt
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li t2, 0x0C002000
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li t3, 0x0C200004
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li t4, 0xFFF
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lw t6, 0(t2) // save current enable status
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sw t4, 0(t2) // enable all relevant interrupts on PLIC
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lw t5, 0(t3) // make PLIC claim
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sw t5, 0(t3) // complete claim made
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sw t6, 0(t2) // restore saved enable status
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j test_loop
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claim_s_plic_interrupts: // clears one non-pending PLIC interrupt
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li t2, 0x0C002080
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li t3, 0x0C201004
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li t4, 0xFFF
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lw t6, 0(t2) // save current enable status
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sw t4, 0(t2) // enable all relevant interrupts on PLIC
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lw t5, 0(t3) // make PLIC claim
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sw t5, 0(t3) // complete claim made
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sw t6, 0(t2) // restore saved enable status
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j test_loop
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uart_data_wait:
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li t2, 0x10000005 // LSR
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li t3, 0x10000002 // IIR
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lb t4, 0(t3) // save IIR before potential clear
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lb t5, 0(t2)
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andi t5, t5, 1 // only care if data is ready
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li t6, 1
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beq t5, t6, uart_data_ready
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j uart_data_wait
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uart_data_ready:
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sb t4, 0(t1)
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sb t5, 1(t1)
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addi t1, t1, 4
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addi a6, a6, 4
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j test_loop
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goto_s_mode:
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// return to address in t3,
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li a0, 3 // Trap handler behavior (go to supervisor mode)
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@ -140,18 +140,22 @@ SETUP_PLIC
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.4byte high_ie, 0x00020000, write32_test # enable high interrupt on bit 17, which is pending
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.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised
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.4byte high_ie, 0x00000000, write32_test # disable high interrupt on bit 17
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts
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.4byte 0x0, 0x00000000, readmip_test # MEIP should be released
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.4byte low_ie, 0x00010000, write32_test # enable low interrupt on bit 16, which is pending
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.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised
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.4byte low_ie, 0x00000000, write32_test # disable low interrupt on bit 16
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts
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.4byte 0x0, 0x00000000, readmip_test # MEIP should be released
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.4byte rise_ie, 0x00200000, write32_test # enable rise interrupt on bit 21, which is pending
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.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised
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.4byte rise_ie, 0x00000000, write32_test # disable rise interrupt on bit 21, which is pending
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts
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.4byte 0x0, 0x00000000, readmip_test # MEIP should be released
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.4byte fall_ie, 0x01000000, write32_test # enable high interrupt on bit 24, which is pending
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.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised
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.4byte fall_ie, 0x00000000, write32_test # disable high interrupt on bit 24, which is pending
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts
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.4byte 0x0, 0x00000000, readmip_test # MEIP should be released
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.4byte 0x0, 0x0, terminate_test # terminate tests
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