Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

pipelined/src/fma/fma16_template.sv

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+// fma16.sv
+// David_Harris@hmc.edu 26 February 2022
+// 16-bit floating-point multiply-accumulate
+
+// Operation: general purpose multiply, add, fma, with optional negation
+//   If mul=1, p = x * y.  Else p = x.
+//   If add=1, result = p + z.  Else result = p.
+//   If negr or negz = 1, negate result or z to handle negations and subtractions
+//   fadd: mul = 0, add = 1, negr = negz = 0
+//   fsub: mul = 0, add = 1, negr = 0, negz = 1
+//   fmul: mul = 1, add = 0, negr = 0, negz = 0
+//   fmadd:  mul = 1, add = 1, negr = 0, negz = 0
+//   fmsub:  mul = 1, add = 1, negr = 0, negz = 1
+//   fnmadd: mul = 1, add = 1, negr = 1, negz = 0
+//   fnmsub: mul = 1, add = 1, negr = 1, negz = 1
+
+module fma16(
+  input  logic [15:0] x, y, z,
+  input  logic        mul, add, negr, negz,
+  input  logic [1:0]  roundmode,  // 00: rz, 01: rne, 10: rp, 11: rn
+  output logic [15:0] result);
+ 
+endmodule
+