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https://github.com/openhwgroup/cvw
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Mostly removed N_SUPPORTED
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@ -111,14 +111,5 @@ module csri #(parameter
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SIP_REGW = 12'b0;
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SIE_REGW = 12'b0;
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end
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// User Modes iterrupts depricated
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/*if (`U_SUPPORTED & `N_SUPPORTED) begin
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UIP_REGW = IP_REGW & MIDELEG_REGW & SIDELEG_REGW & 'h111; // only delegated interrupts visible
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UIE_REGW = IE_REGW & MIDELEG_REGW & SIDELEG_REGW & 'h111; // only delegated interrupts visible
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end else begin
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UIP_REGW = 12'b0;
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UIE_REGW = 12'b0;
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end */
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end
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endmodule
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@ -146,7 +146,7 @@ module csrm #(parameter
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// CSRs
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flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW);
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if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin:deleg // DELEG registers should exist
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if (`S_SUPPORTED) begin:deleg // DELEG registers should exist
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flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK /*12'h7FF*/, MEDELEG_REGW);
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flopenr #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK /*12'h222*/, MIDELEG_REGW);
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end else assign {MEDELEG_REGW, MIDELEG_REGW} = 0;
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@ -165,8 +165,7 @@ module csrm #(parameter
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logic [5:0] entry;
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always_comb begin
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entry = '0;
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IllegalCSRMAccessM = !(`S_SUPPORTED | `U_SUPPORTED & `N_SUPPORTED) &
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(CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
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IllegalCSRMAccessM = !(`S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
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if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + `PMP_ENTRIES) // reading a PMP entry
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CSRMReadValM = PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0];
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else if (CSRAdrM >= PMPCFG0 & CSRAdrM < PMPCFG0 + `PMP_ENTRIES/4) begin
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@ -84,7 +84,6 @@ module trap (
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assign TrapM = ExceptionM | InterruptM; // *** clean this up later DH
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assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
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assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
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assign UTrapM = TrapM & (NextPrivilegeModeM == `U_MODE) & `N_SUPPORTED;
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assign RetM = mretM | sretM;
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always_comb
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