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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-04-19 14:09:50 -05:00
commit 546ef08eb2
59 changed files with 6498 additions and 633 deletions
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74
fpga/constraints/debug2.xdc
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File diff suppressed because one or more lines are too long

153
fpga/generator/wave_config.wcfg
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@ -10,14 +10,14 @@
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="16385fs"></ZoomEndTime>
<Cursor1Time time="6fs"></Cursor1Time>
<ZoomEndTime time="168fs"></ZoomEndTime>
<Cursor1Time time="0fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="452"></NameColumnWidth>
<ValueColumnWidth column_width="145"></ValueColumnWidth>
<ValueColumnWidth column_width="141"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="29" />
<WVObjectSize size="11" />
<wave_markers>
</wave_markers>
<wvobject type="array" fp_name="wallypipelinedsoc/core/PCM">
@ -53,7 +53,6 @@
<wvobject type="group" fp_name="group468">
<obj_property name="label">CPU to LSU</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
@ -111,7 +110,6 @@
<wvobject type="group" fp_name="group470">
<obj_property name="label">PLIC</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/requests">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/requests[12:1]</obj_property>
@ -140,7 +138,6 @@
<wvobject type="group" fp_name="group471">
<obj_property name="label">interrupts</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
<obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
@ -178,7 +175,6 @@
<wvobject type="group" fp_name="group463">
<obj_property name="label">LSU to Bus</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUBusRead">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusRead</obj_property>
@ -312,7 +308,6 @@
<wvobject type="group" fp_name="group487">
<obj_property name="label">sdc</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q</obj_property>
@ -352,144 +347,4 @@
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11:0]</obj_property>
<obj_property name="ObjectShortName">IP_REGW_writeable[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM</obj_property>
<obj_property name="ObjectShortName">MExtIntM</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM</obj_property>
<obj_property name="ObjectShortName">SExtIntM</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM</obj_property>
<obj_property name="ObjectShortName">SwIntM</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM</obj_property>
<obj_property name="ObjectShortName">TimerIntM</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
<obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
<obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIMECMP">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63:0]</obj_property>
<obj_property name="ObjectShortName">MTIMECMP[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIME">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIME[63:0]</obj_property>
<obj_property name="ObjectShortName">MTIME[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intEn[1]__0">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10:1]</obj_property>
<obj_property name="ObjectShortName">intEn[1]__0[10:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intPriority[10]">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intPriority[10][2:0]</obj_property>
<obj_property name="ObjectShortName">intPriority[10][2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1]">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10:1]</obj_property>
<obj_property name="ObjectShortName">irqMatrix[1][1][10:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2]">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10:1]</obj_property>
<obj_property name="ObjectShortName">irqMatrix[1][2][10:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3]">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10:1]</obj_property>
<obj_property name="ObjectShortName">irqMatrix[1][3][10:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4]">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10:1]</obj_property>
<obj_property name="ObjectShortName">irqMatrix[1][4][10:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5]">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10:1]</obj_property>
<obj_property name="ObjectShortName">irqMatrix[1][5][10:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6]">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10:1]</obj_property>
<obj_property name="ObjectShortName">irqMatrix[1][6][10:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7]">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10:1]</obj_property>
<obj_property name="ObjectShortName">irqMatrix[1][7][10:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
</wave_config>

5
pipelined/config/buildroot/wally-config.vh
View File

@ -78,6 +78,9 @@
// Address space
`define RESET_VECTOR 64'h0000000000001000
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 20
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@ -126,6 +129,8 @@
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 1

5
pipelined/config/fpga/wally-config.vh
View File

@ -79,6 +79,9 @@
// Address space
`define RESET_VECTOR 64'h0000000000001000
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 20
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@ -134,6 +137,8 @@
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 1
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 1

4
pipelined/config/rv32e/wally-config.vh
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@ -80,6 +80,9 @@
// Address space
`define RESET_VECTOR 32'h80000000
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 20
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@ -131,6 +134,7 @@
`define BPRED_ENABLED 0
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

4
pipelined/config/rv32gc/wally-config.vh
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@ -78,6 +78,9 @@
// Address space
`define RESET_VECTOR 32'h80000000
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 20
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@ -129,6 +132,7 @@
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

5
pipelined/config/rv32ia/wally-config.vh
View File

@ -80,6 +80,9 @@
// Address space
`define RESET_VECTOR 32'h80000000
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 20
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@ -131,6 +134,8 @@
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

5
pipelined/config/rv32ic/wally-config.vh
View File

@ -78,6 +78,9 @@
// Address space
`define RESET_VECTOR 32'h80000000
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 20
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@ -129,6 +132,8 @@
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

7
pipelined/config/rv64BP/wally-config.vh
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@ -59,7 +59,7 @@
// TLB configuration. Entries should be a power of 2
`define ITLB_ENTRIES 32
`define DTLB_ENTRIES 32
`define DTLB_ENTRIES 32
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
@ -82,6 +82,9 @@
// Bus Interface width
`define AHBW 64
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 20
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@ -132,6 +135,8 @@
//`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
`define BPTYPE "BPGSHARE" // BPTWOBIT or "BPGLOBAL" or BPLOCALPAg or BPGSHARE
`define TESTSBP 1
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

5
pipelined/config/rv64fp/wally-config.vh
View File

@ -84,6 +84,9 @@
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 20
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
@ -130,6 +133,8 @@
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

4
pipelined/config/rv64gc/wally-config.vh
View File

@ -82,6 +82,9 @@
// Bus Interface width
`define AHBW 64
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 20
// Peripheral Physiccal Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@ -132,6 +135,7 @@
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

4
pipelined/config/rv64ia/wally-config.vh
View File

@ -82,6 +82,9 @@
// Bus Interface width
`define AHBW 64
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 20
// Peripheral Physiccal Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@ -132,6 +135,7 @@
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

4
pipelined/config/rv64ic/wally-config.vh
View File

@ -82,6 +82,9 @@
// Bus Interface width
`define AHBW 64
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 20
// Peripheral Physiccal Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@ -132,6 +135,7 @@
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

2
pipelined/regression/regression-wally
View File

@ -45,7 +45,7 @@ configs = [
)
]
def getBuildrootTC(short):
INSTR_LIMIT = 100000 # multiple of 100000
INSTR_LIMIT = 4000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
MAX_EXPECTED = 246000000
if short:
BRcmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"

0
pipelined/regression/wkdir/README
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1249
pipelined/src/fma/baby_torture.tv Normal file
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File diff suppressed because it is too large Load Diff

313
pipelined/src/fma/baby_torture_rz.tv Normal file
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@ -0,0 +1,313 @@
// Torture tests generated Tue Apr 19 15:10:52 2022 by ./torturegen.pl
////////// Testcases from f16_add_rz.tv of type add rounding mode 0
0000_0000_FA02_04_FA02_0 // f16_add_rz.tv line 500 0000_FA02_FA02_00 0 + -1.01000000010 x 2^15 = -1.01000000010 x 2^15
93FF_0000_EBFF_04_EBFF_1 // f16_add_rz.tv line 1000 93FF_EBFF_EBFF_01 -1.01111111111 x 2^-11 + -1.01111111111 x 2^11 = -1.01111111111 x 2^11
// Skipped denorm f16_add_rz.tv line 1500 03FF_C401_C400_01 Denorm + -1.00000000001 x 2^2 = -1.00000000000 x 2^2
// Skipped denorm f16_add_rz.tv line 2000 03FE_0001_03FF_00 Denorm + Denorm = Denorm
54CE_0000_BC00_04_54BE_0 // f16_add_rz.tv line 2500 54CE_BC00_54BE_00 1.00011001110 x 2^6 + -1.00000000000 x 2^0 = 1.00010111110 x 2^6
0401_0000_B7FE_04_B7FD_1 // f16_add_rz.tv line 3000 0401_B7FE_B7FD_01 1.00000000001 x 2^-14 + -1.01111111110 x 2^-2 = -1.01111111101 x 2^-2
07FF_0000_C3FF_04_C3FE_1 // f16_add_rz.tv line 3500 07FF_C3FF_C3FE_01 1.01111111111 x 2^-14 + -1.01111111111 x 2^1 = -1.01111111110 x 2^1
9C3B_0000_87FF_04_9C5A_1 // f16_add_rz.tv line 4000 9C3B_87FF_9C5A_01 -1.00000111011 x 2^-8 + -1.01111111111 x 2^-14 = -1.00001011010 x 2^-8
// Skipped denorm f16_add_rz.tv line 4500 1000_8001_0FFF_01 1.00000000000 x 2^-11 + -Denorm = 1.01111111111 x 2^-12
1001_0000_2FBB_04_2FC3_1 // f16_add_rz.tv line 5000 1001_2FBB_2FC3_01 1.00000000001 x 2^-11 + 1.01110111011 x 2^-4 = 1.01111000011 x 2^-4
37EE_0000_7800_04_7800_1 // f16_add_rz.tv line 5500 37EE_7800_7800_01 1.01111101110 x 2^-2 + 1.00000000000 x 2^15 = 1.00000000000 x 2^15
13FE_0000_47FE_04_47FE_1 // f16_add_rz.tv line 6000 13FE_47FE_47FE_01 1.01111111110 x 2^-11 + 1.01111111110 x 2^2 = 1.01111111110 x 2^2
3400_0000_CA47_04_CA27_0 // f16_add_rz.tv line 6500 3400_CA47_CA27_00 1.00000000000 x 2^-2 + -1.01001000111 x 2^3 = -1.01000100111 x 2^3
30EE_0000_3FFF_04_404E_1 // f16_add_rz.tv line 7000 30EE_3FFF_404E_01 1.00011101110 x 2^-3 + 1.01111111111 x 2^0 = 1.00001001110 x 2^1
37FF_0000_3801_04_3C00_1 // f16_add_rz.tv line 7500 37FF_3801_3C00_01 1.01111111111 x 2^-2 + 1.00000000001 x 2^-1 = 1.00000000000 x 2^0
37FE_0000_B783_04_27B0_0 // f16_add_rz.tv line 8000 37FE_B783_27B0_00 1.01111111110 x 2^-2 + -1.01110000011 x 2^-2 = 1.01110110000 x 2^-6
0EBE_0000_1000_04_135F_0 // f16_add_rz.tv line 8500 0EBE_1000_135F_00 1.01010111110 x 2^-12 + 1.00000000000 x 2^-11 = 1.01101011111 x 2^-11
// Skipped denorm f16_add_rz.tv line 9000 3801_03FE_3801_01 1.00000000001 x 2^-1 + Denorm = 1.00000000001 x 2^-1
3801_0000_480F_04_484F_1 // f16_add_rz.tv line 9500 3801_480F_484F_01 1.00000000001 x 2^-1 + 1.00000001111 x 2^3 = 1.00001001111 x 2^3
// Skipped denorm f16_add_rz.tv line 10000 003E_FBFF_FBFE_01 Denorm + -1.01111111111 x 2^15 = -1.01111111110 x 2^15
3BFE_0000_E801_04_E800_1 // f16_add_rz.tv line 10500 3BFE_E801_E800_01 1.01111111110 x 2^-1 + -1.00000000001 x 2^11 = -1.00000000000 x 2^11
3C00_0000_88D3_04_3BFF_1 // f16_add_rz.tv line 11000 3C00_88D3_3BFF_01 1.00000000000 x 2^0 + -1.00011010011 x 2^-13 = 1.01111111111 x 2^-1
257F_0000_C000_04_BFEA_1 // f16_add_rz.tv line 11500 257F_C000_BFEA_01 1.00101111111 x 2^-6 + -1.00000000000 x 2^1 = -1.01111101010 x 2^0
3FFF_0000_BBFE_04_3C00_0 // f16_add_rz.tv line 12000 3FFF_BBFE_3C00_00 1.01111111111 x 2^0 + -1.01111111110 x 2^-1 = 1.00000000000 x 2^0
3FFE_0000_4AFD_04_4BFC_1 // f16_add_rz.tv line 12500 3FFE_4AFD_4BFC_01 1.01111111110 x 2^0 + 1.01011111101 x 2^3 = 1.01111111100 x 2^3
B7FF_0000_93FF_04_B801_1 // f16_add_rz.tv line 13000 B7FF_93FF_B801_01 -1.01111111111 x 2^-2 + -1.01111111111 x 2^-11 = -1.00000000001 x 2^-1
4001_0000_8401_04_4000_1 // f16_add_rz.tv line 13500 4001_8401_4000_01 1.00000000001 x 2^1 + -1.00000000001 x 2^-14 = 1.00000000000 x 2^1
43FF_0000_3808_04_4480_1 // f16_add_rz.tv line 14000 43FF_3808_4480_01 1.01111111111 x 2^1 + 1.00000001000 x 2^-1 = 1.00010000000 x 2^2
AC0A_0000_7C00_04_7C00_0 // f16_add_rz.tv line 14500 AC0A_7C00_7C00_00 -1.00000001010 x 2^-4 + INF = INF
4400_0000_6BFE_04_6C00_0 // f16_add_rz.tv line 15000 4400_6BFE_6C00_00 1.00000000000 x 2^2 + 1.01111111110 x 2^11 = 1.00000000000 x 2^12
4401_0000_D3F2_04_D371_1 // f16_add_rz.tv line 15500 4401_D3F2_D371_01 1.00000000001 x 2^2 + -1.01111110010 x 2^5 = -1.01101110001 x 2^5
5BC2_0000_43FF_04_5BE1_1 // f16_add_rz.tv line 16000 5BC2_43FF_5BE1_01 1.01111000010 x 2^7 + 1.01111111111 x 2^1 = 1.01111100001 x 2^7
47FE_0000_3C01_04_487F_1 // f16_add_rz.tv line 16500 47FE_3C01_487F_01 1.01111111110 x 2^2 + 1.00000000001 x 2^0 = 1.00001111111 x 2^3
6800_0000_13F1_04_6800_1 // f16_add_rz.tv line 17000 6800_13F1_6800_01 1.00000000000 x 2^11 + 1.01111110001 x 2^-11 = 1.00000000000 x 2^11
78FB_0000_3400_04_78FB_1 // f16_add_rz.tv line 17500 78FB_3400_78FB_01 1.00011111011 x 2^15 + 1.00000000000 x 2^-2 = 1.00011111011 x 2^15
6BFF_0000_07FE_04_6BFF_1 // f16_add_rz.tv line 18000 6BFF_07FE_6BFF_01 1.01111111111 x 2^11 + 1.01111111110 x 2^-14 = 1.01111111111 x 2^11
6BFE_0000_13FE_04_6BFE_1 // f16_add_rz.tv line 18500 6BFE_13FE_6BFE_01 1.01111111110 x 2^11 + 1.01111111110 x 2^-11 = 1.01111111110 x 2^11
382F_0000_FFFF_04_FFFF_0 // f16_add_rz.tv line 19000 382F_FFFF_FFFF_00 1.00000101111 x 2^-1 + NaN = NaN
7800_0000_F801_04_D000_0 // f16_add_rz.tv line 19500 7800_F801_D000_00 1.00000000000 x 2^15 + -1.00000000001 x 2^15 = -1.00000000000 x 2^5
7801_0000_4877_04_7801_1 // f16_add_rz.tv line 20000 7801_4877_7801_01 1.00000000001 x 2^15 + 1.00001110111 x 2^3 = 1.00000000001 x 2^15
// Skipped denorm f16_add_rz.tv line 20500 0090_C400_C3FF_01 Denorm + -1.00000000000 x 2^2 = -1.01111111111 x 2^1
7BFE_0000_BFFE_04_7BFD_1 // f16_add_rz.tv line 21000 7BFE_BFFE_7BFD_01 1.01111111110 x 2^15 + -1.01111111110 x 2^0 = 1.01111111101 x 2^15
7C00_0000_4F08_04_7C00_0 // f16_add_rz.tv line 21500 7C00_4F08_7C00_00 INF + 1.01100001000 x 2^4 = INF
BFFA_0000_B7FF_04_C0FC_1 // f16_add_rz.tv line 22000 BFFA_B7FF_C0FC_01 -1.01111111010 x 2^0 + -1.01111111111 x 2^-2 = -1.00011111100 x 2^1
7FFF_0000_9001_04_7FFF_0 // f16_add_rz.tv line 22500 7FFF_9001_7FFF_00 NaN + -1.00000000001 x 2^-11 = NaN
7FFE_0000_B82F_04_7FFE_0 // f16_add_rz.tv line 23000 7FFE_B82F_7FFE_00 NaN + -1.00000101111 x 2^-1 = NaN
// Skipped denorm f16_add_rz.tv line 23500 2F68_8000_2F68_00 1.01101101000 x 2^-4 + -Denorm = 1.01101101000 x 2^-4
// Skipped denorm f16_add_rz.tv line 24000 8001_7BFE_7BFD_01 -Denorm + 1.01111111110 x 2^15 = 1.01111111101 x 2^15
// Skipped denorm f16_add_rz.tv line 24500 83FF_EB8E_EB8E_01 -Denorm + -1.01110001110 x 2^11 = -1.01110001110 x 2^11
75FF_0000_47FF_04_75FF_1 // f16_add_rz.tv line 25000 75FF_47FF_75FF_01 1.00111111111 x 2^14 + 1.01111111111 x 2^2 = 1.00111111111 x 2^14
8400_0000_4001_04_4000_1 // f16_add_rz.tv line 25500 8400_4001_4000_01 -1.00000000000 x 2^-14 + 1.00000000001 x 2^1 = 1.00000000000 x 2^1
8401_0000_C3E7_04_C3E7_1 // f16_add_rz.tv line 26000 8401_C3E7_C3E7_01 -1.00000000001 x 2^-14 + -1.01111100111 x 2^1 = -1.01111100111 x 2^1
CC00_0000_3800_04_CBC0_0 // f16_add_rz.tv line 26500 CC00_3800_CBC0_00 -1.00000000000 x 2^4 + 1.00000000000 x 2^-1 = -1.01111000000 x 2^3
87FE_0000_13FE_04_12FE_1 // f16_add_rz.tv line 27000 87FE_13FE_12FE_01 -1.01111111110 x 2^-14 + 1.01111111110 x 2^-11 = 1.01011111110 x 2^-11
9000_0000_7FF2_04_7FF2_0 // f16_add_rz.tv line 27500 9000_7FF2_7FF2_00 -1.00000000000 x 2^-11 + NaN = NaN
// Skipped denorm f16_add_rz.tv line 28000 C082_03FF_C081_01 -1.00010000010 x 2^1 + Denorm = -1.00010000001 x 2^1
9001_0000_FC01_04_FE01_0 // f16_add_rz.tv line 28500 9001_FC01_FE01_10 -1.00000000001 x 2^-11 + NaN = NaN
93FF_0000_2DFF_04_2DEF_1 // f16_add_rz.tv line 29000 93FF_2DFF_2DEF_01 -1.01111111111 x 2^-11 + 1.00111111111 x 2^-4 = 1.00111101111 x 2^-4
BE01_0000_E800_04_E800_1 // f16_add_rz.tv line 29500 BE01_E800_E800_01 -1.01000000001 x 2^0 + -1.00000000000 x 2^11 = -1.00000000000 x 2^11
B400_0000_C3FE_04_C43F_0 // f16_add_rz.tv line 30000 B400_C3FE_C43F_00 -1.00000000000 x 2^-2 + -1.01111111110 x 2^1 = -1.00000111111 x 2^2
B401_0000_2702_04_B321_1 // f16_add_rz.tv line 30500 B401_2702_B321_01 -1.00000000001 x 2^-2 + 1.01100000010 x 2^-6 = -1.01100100001 x 2^-3
E09F_0000_BBFF_04_E0A0_1 // f16_add_rz.tv line 31000 E09F_BBFF_E0A0_01 -1.00010011111 x 2^9 + -1.01111111111 x 2^-1 = -1.00010100000 x 2^9
B7FE_0000_B401_04_B9FF_1 // f16_add_rz.tv line 31500 B7FE_B401_B9FF_01 -1.01111111110 x 2^-2 + -1.00000000001 x 2^-2 = -1.00111111111 x 2^-1
// Skipped denorm f16_add_rz.tv line 32000 B800_80BF_B800_01 -1.00000000000 x 2^-1 + -Denorm = -1.00000000000 x 2^-1
6BBC_0000_8400_04_6BBB_1 // f16_add_rz.tv line 32500 6BBC_8400_6BBB_01 1.01110111100 x 2^11 + -1.00000000000 x 2^-14 = 1.01110111011 x 2^11
BBFF_0000_7FFE_04_7FFE_0 // f16_add_rz.tv line 33000 BBFF_7FFE_7FFE_00 -1.01111111111 x 2^-1 + NaN = NaN
BBFE_0000_09DF_04_BBFD_1 // f16_add_rz.tv line 33500 BBFE_09DF_BBFD_01 -1.01111111110 x 2^-1 + 1.00111011111 x 2^-13 = -1.01111111101 x 2^-1
124E_0000_6BFF_04_6BFF_1 // f16_add_rz.tv line 34000 124E_6BFF_6BFF_01 1.01001001110 x 2^-11 + 1.01111111111 x 2^11 = 1.01111111111 x 2^11
BC01_0000_4401_04_4201_1 // f16_add_rz.tv line 34500 BC01_4401_4201_01 -1.00000000001 x 2^0 + 1.00000000001 x 2^2 = 1.01000000001 x 2^1
BFFF_0000_10BF_04_BFFE_1 // f16_add_rz.tv line 35000 BFFF_10BF_BFFE_01 -1.01111111111 x 2^0 + 1.00010111111 x 2^-11 = -1.01111111110 x 2^0
48EF_0000_3C00_04_496F_0 // f16_add_rz.tv line 35500 48EF_3C00_496F_00 1.00011101111 x 2^3 + 1.00000000000 x 2^0 = 1.00101101111 x 2^3
C000_0000_37FE_04_BE00_1 // f16_add_rz.tv line 36000 C000_37FE_BE00_01 -1.00000000000 x 2^1 + 1.01111111110 x 2^-2 = -1.01000000000 x 2^0
// Skipped denorm f16_add_rz.tv line 36500 C001_021F_C000_01 -1.00000000001 x 2^1 + Denorm = -1.00000000000 x 2^1
1180_0000_07FF_04_127F_1 // f16_add_rz.tv line 37000 1180_07FF_127F_01 1.00110000000 x 2^-11 + 1.01111111111 x 2^-14 = 1.01001111111 x 2^-11
// Skipped denorm f16_add_rz.tv line 37500 C3FE_0001_C3FD_01 -1.01111111110 x 2^1 + Denorm = -1.01111111101 x 2^1
// Skipped denorm f16_add_rz.tv line 38000 C3FE_00FF_C3FD_01 -1.01111111110 x 2^1 + Denorm = -1.01111111101 x 2^1
1A7C_0000_F800_04_F7FF_1 // f16_add_rz.tv line 38500 1A7C_F800_F7FF_01 1.01001111100 x 2^-9 + -1.00000000000 x 2^15 = -1.01111111111 x 2^14
C401_0000_C7FE_04_C9FF_1 // f16_add_rz.tv line 39000 C401_C7FE_C9FF_01 -1.00000000001 x 2^2 + -1.01111111110 x 2^2 = -1.00111111111 x 2^3
C7FF_0000_C73F_04_CB9F_0 // f16_add_rz.tv line 39500 C7FF_C73F_CB9F_00 -1.01111111111 x 2^2 + -1.01100111111 x 2^2 = -1.01110011111 x 2^3
3F10_0000_BFFF_04_B378_0 // f16_add_rz.tv line 40000 3F10_BFFF_B378_00 1.01100010000 x 2^0 + -1.01111111111 x 2^0 = -1.01101111000 x 2^-3
E800_0000_B801_04_E800_1 // f16_add_rz.tv line 40500 E800_B801_E800_01 -1.00000000000 x 2^11 + -1.00000000001 x 2^-1 = -1.00000000000 x 2^11
E801_0000_B387_04_E801_1 // f16_add_rz.tv line 41000 E801_B387_E801_01 -1.00000000001 x 2^11 + -1.01110000111 x 2^-3 = -1.00000000001 x 2^11
CBE1_0000_9000_04_CBE1_1 // f16_add_rz.tv line 41500 CBE1_9000_CBE1_01 -1.01111100001 x 2^3 + -1.00000000000 x 2^-11 = -1.01111100001 x 2^3
// Skipped denorm f16_add_rz.tv line 42000 EBFE_83FE_EBFE_01 -1.01111111110 x 2^11 + -Denorm = -1.01111111110 x 2^11
F800_0000_3F00_04_F7FF_1 // f16_add_rz.tv line 42500 F800_3F00_F7FF_01 -1.00000000000 x 2^15 + 1.01100000000 x 2^0 = -1.01111111111 x 2^14
CFBF_0000_7BFF_04_7BFE_1 // f16_add_rz.tv line 43000 CFBF_7BFF_7BFE_01 -1.01110111111 x 2^4 + 1.01111111111 x 2^15 = 1.01111111110 x 2^15
FBFF_0000_6801_04_FBBE_1 // f16_add_rz.tv line 43500 FBFF_6801_FBBE_01 -1.01111111111 x 2^15 + 1.00000000001 x 2^11 = -1.01110111110 x 2^15
FBFE_0000_11FF_04_FBFD_1 // f16_add_rz.tv line 44000 FBFE_11FF_FBFD_01 -1.01111111110 x 2^15 + 1.00111111111 x 2^-11 = -1.01111111101 x 2^15
3CD8_0000_4000_04_426C_0 // f16_add_rz.tv line 44500 3CD8_4000_426C_00 1.00011011000 x 2^0 + 1.00000000000 x 2^1 = 1.01001101100 x 2^1
FC01_0000_3BFE_04_FE01_0 // f16_add_rz.tv line 45000 FC01_3BFE_FE01_10 NaN + 1.01111111110 x 2^-1 = NaN
FFFF_0000_44F7_04_FFFF_0 // f16_add_rz.tv line 45500 FFFF_44F7_FFFF_00 NaN + 1.00011110111 x 2^2 = NaN
CB78_0000_13FF_04_CB77_1 // f16_add_rz.tv line 46000 CB78_13FF_CB77_01 -1.01101111000 x 2^3 + 1.01111111111 x 2^-11 = -1.01101110111 x 2^3
////////// Testcases from f16_mul_rz.tv of type mul rounding mode 0
0000_FA02_3CFF_08_8000_0 // f16_mul_rz.tv line 500 0000_FA02_8000_00 0 * -1.01000000010 x 2^15 = -Denorm
93FF_EBFF_3CFF_08_43FE_1 // f16_mul_rz.tv line 1000 93FF_EBFF_43FE_01 -1.01111111111 x 2^-11 * -1.01111111111 x 2^11 = 1.01111111110 x 2^1
// Skipped denorm f16_mul_rz.tv line 1500 03FF_C401_8BFF_01 Denorm * -1.00000000001 x 2^2 = -1.01111111111 x 2^-13
// Skipped denorm f16_mul_rz.tv line 2000 03FE_0001_0000_03 Denorm * Denorm = 0
54CE_BC00_3CFF_08_D4CE_0 // f16_mul_rz.tv line 2500 54CE_BC00_D4CE_00 1.00011001110 x 2^6 * -1.00000000000 x 2^0 = -1.00011001110 x 2^6
0401_B7FE_3CFF_08_81FF_3 // f16_mul_rz.tv line 3000 0401_B7FE_81FF_03 1.00000000001 x 2^-14 * -1.01111111110 x 2^-2 = -Denorm
07FF_C3FF_3CFF_08_8FFE_1 // f16_mul_rz.tv line 3500 07FF_C3FF_8FFE_01 1.01111111111 x 2^-14 * -1.01111111111 x 2^1 = -1.01111111110 x 2^-12
9C3B_87FF_3CFF_08_0008_3 // f16_mul_rz.tv line 4000 9C3B_87FF_0008_03 -1.00000111011 x 2^-8 * -1.01111111111 x 2^-14 = Denorm
// Skipped denorm f16_mul_rz.tv line 4500 1000_8001_8000_03 1.00000000000 x 2^-11 * -Denorm = -Denorm
1001_2FBB_3CFF_08_03DE_3 // f16_mul_rz.tv line 5000 1001_2FBB_03DE_03 1.00000000001 x 2^-11 * 1.01110111011 x 2^-4 = Denorm
37EE_7800_3CFF_08_73EE_0 // f16_mul_rz.tv line 5500 37EE_7800_73EE_00 1.01111101110 x 2^-2 * 1.00000000000 x 2^15 = 1.01111101110 x 2^13
13FE_47FE_3CFF_08_1FFC_1 // f16_mul_rz.tv line 6000 13FE_47FE_1FFC_01 1.01111111110 x 2^-11 * 1.01111111110 x 2^2 = 1.01111111100 x 2^-8
3400_CA47_3CFF_08_C247_0 // f16_mul_rz.tv line 6500 3400_CA47_C247_00 1.00000000000 x 2^-2 * -1.01001000111 x 2^3 = -1.01001000111 x 2^1
30EE_3FFF_3CFF_08_34ED_1 // f16_mul_rz.tv line 7000 30EE_3FFF_34ED_01 1.00011101110 x 2^-3 * 1.01111111111 x 2^0 = 1.00011101101 x 2^-2
37FF_3801_3CFF_08_3400_1 // f16_mul_rz.tv line 7500 37FF_3801_3400_01 1.01111111111 x 2^-2 * 1.00000000001 x 2^-1 = 1.00000000000 x 2^-2
37FE_B783_3CFF_08_B381_1 // f16_mul_rz.tv line 8000 37FE_B783_B381_01 1.01111111110 x 2^-2 * -1.01110000011 x 2^-2 = -1.01110000001 x 2^-3
0EBE_1000_3CFF_08_0003_3 // f16_mul_rz.tv line 8500 0EBE_1000_0003_03 1.01010111110 x 2^-12 * 1.00000000000 x 2^-11 = Denorm
// Skipped denorm f16_mul_rz.tv line 9000 3801_03FE_01FF_03 1.00000000001 x 2^-1 * Denorm = Denorm
3801_480F_3CFF_08_4410_1 // f16_mul_rz.tv line 9500 3801_480F_4410_01 1.00000000001 x 2^-1 * 1.00000001111 x 2^3 = 1.00000010000 x 2^2
// Skipped denorm f16_mul_rz.tv line 10000 003E_FBFF_B3BF_01 Denorm * -1.01111111111 x 2^15 = -1.01110111111 x 2^-3
3BFE_E801_3CFF_08_E7FF_1 // f16_mul_rz.tv line 10500 3BFE_E801_E7FF_01 1.01111111110 x 2^-1 * -1.00000000001 x 2^11 = -1.01111111111 x 2^10
3C00_88D3_3CFF_08_88D3_0 // f16_mul_rz.tv line 11000 3C00_88D3_88D3_00 1.00000000000 x 2^0 * -1.00011010011 x 2^-13 = -1.00011010011 x 2^-13
257F_C000_3CFF_08_A97F_0 // f16_mul_rz.tv line 11500 257F_C000_A97F_00 1.00101111111 x 2^-6 * -1.00000000000 x 2^1 = -1.00101111111 x 2^-5
3FFF_BBFE_3CFF_08_BFFD_1 // f16_mul_rz.tv line 12000 3FFF_BBFE_BFFD_01 1.01111111111 x 2^0 * -1.01111111110 x 2^-1 = -1.01111111101 x 2^0
3FFE_4AFD_3CFF_08_4EFB_1 // f16_mul_rz.tv line 12500 3FFE_4AFD_4EFB_01 1.01111111110 x 2^0 * 1.01011111101 x 2^3 = 1.01011111011 x 2^4
B7FF_93FF_3CFF_08_0FFE_1 // f16_mul_rz.tv line 13000 B7FF_93FF_0FFE_01 -1.01111111111 x 2^-2 * -1.01111111111 x 2^-11 = 1.01111111110 x 2^-12
4001_8401_3CFF_08_8802_1 // f16_mul_rz.tv line 13500 4001_8401_8802_01 1.00000000001 x 2^1 * -1.00000000001 x 2^-14 = -1.00000000010 x 2^-13
43FF_3808_3CFF_08_4007_1 // f16_mul_rz.tv line 14000 43FF_3808_4007_01 1.01111111111 x 2^1 * 1.00000001000 x 2^-1 = 1.00000000111 x 2^1
AC0A_7C00_3CFF_08_FC00_0 // f16_mul_rz.tv line 14500 AC0A_7C00_FC00_00 -1.00000001010 x 2^-4 * INF = -INF
4400_6BFE_3CFF_08_73FE_0 // f16_mul_rz.tv line 15000 4400_6BFE_73FE_00 1.00000000000 x 2^2 * 1.01111111110 x 2^11 = 1.01111111110 x 2^13
4401_D3F2_3CFF_08_DBF3_1 // f16_mul_rz.tv line 15500 4401_D3F2_DBF3_01 1.00000000001 x 2^2 * -1.01111110010 x 2^5 = -1.01111110011 x 2^7
5BC2_43FF_3CFF_08_63C1_1 // f16_mul_rz.tv line 16000 5BC2_43FF_63C1_01 1.01111000010 x 2^7 * 1.01111111111 x 2^1 = 1.01111000001 x 2^9
47FE_3C01_3CFF_08_47FF_1 // f16_mul_rz.tv line 16500 47FE_3C01_47FF_01 1.01111111110 x 2^2 * 1.00000000001 x 2^0 = 1.01111111111 x 2^2
6800_13F1_3CFF_08_3FF1_0 // f16_mul_rz.tv line 17000 6800_13F1_3FF1_00 1.00000000000 x 2^11 * 1.01111110001 x 2^-11 = 1.01111110001 x 2^0
78FB_3400_3CFF_08_70FB_0 // f16_mul_rz.tv line 17500 78FB_3400_70FB_00 1.00011111011 x 2^15 * 1.00000000000 x 2^-2 = 1.00011111011 x 2^13
6BFF_07FE_3CFF_08_37FD_1 // f16_mul_rz.tv line 18000 6BFF_07FE_37FD_01 1.01111111111 x 2^11 * 1.01111111110 x 2^-14 = 1.01111111101 x 2^-2
6BFE_13FE_3CFF_08_43FC_1 // f16_mul_rz.tv line 18500 6BFE_13FE_43FC_01 1.01111111110 x 2^11 * 1.01111111110 x 2^-11 = 1.01111111100 x 2^1
382F_FFFF_3CFF_08_FFFF_0 // f16_mul_rz.tv line 19000 382F_FFFF_FFFF_00 1.00000101111 x 2^-1 * NaN = NaN
7800_F801_3CFF_08_FBFF_5 // f16_mul_rz.tv line 19500 7800_F801_FBFF_05 1.00000000000 x 2^15 * -1.00000000001 x 2^15 = -1.01111111111 x 2^15
7801_4877_3CFF_08_7BFF_5 // f16_mul_rz.tv line 20000 7801_4877_7BFF_05 1.00000000001 x 2^15 * 1.00001110111 x 2^3 = 1.01111111111 x 2^15
// Skipped denorm f16_mul_rz.tv line 20500 0090_C400_8240_00 Denorm * -1.00000000000 x 2^2 = -Denorm
7BFE_BFFE_3CFF_08_FBFF_5 // f16_mul_rz.tv line 21000 7BFE_BFFE_FBFF_05 1.01111111110 x 2^15 * -1.01111111110 x 2^0 = -1.01111111111 x 2^15
7C00_4F08_3CFF_08_7C00_0 // f16_mul_rz.tv line 21500 7C00_4F08_7C00_00 INF * 1.01100001000 x 2^4 = INF
BFFA_B7FF_3CFF_08_3BF9_1 // f16_mul_rz.tv line 22000 BFFA_B7FF_3BF9_01 -1.01111111010 x 2^0 * -1.01111111111 x 2^-2 = 1.01111111001 x 2^-1
7FFF_9001_3CFF_08_7FFF_0 // f16_mul_rz.tv line 22500 7FFF_9001_7FFF_00 NaN * -1.00000000001 x 2^-11 = NaN
7FFE_B82F_3CFF_08_7FFE_0 // f16_mul_rz.tv line 23000 7FFE_B82F_7FFE_00 NaN * -1.00000101111 x 2^-1 = NaN
// Skipped denorm f16_mul_rz.tv line 23500 2F68_8000_8000_00 1.01101101000 x 2^-4 * -Denorm = -Denorm
// Skipped denorm f16_mul_rz.tv line 24000 8001_7BFE_9BFE_00 -Denorm * 1.01111111110 x 2^15 = -1.01111111110 x 2^-9
// Skipped denorm f16_mul_rz.tv line 24500 83FF_EB8E_338C_01 -Denorm * -1.01110001110 x 2^11 = 1.01110001100 x 2^-3
75FF_47FF_3CFF_08_7BFF_5 // f16_mul_rz.tv line 25000 75FF_47FF_7BFF_05 1.00111111111 x 2^14 * 1.01111111111 x 2^2 = 1.01111111111 x 2^15
8400_4001_3CFF_08_8801_0 // f16_mul_rz.tv line 25500 8400_4001_8801_00 -1.00000000000 x 2^-14 * 1.00000000001 x 2^1 = -1.00000000001 x 2^-13
8401_C3E7_3CFF_08_0BE8_1 // f16_mul_rz.tv line 26000 8401_C3E7_0BE8_01 -1.00000000001 x 2^-14 * -1.01111100111 x 2^1 = 1.01111101000 x 2^-13
CC00_3800_3CFF_08_C800_0 // f16_mul_rz.tv line 26500 CC00_3800_C800_00 -1.00000000000 x 2^4 * 1.00000000000 x 2^-1 = -1.00000000000 x 2^3
87FE_13FE_3CFF_08_8001_3 // f16_mul_rz.tv line 27000 87FE_13FE_8001_03 -1.01111111110 x 2^-14 * 1.01111111110 x 2^-11 = -Denorm
9000_7FF2_3CFF_08_7FF2_0 // f16_mul_rz.tv line 27500 9000_7FF2_7FF2_00 -1.00000000000 x 2^-11 * NaN = NaN
// Skipped denorm f16_mul_rz.tv line 28000 C082_03FF_8880_01 -1.00010000010 x 2^1 * Denorm = -1.00010000000 x 2^-13
9001_FC01_3CFF_08_FE01_0 // f16_mul_rz.tv line 28500 9001_FC01_FE01_10 -1.00000000001 x 2^-11 * NaN = NaN
93FF_2DFF_3CFF_08_85FE_1 // f16_mul_rz.tv line 29000 93FF_2DFF_85FE_01 -1.01111111111 x 2^-11 * 1.00111111111 x 2^-4 = -1.00111111110 x 2^-14
BE01_E800_3CFF_08_6A01_0 // f16_mul_rz.tv line 29500 BE01_E800_6A01_00 -1.01000000001 x 2^0 * -1.00000000000 x 2^11 = 1.01000000001 x 2^11
B400_C3FE_3CFF_08_3BFE_0 // f16_mul_rz.tv line 30000 B400_C3FE_3BFE_00 -1.00000000000 x 2^-2 * -1.01111111110 x 2^1 = 1.01111111110 x 2^-1
B401_2702_3CFF_08_9F03_1 // f16_mul_rz.tv line 30500 B401_2702_9F03_01 -1.00000000001 x 2^-2 * 1.01100000010 x 2^-6 = -1.01100000011 x 2^-8
E09F_BBFF_3CFF_08_609E_1 // f16_mul_rz.tv line 31000 E09F_BBFF_609E_01 -1.00010011111 x 2^9 * -1.01111111111 x 2^-1 = 1.00010011110 x 2^9
B7FE_B401_3CFF_08_2FFF_1 // f16_mul_rz.tv line 31500 B7FE_B401_2FFF_01 -1.01111111110 x 2^-2 * -1.00000000001 x 2^-2 = 1.01111111111 x 2^-4
// Skipped denorm f16_mul_rz.tv line 32000 B800_80BF_005F_03 -1.00000000000 x 2^-1 * -Denorm = Denorm
6BBC_8400_3CFF_08_B3BC_0 // f16_mul_rz.tv line 32500 6BBC_8400_B3BC_00 1.01110111100 x 2^11 * -1.00000000000 x 2^-14 = -1.01110111100 x 2^-3
BBFF_7FFE_3CFF_08_7FFE_0 // f16_mul_rz.tv line 33000 BBFF_7FFE_7FFE_00 -1.01111111111 x 2^-1 * NaN = NaN
BBFE_09DF_3CFF_08_89DD_1 // f16_mul_rz.tv line 33500 BBFE_09DF_89DD_01 -1.01111111110 x 2^-1 * 1.00111011111 x 2^-13 = -1.00111011101 x 2^-13
124E_6BFF_3CFF_08_424D_1 // f16_mul_rz.tv line 34000 124E_6BFF_424D_01 1.01001001110 x 2^-11 * 1.01111111111 x 2^11 = 1.01001001101 x 2^1
BC01_4401_3CFF_08_C402_1 // f16_mul_rz.tv line 34500 BC01_4401_C402_01 -1.00000000001 x 2^0 * 1.00000000001 x 2^2 = -1.00000000010 x 2^2
BFFF_10BF_3CFF_08_94BE_1 // f16_mul_rz.tv line 35000 BFFF_10BF_94BE_01 -1.01111111111 x 2^0 * 1.00010111111 x 2^-11 = -1.00010111110 x 2^-10
48EF_3C00_3CFF_08_48EF_0 // f16_mul_rz.tv line 35500 48EF_3C00_48EF_00 1.00011101111 x 2^3 * 1.00000000000 x 2^0 = 1.00011101111 x 2^3
C000_37FE_3CFF_08_BBFE_0 // f16_mul_rz.tv line 36000 C000_37FE_BBFE_00 -1.00000000000 x 2^1 * 1.01111111110 x 2^-2 = -1.01111111110 x 2^-1
// Skipped denorm f16_mul_rz.tv line 36500 C001_021F_843F_01 -1.00000000001 x 2^1 * Denorm = -1.00000111111 x 2^-14
1180_07FF_3CFF_08_0001_3 // f16_mul_rz.tv line 37000 1180_07FF_0001_03 1.00110000000 x 2^-11 * 1.01111111111 x 2^-14 = Denorm
// Skipped denorm f16_mul_rz.tv line 37500 C3FE_0001_8003_03 -1.01111111110 x 2^1 * Denorm = -Denorm
// Skipped denorm f16_mul_rz.tv line 38000 C3FE_00FF_83FB_03 -1.01111111110 x 2^1 * Denorm = -Denorm
1A7C_F800_3CFF_08_D67C_0 // f16_mul_rz.tv line 38500 1A7C_F800_D67C_00 1.01001111100 x 2^-9 * -1.00000000000 x 2^15 = -1.01001111100 x 2^6
C401_C7FE_3CFF_08_4FFF_1 // f16_mul_rz.tv line 39000 C401_C7FE_4FFF_01 -1.00000000001 x 2^2 * -1.01111111110 x 2^2 = 1.01111111111 x 2^4
C7FF_C73F_3CFF_08_533E_1 // f16_mul_rz.tv line 39500 C7FF_C73F_533E_01 -1.01111111111 x 2^2 * -1.01100111111 x 2^2 = 1.01100111110 x 2^5
3F10_BFFF_3CFF_08_C30F_1 // f16_mul_rz.tv line 40000 3F10_BFFF_C30F_01 1.01100010000 x 2^0 * -1.01111111111 x 2^0 = -1.01100001111 x 2^1
E800_B801_3CFF_08_6401_0 // f16_mul_rz.tv line 40500 E800_B801_6401_00 -1.00000000000 x 2^11 * -1.00000000001 x 2^-1 = 1.00000000001 x 2^10
E801_B387_3CFF_08_5F88_1 // f16_mul_rz.tv line 41000 E801_B387_5F88_01 -1.00000000001 x 2^11 * -1.01110000111 x 2^-3 = 1.01110001000 x 2^8
CBE1_9000_3CFF_08_1FE1_0 // f16_mul_rz.tv line 41500 CBE1_9000_1FE1_00 -1.01111100001 x 2^3 * -1.00000000000 x 2^-11 = 1.01111100001 x 2^-8
// Skipped denorm f16_mul_rz.tv line 42000 EBFE_83FE_33FA_01 -1.01111111110 x 2^11 * -Denorm = 1.01111111010 x 2^-3
F800_3F00_3CFF_08_FB00_0 // f16_mul_rz.tv line 42500 F800_3F00_FB00_00 -1.00000000000 x 2^15 * 1.01100000000 x 2^0 = -1.01100000000 x 2^15
CFBF_7BFF_3CFF_08_FBFF_5 // f16_mul_rz.tv line 43000 CFBF_7BFF_FBFF_05 -1.01110111111 x 2^4 * 1.01111111111 x 2^15 = -1.01111111111 x 2^15
FBFF_6801_3CFF_08_FBFF_5 // f16_mul_rz.tv line 43500 FBFF_6801_FBFF_05 -1.01111111111 x 2^15 * 1.00000000001 x 2^11 = -1.01111111111 x 2^15
FBFE_11FF_3CFF_08_D1FD_1 // f16_mul_rz.tv line 44000 FBFE_11FF_D1FD_01 -1.01111111110 x 2^15 * 1.00111111111 x 2^-11 = -1.00111111101 x 2^5
3CD8_4000_3CFF_08_40D8_0 // f16_mul_rz.tv line 44500 3CD8_4000_40D8_00 1.00011011000 x 2^0 * 1.00000000000 x 2^1 = 1.00011011000 x 2^1
FC01_3BFE_3CFF_08_FE01_0 // f16_mul_rz.tv line 45000 FC01_3BFE_FE01_10 NaN * 1.01111111110 x 2^-1 = NaN
FFFF_44F7_3CFF_08_FFFF_0 // f16_mul_rz.tv line 45500 FFFF_44F7_FFFF_00 NaN * 1.00011110111 x 2^2 = NaN
CB78_13FF_3CFF_08_A377_1 // f16_mul_rz.tv line 46000 CB78_13FF_A377_01 -1.01101111000 x 2^3 * 1.01111111111 x 2^-11 = -1.01101110111 x 2^-7
////////// Testcases from f16_mulAdd_rz.tv of type mulAdd rounding mode 0
0000_0BE3_B9AB_0c_B9AB_0 // f16_mulAdd_rz.tv line 50000 0000_0BE3_B9AB_B9AB_00 0 * 1.01111100011 x 2^-13 + -1.00110101011 x 2^-1 = -1.00110101011 x 2^-1
2FC7_E793_3FFE_0c_DB4D_1 // f16_mulAdd_rz.tv line 100000 2FC7_E793_3FFE_DB4D_01 1.01111000111 x 2^-4 * -1.01110010011 x 2^10 + 1.01111111110 x 2^0 = -1.01101001101 x 2^7
4B04_3401_4EC1_0c_4FA1_1 // f16_mulAdd_rz.tv line 150000 4B04_3401_4EC1_4FA1_01 1.01100000100 x 2^3 * 1.00000000001 x 2^-2 + 1.01011000001 x 2^4 = 1.01110100001 x 2^4
// Skipped denorm f16_mulAdd_rz.tv line 200000 03FF_E800_F732_F732_01 Denorm * -1.00000000000 x 2^11 + -1.01100110010 x 2^14 = -1.01100110010 x 2^14
// Skipped denorm f16_mulAdd_rz.tv line 250000 03FE_D4FF_B401_B414_01 Denorm * -1.00011111111 x 2^6 + -1.00000000001 x 2^-2 = -1.00000010100 x 2^-2
C411_63FF_D382_0c_EC1F_1 // f16_mulAdd_rz.tv line 300000 C411_63FF_D382_EC1F_01 -1.00000010001 x 2^2 * 1.01111111111 x 2^9 + -1.01110000010 x 2^5 = -1.00000011111 x 2^12
B7E7_A09F_CC08_0c_CC07_1 // f16_mulAdd_rz.tv line 350000 B7E7_A09F_CC08_CC07_01 -1.01111100111 x 2^-2 * -1.00010011111 x 2^-7 + -1.00000001000 x 2^4 = -1.00000000111 x 2^4
90BB_BC01_0400_0c_113C_1 // f16_mulAdd_rz.tv line 400000 90BB_BC01_0400_113C_01 -1.00010111011 x 2^-11 * -1.00000000001 x 2^0 + 1.00000000000 x 2^-14 = 1.00100111100 x 2^-11
07FF_7C00_37FE_0c_7C00_0 // f16_mulAdd_rz.tv line 450000 07FF_7C00_37FE_7C00_00 1.01111111111 x 2^-14 * INF + 1.01111111110 x 2^-2 = INF
07FE_C197_6C7F_0c_6C7E_1 // f16_mulAdd_rz.tv line 500000 07FE_C197_6C7F_6C7E_01 1.01111111110 x 2^-14 * -1.00110010111 x 2^1 + 1.00001111111 x 2^12 = 1.00001111110 x 2^12
BC13_2BD7_7BFE_0c_7BFD_1 // f16_mulAdd_rz.tv line 550000 BC13_2BD7_7BFE_7BFD_01 -1.00000010011 x 2^0 * 1.01111010111 x 2^-5 + 1.01111111110 x 2^15 = 1.01111111101 x 2^15
B5BB_9001_6846_0c_6846_1 // f16_mulAdd_rz.tv line 600000 B5BB_9001_6846_6846_01 -1.00110111011 x 2^-2 * -1.00000000001 x 2^-11 + 1.00001000110 x 2^11 = 1.00001000110 x 2^11
1001_4400_C0DF_0c_C0DD_1 // f16_mulAdd_rz.tv line 650000 1001_4400_C0DF_C0DD_01 1.00000000001 x 2^-11 * 1.00000000000 x 2^2 + -1.00011011111 x 2^1 = -1.00011011101 x 2^1
13FF_2C01_C401_0c_C400_1 // f16_mulAdd_rz.tv line 700000 13FF_2C01_C401_C400_01 1.01111111111 x 2^-11 * 1.00000000001 x 2^-4 + -1.00000000001 x 2^2 = -1.00000000000 x 2^2
ABBF_BBA9_BB78_0c_BB01_1 // f16_mulAdd_rz.tv line 750000 ABBF_BBA9_BB78_BB01_01 -1.01110111111 x 2^-5 * -1.01110101001 x 2^-1 + -1.01101111000 x 2^-1 = -1.01100000001 x 2^-1
8409_3401_AEBF_0c_AEBF_1 // f16_mulAdd_rz.tv line 800000 8409_3401_AEBF_AEBF_01 -1.00000001001 x 2^-14 * 1.00000000001 x 2^-2 + -1.01010111111 x 2^-4 = -1.01010111111 x 2^-4
41FE_3801_3C00_0c_40FF_1 // f16_mulAdd_rz.tv line 850000 41FE_3801_3C00_40FF_01 1.00111111110 x 2^1 * 1.00000000001 x 2^-1 + 1.00000000000 x 2^0 = 1.00011111111 x 2^1
3400_F800_47FE_0c_EFFE_1 // f16_mulAdd_rz.tv line 900000 3400_F800_47FE_EFFE_01 1.00000000000 x 2^-2 * -1.00000000000 x 2^15 + 1.01111111110 x 2^2 = -1.01111111110 x 2^12
3401_BFCE_F963_0c_F963_1 // f16_mulAdd_rz.tv line 950000 3401_BFCE_F963_F963_01 1.00000000001 x 2^-2 * -1.01111001110 x 2^0 + -1.00101100011 x 2^15 = -1.00101100011 x 2^15
C8C0_1018_93FE_0c_9DDC_1 // f16_mulAdd_rz.tv line 1000000 C8C0_1018_93FE_9DDC_01 -1.00011000000 x 2^3 * 1.00000011000 x 2^-11 + -1.01111111110 x 2^-11 = -1.00111011100 x 2^-8
CA7E_0401_CEEE_0c_CEEE_1 // f16_mulAdd_rz.tv line 1050000 CA7E_0401_CEEE_CEEE_01 -1.01001111110 x 2^3 * 1.00000000001 x 2^-14 + -1.01011101110 x 2^4 = -1.01011101110 x 2^4
37FE_C000_B301_0c_BCDF_1 // f16_mulAdd_rz.tv line 1100000 37FE_C000_B301_BCDF_01 1.01111111110 x 2^-2 * -1.00000000000 x 2^1 + -1.01100000001 x 2^-3 = -1.00011011111 x 2^0
// Skipped denorm f16_mulAdd_rz.tv line 1150000 3800_5277_0001_4E77_01 1.00000000000 x 2^-1 * 1.01001110111 x 2^5 + Denorm = 1.01001110111 x 2^4
747B_6881_F708_0c_7BFF_5 // f16_mulAdd_rz.tv line 1200000 747B_6881_F708_7BFF_05 1.00001111011 x 2^14 * 1.00010000001 x 2^11 + -1.01100001000 x 2^14 = 1.01111111111 x 2^15
C80C_C67F_93FF_0c_5292_1 // f16_mulAdd_rz.tv line 1250000 C80C_C67F_93FF_5292_01 -1.00000001100 x 2^3 * -1.01001111111 x 2^2 + -1.01111111111 x 2^-11 = 1.01010010010 x 2^5
46DF_B401_7800_0c_77FF_1 // f16_mulAdd_rz.tv line 1300000 46DF_B401_7800_77FF_01 1.01011011111 x 2^2 * -1.00000000001 x 2^-2 + 1.00000000000 x 2^15 = 1.01111111111 x 2^14
// Skipped denorm f16_mulAdd_rz.tv line 1350000 3BFE_6800_83FE_67FD_01 1.01111111110 x 2^-1 * 1.00000000000 x 2^11 + -Denorm = 1.01111111101 x 2^10
3C00_CFBE_AC04_0c_CFC2_1 // f16_mulAdd_rz.tv line 1400000 3C00_CFBE_AC04_CFC2_01 1.00000000000 x 2^0 * -1.01110111110 x 2^4 + -1.00000000100 x 2^-4 = -1.01111000010 x 2^4
E877_C512_C3FE_0c_71A8_1 // f16_mulAdd_rz.tv line 1450000 E877_C512_C3FE_71A8_01 -1.00001110111 x 2^11 * -1.00100010010 x 2^2 + -1.01111111110 x 2^1 = 1.00110101000 x 2^13
// Skipped denorm f16_mulAdd_rz.tv line 1500000 C011_8001_400B_400B_01 -1.00000010001 x 2^1 * -Denorm + 1.00000001011 x 2^1 = 1.00000001011 x 2^1
3FFF_3C01_B43B_0c_3EF2_1 // f16_mulAdd_rz.tv line 1550000 3FFF_3C01_B43B_3EF2_01 1.01111111111 x 2^0 * 1.00000000001 x 2^0 + -1.00000111011 x 2^-2 = 1.01011110010 x 2^0
3FFF_CD3F_3801_0c_D12E_1 // f16_mulAdd_rz.tv line 1600000 3FFF_CD3F_3801_D12E_01 1.01111111111 x 2^0 * -1.00100111111 x 2^4 + 1.00000000001 x 2^-1 = -1.00100101110 x 2^5
325F_6B90_1607_0c_6205_1 // f16_mulAdd_rz.tv line 1650000 325F_6B90_1607_6205_01 1.01001011111 x 2^-3 * 1.01110010000 x 2^11 + 1.01000000111 x 2^-10 = 1.01000000101 x 2^9
7B86_BFFA_1CFC_0c_FBFF_5 // f16_mulAdd_rz.tv line 1700000 7B86_BFFA_1CFC_FBFF_05 1.01110000110 x 2^15 * -1.01111111010 x 2^0 + 1.00011111100 x 2^-8 = -1.01111111111 x 2^15
D61E_1001_9000_0c_AA2F_1 // f16_mulAdd_rz.tv line 1750000 D61E_1001_9000_AA2F_01 -1.01000011110 x 2^6 * 1.00000000001 x 2^-11 + -1.00000000000 x 2^-11 = -1.01000101111 x 2^-5
4001_C400_BBFE_0c_C880_1 // f16_mulAdd_rz.tv line 1800000 4001_C400_BBFE_C880_01 1.00000000001 x 2^1 * -1.00000000000 x 2^2 + -1.01111111110 x 2^-1 = -1.00010000000 x 2^3
43FF_4500_C91D_0c_48E1_1 // f16_mulAdd_rz.tv line 1850000 43FF_4500_C91D_48E1_01 1.01111111111 x 2^1 * 1.00100000000 x 2^2 + -1.00100011101 x 2^3 = 1.00011100001 x 2^3
B710_BB18_FFFE_0c_FFFE_0 // f16_mulAdd_rz.tv line 1900000 B710_BB18_FFFE_FFFE_00 -1.01100010000 x 2^-2 * -1.01100011000 x 2^-1 + NaN = NaN
6817_FFFF_B85F_0c_FFFF_0 // f16_mulAdd_rz.tv line 1950000 6817_FFFF_B85F_FFFF_00 1.00000010111 x 2^11 * NaN + -1.00001011111 x 2^-1 = NaN
4400_B801_D510_0c_D530_1 // f16_mulAdd_rz.tv line 2000000 4400_B801_D510_D530_01 1.00000000000 x 2^2 * -1.00000000001 x 2^-1 + -1.00100010000 x 2^6 = -1.00100110000 x 2^6
4401_43E6_6801_0c_6808_1 // f16_mulAdd_rz.tv line 2050000 4401_43E6_6801_6808_01 1.00000000001 x 2^2 * 1.01111100110 x 2^1 + 1.00000000001 x 2^11 = 1.00000001000 x 2^11
// Skipped denorm f16_mulAdd_rz.tv line 2100000 FF2B_4784_0376_FF2B_00 NaN * 1.01110000100 x 2^2 + Denorm = NaN
497E_BBDB_46E6_0c_C3C6_1 // f16_mulAdd_rz.tv line 2150000 497E_BBDB_46E6_C3C6_01 1.00101111110 x 2^3 * -1.01111011011 x 2^-1 + 1.01011100110 x 2^2 = -1.01111000110 x 2^1
2FD8_8401_C000_0c_C000_1 // f16_mulAdd_rz.tv line 2200000 2FD8_8401_C000_C000_01 1.01111011000 x 2^-4 * -1.00000000001 x 2^-14 + -1.00000000000 x 2^1 = -1.00000000000 x 2^1
6800_4000_EBFE_0c_4400_0 // f16_mulAdd_rz.tv line 2250000 6800_4000_EBFE_4400_00 1.00000000000 x 2^11 * 1.00000000000 x 2^1 + -1.01111111110 x 2^11 = 1.00000000000 x 2^2
// Skipped denorm f16_mulAdd_rz.tv line 2300000 6801_800C_305F_3052_01 1.00000000001 x 2^11 * -Denorm + 1.00001011111 x 2^-3 = 1.00001010010 x 2^-3
C0E9_B2FF_37FE_0c_3C25_1 // f16_mulAdd_rz.tv line 2350000 C0E9_B2FF_37FE_3C25_01 -1.00011101001 x 2^1 * -1.01011111111 x 2^-3 + 1.01111111110 x 2^-2 = 1.00000100101 x 2^0
6A7F_7BFF_7405_0c_7BFF_5 // f16_mulAdd_rz.tv line 2400000 6A7F_7BFF_7405_7BFF_05 1.01001111111 x 2^11 * 1.01111111111 x 2^15 + 1.00000000101 x 2^14 = 1.01111111111 x 2^15
6BFE_3401_B87A_0c_63FE_1 // f16_mulAdd_rz.tv line 2450000 6BFE_3401_B87A_63FE_01 1.01111111110 x 2^11 * 1.00000000001 x 2^-2 + -1.00001111010 x 2^-1 = 1.01111111110 x 2^9
6BFE_343E_8401_0c_643C_1 // f16_mulAdd_rz.tv line 2500000 6BFE_343E_8401_643C_01 1.01111111110 x 2^11 * 1.00000111110 x 2^-2 + -1.00000000001 x 2^-14 = 1.00000111100 x 2^10
// Skipped denorm f16_mulAdd_rz.tv line 2550000 3D03_02FB_AFFE_AFFD_01 1.00100000011 x 2^0 * Denorm + -1.01111111110 x 2^-4 = -1.01111111101 x 2^-4
7A10_47D2_AC4E_0c_7BFF_5 // f16_mulAdd_rz.tv line 2600000 7A10_47D2_AC4E_7BFF_05 1.01000010000 x 2^15 * 1.01111010010 x 2^2 + -1.00001001110 x 2^-4 = 1.01111111111 x 2^15
// Skipped denorm f16_mulAdd_rz.tv line 2650000 FBFE_0001_FC00_FC00_00 -1.01111111110 x 2^15 * Denorm + -INF = -INF
7BFF_BC01_07FE_0c_FBFF_5 // f16_mulAdd_rz.tv line 2700000 7BFF_BC01_07FE_FBFF_05 1.01111111111 x 2^15 * -1.00000000001 x 2^0 + 1.01111111110 x 2^-14 = -1.01111111111 x 2^15
7BFE_310F_5000_0c_7111_1 // f16_mulAdd_rz.tv line 2750000 7BFE_310F_5000_7111_01 1.01111111110 x 2^15 * 1.00100001111 x 2^-3 + 1.00000000000 x 2^5 = 1.00100010001 x 2^13
7933_17DE_47FE_0c_559C_1 // f16_mulAdd_rz.tv line 2800000 7933_17DE_47FE_559C_01 1.00100110011 x 2^15 * 1.01111011110 x 2^-10 + 1.01111111110 x 2^2 = 1.00110011100 x 2^6
// Skipped denorm f16_mulAdd_rz.tv line 2850000 0083_EBFF_B00F_B114_01 Denorm * -1.01111111111 x 2^11 + -1.00000001111 x 2^-3 = -1.00100010100 x 2^-3
7C01_9001_406F_0c_7E01_0 // f16_mulAdd_rz.tv line 2900000 7C01_9001_406F_7E01_10 NaN * -1.00000000001 x 2^-11 + 1.00001101111 x 2^1 = NaN
7FFF_E3C7_BC01_0c_7FFF_0 // f16_mulAdd_rz.tv line 2950000 7FFF_E3C7_BC01_7FFF_00 NaN * -1.01111000111 x 2^9 + -1.00000000001 x 2^0 = NaN
C4FF_87CF_2FDC_0c_2FE5_1 // f16_mulAdd_rz.tv line 3000000 C4FF_87CF_2FDC_2FE5_01 -1.00011111111 x 2^2 * -1.01111001111 x 2^-14 + 1.01111011100 x 2^-4 = 1.01111100101 x 2^-4
87F8_6016_4AB3_0c_4AAA_1 // f16_mulAdd_rz.tv line 3050000 87F8_6016_4AB3_4AAA_01 -1.01111111000 x 2^-14 * 1.00000010110 x 2^9 + 1.01010110011 x 2^3 = 1.01010101010 x 2^3
785F_7FFF_3400_0c_7FFF_0 // f16_mulAdd_rz.tv line 3100000 785F_7FFF_3400_7FFF_00 1.00001011111 x 2^15 * NaN + 1.00000000000 x 2^-2 = NaN
// Skipped denorm f16_mulAdd_rz.tv line 3150000 8001_3801_3FFE_3FFD_01 -Denorm * 1.00000000001 x 2^-1 + 1.01111111110 x 2^0 = 1.01111111101 x 2^0
// Skipped denorm f16_mulAdd_rz.tv line 3200000 8001_9376_03E0_03E0_03 -Denorm * -1.01101110110 x 2^-11 + Denorm = Denorm
// Skipped denorm f16_mulAdd_rz.tv line 3250000 BBF8_3103_83FE_B0FE_01 -1.01111111000 x 2^-1 * 1.00100000011 x 2^-3 + -Denorm = -1.00011111110 x 2^-3
4702_47FF_5F80_0c_6030_1 // f16_mulAdd_rz.tv line 3300000 4702_47FF_5F80_6030_01 1.01100000010 x 2^2 * 1.01111111111 x 2^2 + 1.01110000000 x 2^8 = 1.00000110000 x 2^9
8400_0401_4010_0c_400F_1 // f16_mulAdd_rz.tv line 3350000 8400_0401_4010_400F_01 -1.00000000000 x 2^-14 * 1.00000000001 x 2^-14 + 1.00000010000 x 2^1 = 1.00000001111 x 2^1
8400_33B6_F801_0c_F801_1 // f16_mulAdd_rz.tv line 3400000 8400_33B6_F801_F801_01 -1.00000000000 x 2^-14 * 1.01110110110 x 2^-3 + -1.00000000001 x 2^15 = -1.00000000001 x 2^15
DAAF_4B90_C7BD_0c_EA55_1 // f16_mulAdd_rz.tv line 3450000 DAAF_4B90_C7BD_EA55_01 -1.01010101111 x 2^7 * 1.01110010000 x 2^3 + -1.01110111101 x 2^2 = -1.01001010101 x 2^11
9021_32AD_B399_0c_B399_1 // f16_mulAdd_rz.tv line 3500000 9021_32AD_B399_B399_01 -1.00000100001 x 2^-11 * 1.01010101101 x 2^-3 + -1.01110011001 x 2^-3 = -1.01110011001 x 2^-3
AF8F_FBFF_4400_0c_6F8F_1 // f16_mulAdd_rz.tv line 3550000 AF8F_FBFF_4400_6F8F_01 -1.01110001111 x 2^-4 * -1.01111111111 x 2^15 + 1.00000000000 x 2^2 = 1.01110001111 x 2^12
87FE_B401_7BFE_0c_7BFE_1 // f16_mulAdd_rz.tv line 3600000 87FE_B401_7BFE_7BFE_01 -1.01111111110 x 2^-14 * -1.00000000001 x 2^-2 + 1.01111111110 x 2^15 = 1.01111111110 x 2^15
9000_8E7C_0BAF_0c_0BB0_1 // f16_mulAdd_rz.tv line 3650000 9000_8E7C_0BAF_0BB0_01 -1.00000000000 x 2^-11 * -1.01001111100 x 2^-12 + 1.01110101111 x 2^-13 = 1.01110110000 x 2^-13
744C_95FA_BBFE_0c_CEAB_1 // f16_mulAdd_rz.tv line 3700000 744C_95FA_BBFE_CEAB_01 1.00001001100 x 2^14 * -1.00111111010 x 2^-10 + -1.01111111110 x 2^-1 = -1.01010101011 x 2^4
42FE_C3FF_B81C_0c_CB3E_1 // f16_mulAdd_rz.tv line 3750000 42FE_C3FF_B81C_CB3E_01 1.01011111110 x 2^1 * -1.01111111111 x 2^1 + -1.00000011100 x 2^-1 = -1.01100111110 x 2^3
// Skipped denorm f16_mulAdd_rz.tv line 3800000 93FF_8001_88FE_88FD_01 -1.01111111111 x 2^-11 * -Denorm + -1.00011111110 x 2^-13 = -1.00011111101 x 2^-13
93FE_7401_1001_0c_CBFF_1 // f16_mulAdd_rz.tv line 3850000 93FE_7401_1001_CBFF_01 -1.01111111110 x 2^-11 * 1.00000000001 x 2^14 + 1.00000000001 x 2^-11 = -1.01111111111 x 2^3
3C16_42F4_43E1_0c_477D_1 // f16_mulAdd_rz.tv line 3900000 3C16_42F4_43E1_477D_01 1.00000010110 x 2^0 * 1.01011110100 x 2^1 + 1.01111100001 x 2^1 = 1.01101111101 x 2^2
7FBF_47FF_C18F_0c_7FBF_0 // f16_mulAdd_rz.tv line 3950000 7FBF_47FF_C18F_7FBF_00 NaN * 1.01111111111 x 2^2 + -1.00110001111 x 2^1 = NaN
// Skipped denorm f16_mulAdd_rz.tv line 4000000 441E_6BFF_8000_741D_01 1.00000011110 x 2^2 * 1.01111111111 x 2^11 + -Denorm = 1.00000011101 x 2^14
B7FF_1001_93FE_0c_94FF_1 // f16_mulAdd_rz.tv line 4050000 B7FF_1001_93FE_94FF_01 -1.01111111111 x 2^-2 * 1.00000000001 x 2^-11 + -1.01111111110 x 2^-11 = -1.00011111111 x 2^-10
B7FF_C9C0_47DF_0c_4ACF_1 // f16_mulAdd_rz.tv line 4100000 B7FF_C9C0_47DF_4ACF_01 -1.01111111111 x 2^-2 * -1.00111000000 x 2^3 + 1.01111011111 x 2^2 = 1.01011001111 x 2^3
C40F_AB7F_EBFE_0c_EBFD_1 // f16_mulAdd_rz.tv line 4150000 C40F_AB7F_EBFE_EBFD_01 -1.00000001111 x 2^2 * -1.01101111111 x 2^-5 + -1.01111111110 x 2^11 = -1.01111111101 x 2^11
D404_3FFE_EAF9_0c_EB39_1 // f16_mulAdd_rz.tv line 4200000 D404_3FFE_EAF9_EB39_01 -1.00000000100 x 2^6 * 1.01111111110 x 2^0 + -1.01011111001 x 2^11 = -1.01100111001 x 2^11
B800_FFFF_F201_0c_FFFF_0 // f16_mulAdd_rz.tv line 4250000 B800_FFFF_F201_FFFF_00 -1.00000000000 x 2^-1 * NaN + -1.01000000001 x 2^13 = NaN
B801_3D3F_4001_0c_3D61_1 // f16_mulAdd_rz.tv line 4300000 B801_3D3F_4001_3D61_01 -1.00000000001 x 2^-1 * 1.00100111111 x 2^0 + 1.00000000001 x 2^1 = 1.00101100001 x 2^0
4FFF_4D63_77FF_0c_7815_1 // f16_mulAdd_rz.tv line 4350000 4FFF_4D63_77FF_7815_01 1.01111111111 x 2^4 * 1.00101100011 x 2^4 + 1.01111111111 x 2^14 = 1.00000010101 x 2^15
C41B_0FA0_C902_0c_C902_1 // f16_mulAdd_rz.tv line 4400000 C41B_0FA0_C902_C902_01 -1.00000011011 x 2^2 * 1.01110100000 x 2^-12 + -1.00100000010 x 2^3 = -1.00100000010 x 2^3
B7C2_C7FF_B800_0c_42C1_1 // f16_mulAdd_rz.tv line 4450000 B7C2_C7FF_B800_42C1_01 -1.01111000010 x 2^-2 * -1.01111111111 x 2^2 + -1.00000000000 x 2^-1 = 1.01011000001 x 2^1
BC00_8401_C3FE_0c_C3FD_1 // f16_mulAdd_rz.tv line 4500000 BC00_8401_C3FE_C3FD_01 -1.00000000000 x 2^0 * -1.00000000001 x 2^-14 + -1.01111111110 x 2^1 = -1.01111111101 x 2^1
BC01_6800_D06F_0c_E812_1 // f16_mulAdd_rz.tv line 4550000 BC01_6800_D06F_E812_01 -1.00000000001 x 2^0 * 1.00000000000 x 2^11 + -1.00001101111 x 2^5 = -1.00000010010 x 2^11
CFBC_931A_07FE_0c_26E5_1 // f16_mulAdd_rz.tv line 4600000 CFBC_931A_07FE_26E5_01 -1.01110111100 x 2^4 * -1.01100011010 x 2^-11 + 1.01111111110 x 2^-14 = 1.01011100101 x 2^-6
7C70_BBFE_27F8_0c_7E70_0 // f16_mulAdd_rz.tv line 4650000 7C70_BBFE_27F8_7E70_10 NaN * -1.01111111110 x 2^-1 + 1.01111111000 x 2^-6 = NaN
BFFE_7BFF_D3DF_0c_FBFF_5 // f16_mulAdd_rz.tv line 4700000 BFFE_7BFF_D3DF_FBFF_05 -1.01111111110 x 2^0 * 1.01111111111 x 2^15 + -1.01111011111 x 2^5 = -1.01111111111 x 2^15
C000_2383_7C01_0c_7E01_0 // f16_mulAdd_rz.tv line 4750000 C000_2383_7C01_7E01_10 -1.00000000000 x 2^1 * 1.01110000011 x 2^-7 + NaN = NaN
// Skipped denorm f16_mulAdd_rz.tv line 4800000 AFBC_8020_87F2_87EE_01 -1.01110111100 x 2^-4 * -Denorm + -1.01111110010 x 2^-14 = -1.01111101110 x 2^-14
D00C_B8F6_B3CF_0c_4CF5_1 // f16_mulAdd_rz.tv line 4850000 D00C_B8F6_B3CF_4CF5_01 -1.00000001100 x 2^5 * -1.00011110110 x 2^-1 + -1.01111001111 x 2^-3 = 1.00011110101 x 2^4
8BEB_43FF_E800_0c_E800_1 // f16_mulAdd_rz.tv line 4900000 8BEB_43FF_E800_E800_01 -1.01111101011 x 2^-13 * 1.01111111111 x 2^1 + -1.00000000000 x 2^11 = -1.00000000000 x 2^11
// Skipped denorm f16_mulAdd_rz.tv line 4950000 C3FE_0001_FFFE_FFFE_00 -1.01111111110 x 2^1 * Denorm + NaN = NaN
C3FE_B1FF_A600_0c_39CD_1 // f16_mulAdd_rz.tv line 5000000 C3FE_B1FF_A600_39CD_01 -1.01111111110 x 2^1 * -1.00111111111 x 2^-3 + -1.01000000000 x 2^-6 = 1.00111001101 x 2^-1
B004_FC44_3FFE_0c_FE44_0 // f16_mulAdd_rz.tv line 5050000 B004_FC44_3FFE_FE44_10 -1.00000000100 x 2^-3 * NaN + 1.01111111110 x 2^0 = NaN
85FF_37FE_31FE_0c_31FD_1 // f16_mulAdd_rz.tv line 5100000 85FF_37FE_31FE_31FD_01 -1.00111111111 x 2^-14 * 1.01111111110 x 2^-2 + 1.00111111110 x 2^-3 = 1.00111111101 x 2^-3
C401_EBFF_92C2_0c_7400_1 // f16_mulAdd_rz.tv line 5150000 C401_EBFF_92C2_7400_01 -1.00000000001 x 2^2 * -1.01111111111 x 2^11 + -1.01011000010 x 2^-11 = 1.00000000000 x 2^14
C7FF_B408_B401_0c_3F0E_1 // f16_mulAdd_rz.tv line 5200000 C7FF_B408_B401_3F0E_01 -1.01111111111 x 2^2 * -1.00000001000 x 2^-2 + -1.00000000001 x 2^-2 = 1.01100001110 x 2^0
43E0_C6FB_2360_0c_CEDE_1 // f16_mulAdd_rz.tv line 5250000 43E0_C6FB_2360_CEDE_01 1.01111100000 x 2^1 * -1.01011111011 x 2^2 + 1.01101100000 x 2^-7 = -1.01011011110 x 2^4
8B87_2C17_4F43_0c_4F42_1 // f16_mulAdd_rz.tv line 5300000 8B87_2C17_4F43_4F42_01 -1.01110000111 x 2^-13 * 1.00000010111 x 2^-4 + 1.01101000011 x 2^4 = 1.01101000010 x 2^4
// Skipped denorm f16_mulAdd_rz.tv line 5350000 830F_BFFE_0400_090E_01 -Denorm * -1.01111111110 x 2^0 + 1.00000000000 x 2^-14 = 1.00100001110 x 2^-13
E801_7FFF_37FE_0c_7FFF_0 // f16_mulAdd_rz.tv line 5400000 E801_7FFF_37FE_7FFF_00 -1.00000000001 x 2^11 * NaN + 1.01111111110 x 2^-2 = NaN
EBFF_483F_C7C1_0c_F83E_1 // f16_mulAdd_rz.tv line 5450000 EBFF_483F_C7C1_F83E_01 -1.01111111111 x 2^11 * 1.00000111111 x 2^3 + -1.01111000001 x 2^2 = -1.00000111110 x 2^15
49FE_3703_7BFE_0c_7BFE_1 // f16_mulAdd_rz.tv line 5500000 49FE_3703_7BFE_7BFE_01 1.00111111110 x 2^3 * 1.01100000011 x 2^-2 + 1.01111111110 x 2^15 = 1.01111111110 x 2^15
84BE_93FE_33DE_0c_33DE_1 // f16_mulAdd_rz.tv line 5550000 84BE_93FE_33DE_33DE_01 -1.00010111110 x 2^-14 * -1.01111111110 x 2^-11 + 1.01111011110 x 2^-3 = 1.01111011110 x 2^-3
F800_47FF_40FE_0c_FBFF_5 // f16_mulAdd_rz.tv line 5600000 F800_47FF_40FE_FBFF_05 -1.00000000000 x 2^15 * 1.01111111111 x 2^2 + 1.00011111110 x 2^1 = -1.01111111111 x 2^15
F801_E3FE_C401_0c_7BFF_5 // f16_mulAdd_rz.tv line 5650000 F801_E3FE_C401_7BFF_05 -1.00000000001 x 2^15 * -1.01111111110 x 2^9 + -1.00000000001 x 2^2 = 1.01111111111 x 2^15
0E80_0810_E912_0c_E911_1 // f16_mulAdd_rz.tv line 5700000 0E80_0810_E912_E911_01 1.01010000000 x 2^-12 * 1.00000010000 x 2^-13 + -1.00100010010 x 2^11 = -1.00100010001 x 2^11
A67F_49FF_4D3E_0c_4D2A_1 // f16_mulAdd_rz.tv line 5750000 A67F_49FF_4D3E_4D2A_01 -1.01001111111 x 2^-6 * 1.00111111111 x 2^3 + 1.00100111110 x 2^4 = 1.00100101010 x 2^4
22DC_3BFE_3C00_0c_3C0D_1 // f16_mulAdd_rz.tv line 5800000 22DC_3BFE_3C00_3C0D_01 1.01011011100 x 2^-7 * 1.01111111110 x 2^-1 + 1.00000000000 x 2^0 = 1.00000001101 x 2^0
FBFE_FBFF_47FE_0c_7BFF_5 // f16_mulAdd_rz.tv line 5850000 FBFE_FBFF_47FE_7BFF_05 -1.01111111110 x 2^15 * -1.01111111111 x 2^15 + 1.01111111110 x 2^2 = 1.01111111111 x 2^15
FC00_CE07_47C3_0c_7C00_0 // f16_mulAdd_rz.tv line 5900000 FC00_CE07_47C3_7C00_00 -INF * -1.01000000111 x 2^4 + 1.01111000011 x 2^2 = INF
343D_C5C9_93FE_0c_BE22_1 // f16_mulAdd_rz.tv line 5950000 343D_C5C9_93FE_BE22_01 1.00000111101 x 2^-2 * -1.00111001001 x 2^2 + -1.01111111110 x 2^-11 = -1.01000100010 x 2^0
EA10_07FE_C803_0c_C833_1 // f16_mulAdd_rz.tv line 6000000 EA10_07FE_C803_C833_01 -1.01000010000 x 2^11 * 1.01111111110 x 2^-14 + -1.00000000011 x 2^3 = -1.00000110011 x 2^3
FFFF_C3FF_EA40_0c_FFFF_0 // f16_mulAdd_rz.tv line 6050000 FFFF_C3FF_EA40_FFFF_00 NaN * -1.01111111111 x 2^1 + -1.01001000000 x 2^11 = NaN
// Skipped denorm f16_mulAdd_rz.tv line 6100000 FFFE_80F8_0001_FFFE_00 NaN * -Denorm + Denorm = NaN

8
pipelined/src/fpu/fcvtfp.sv
View File

@ -30,11 +30,17 @@ module cvtfp (
logic [31:0] DSRes; // double to single precision result
// add support for all formats
// consider reordering code blocks so upconverting is in one region of the file
// and downconverting is in the other region.
///////////////////////////////////////////////////////////////////////////////
// LZC
// LZC: Leading Zero Counter
///////////////////////////////////////////////////////////////////////////////
// *** consider sharing this with fcvtint
// *** emphasize parallel structure between the two
// *** add a priorityencoder module to generic (similar to priorityonehot) and use it
// LZC - find the first 1 in the input's mantissa
logic [8:0] i,NormCnt;

4
pipelined/src/fpu/fcvtint.sv
View File

@ -61,6 +61,10 @@ module fcvt (
// fcvt.d.l = 100
// fcvt.d.lu = 110
// {long, unsigned, to int}
// *** revisit this module, explain in more depth
// should the int to fp and fp to int paths be separated?
// add support for all formats
// calculate signals based off the input and output's size
assign Res64 = (FOpCtrlE[0]&FOpCtrlE[2]) | (FmtE&~FOpCtrlE[0]);

9
pipelined/src/ieu/alu.sv
View File

@ -40,9 +40,9 @@ module alu #(parameter WIDTH=32) (
logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
logic Carry, Neg;
logic LT, LTU;
logic Overflow;
logic W64, SubArith, ALUOp;
logic [2:0] ALUFunct;
logic Asign, Bsign;
// Extract control signals
// W64 indicates RV64 W-suffix instructions acting on lower 32-bit word
@ -57,12 +57,13 @@ module alu #(parameter WIDTH=32) (
// Shifts
shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
// condition code flags based on subtract output
// condition code flags based on subtract output Sum = A-B
// Overflow occurs when the numbers being subtracted have the opposite sign
// and the result has the opposite sign of A
assign Overflow = (A[WIDTH-1] ^ B[WIDTH-1]) & (A[WIDTH-1] ^ Sum[WIDTH-1]);
assign Neg = Sum[WIDTH-1];
assign LT = Neg ^ Overflow;
assign Asign = A[WIDTH-1];
assign Bsign = B[WIDTH-1];
assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; // simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow
assign LTU = ~Carry;
// SLT

35
pipelined/src/ieu/comparator.sv
View File

@ -36,9 +36,8 @@ module comparator #(parameter WIDTH=32) (
logic [WIDTH-1:0] bbar, diff;
logic carry, eq, neg, overflow, lt, ltu;
// NOTE: This can be replaced by some faster logic optimized
// to just compute flags and not the difference.
/*
// Subtractor implementation
// subtraction
assign bbar = ~b;
@ -53,5 +52,35 @@ module comparator #(parameter WIDTH=32) (
assign lt = neg ^ overflow;
assign ltu = ~carry;
assign flags = {eq, lt, ltu};
*/
/* verilator lint_off UNOPTFLAT */
// prefix implementation
localparam levels=$clog2(WIDTH);
genvar i;
genvar level;
logic [WIDTH-1:0] e[levels:0];
logic [WIDTH-1:0] l[levels:0];
logic eq2, lt2, ltu2;
// Bitwise logic
assign e[0] = a ~^ b; // bitwise equality
assign l[0] = ~a & b; // bitwise less than unsigned: A=0 and B=1
// Recursion
for (level = 1; level<=levels; level++) begin
for (i=0; i<WIDTH/(2**level); i++) begin
assign e[level][i] = e[level-1][i*2+1] & e[level-1][i*2]; // group equal if both parts equal
assign l[level][i] = l[level-1][i*2+1] | e[level-1][i*2+1] & l[level-1][i*2]; // group less if upper is les or upper equal and lower less
end
end
// Output logic
assign eq2 = e[levels][0]; // A = B if all bits are equal
assign ltu2 = l[levels][0]; // A < B if group is less (unsigned)
// A < B signed if less than unsigned and msb is not < unsigned, or if A negative and B positive
assign lt2 = ltu2 & ~l[0][WIDTH-1] | a[WIDTH-1] & ~b[WIDTH-1];
assign flags = {eq2, lt2, ltu2};
/* verilator lint_on UNOPTFLAT */
endmodule

41
pipelined/src/ifu/gsharePredictor.sv
View File

@ -31,10 +31,7 @@
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module gsharePredictor
#(parameter int k = 10
)
(input logic clk,
input logic reset,
input logic StallF, StallE,
@ -52,8 +49,8 @@ module gsharePredictor
input logic [1:0] UpdateBPPredE
);
logic [k+1:0] GHR, GHRNext;
logic [k-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
logic [`BPRED_SIZE+1:0] GHR, GHRNext;
logic [`BPRED_SIZE-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
logic PHTUpdateEN;
logic BPClassWrongNonCFI;
logic BPClassWrongCFI;
@ -63,7 +60,7 @@ module gsharePredictor
logic [6:0] GHRMuxSel;
logic GHRUpdateEN;
logic [k-1:0] GHRLookup;
logic [`BPRED_SIZE-1:0] GHRLookup;
assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
@ -85,18 +82,18 @@ module gsharePredictor
// hoping this created a AND-OR mux.
always_comb begin
case (GHRMuxSel)
7'b000_0001: GHRNext = GHR[k-1+2:0]; // no change
7'b000_0010: GHRNext = {GHR[k-2+2:0], PCSrcE}; // branch update
7'b000_0100: GHRNext = {1'b0, GHR[k+1:1]}; // repair 1
7'b000_1000: GHRNext = {GHR[k-1+2:1], PCSrcE}; // branch update with mis prediction correction
7'b001_0000: GHRNext = {2'b00, GHR[k+1:2]}; // repair 2
7'b010_0000: GHRNext = {1'b0, GHR[k+1:2], PCSrcE}; // branch update + repair 1
7'b100_0000: GHRNext = {GHR[k-2+2:0], BPPredF[1]}; // speculative update
default: GHRNext = GHR[k-1+2:0];
7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0]; // no change
7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update
7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1
7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction
7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2
7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1
7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], BPPredF[1]}; // speculative update
default: GHRNext = GHR[`BPRED_SIZE-1+2:0];
endcase
end
flopenr #(k+2) GlobalHistoryRegister(.clk(clk),
flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk),
.reset(reset),
.en((GHRUpdateEN)),
.d(GHRNext),
@ -105,21 +102,21 @@ module gsharePredictor
// if actively updating the GHR at the time of prediction we want to us
// GHRNext as the lookup rather than GHR.
assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[k:1] : GHR[k-1:0];
assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[k+1:2] : GHR[k:1];
assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0];
assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1];
assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
assign PHTUpdateEN = InstrClassE[0] & ~StallE;
assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[k-1:0] : GHR[k-1:0];
assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0];
// Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
SRAM2P1R1W #(k, 2) PHT(.clk(clk),
SRAM2P1R1W #(`BPRED_SIZE, 2) PHT(.clk(clk),
.reset(reset),
//.RA1(GHR[k-1:0]),
.RA1(GHRLookup ^ PCNextF[k:1]),
//.RA1(GHR[`BPRED_SIZE-1:0]),
.RA1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
.RD1(BPPredF),
.REN1(~StallF),
.WA1(PHTUpdateAdr ^ PCE[k:1]),
.WA1(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
.WD1(UpdateBPPredE),
.WEN1(PHTUpdateEN),
.BitWEN1(2'b11));

2
pipelined/src/ifu/ifu.sv
View File

@ -140,7 +140,7 @@ module ifu (
// WFI
/////////////////////////////////////////////////////////////////////////////////////////////
assign wfiD = (InstrD[6:0] == 7'b111011 && InstrD[31:20] == 12'b000100000101); // WFI in decode stage
assign wfiD = (InstrD[6:0] == 7'b1110011 && InstrD[31:20] == 12'b000100000101); // WFI in decode stage
assign InstrNextF = wfiD ? InstrD : PostSpillInstrRawF; // on WFI, keep replaying WFI
////////////////////////////////////////////////////////////////////////////////////////////////

4
pipelined/src/lsu/atomic.sv
View File

@ -41,7 +41,7 @@ module atomic (
input logic [1:0] LSUAtomicM,
input logic [1:0] PreLSURWM,
input logic IgnoreRequest,
output logic [`XLEN-1:0] FinalAMOWriteDataM,
output logic [`XLEN-1:0] AMOWriteDataM,
output logic SquashSCW,
output logic [1:0] LSURWM);
@ -50,7 +50,7 @@ module atomic (
amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]),
.result(AMOResult));
mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], AMOWriteDataM);
assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
lrsc lrsc(.clk, .reset, .FlushW, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
.SquashSCW, .LSURWM);

9
pipelined/src/lsu/lsu.sv
View File

@ -145,6 +145,7 @@ module lsu (
assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
// MMU and Misalignment fault logic required if privileged unit exists
// *** DH: This is too strong a requirement. Separate MMU in `VIRTMEM_SUPPORTED from simpler faults in `ZICSR_SUPPORTED
if(`ZICSR_SUPPORTED == 1) begin : dmmu
logic DisableTranslation;
assign DisableTranslation = SelHPTW | FlushDCacheM;
@ -181,7 +182,7 @@ module lsu (
// Memory System
// Either Data Cache or Data Tightly Integrated Memory or just bus interface
/////////////////////////////////////////////////////////////////////////////////////////////
logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM;
logic [`XLEN-1:0] AMOWriteDataM, FinalWriteDataM;
logic [`XLEN-1:0] ReadDataWordM;
logic [`XLEN-1:0] ReadDataWordMuxM;
logic IgnoreRequest;
@ -255,13 +256,13 @@ module lsu (
if (`A_SUPPORTED) begin:atomic
atomic atomic(.clk, .reset, .FlushW, .StallW, .ReadDataM, .LSUWriteDataM, .LSUPAdrM,
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
.FinalAMOWriteDataM, .SquashSCW, .LSURWM);
.AMOWriteDataM, .SquashSCW, .LSURWM);
end else begin:lrsc
assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM;
assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign AMOWriteDataM = LSUWriteDataM;
end
subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]),
.LSUFunct3M, .FinalAMOWriteDataM, .FinalWriteDataM, .ByteMaskM);
.LSUFunct3M, .AMOWriteDataM, .FinalWriteDataM, .ByteMaskM);
endmodule

51
pipelined/src/lsu/subwordwrite.sv
View File

@ -33,55 +33,30 @@
module subwordwrite (
input logic [2:0] LSUPAdrM,
input logic [2:0] LSUFunct3M,
input logic [`XLEN-1:0] FinalAMOWriteDataM,
input logic [`XLEN-1:0] AMOWriteDataM,
output logic [`XLEN-1:0] FinalWriteDataM,
output logic [`XLEN/8-1:0] ByteMaskM
);
logic [`XLEN-1:0] WriteDataSubwordDuplicated;
);
swbytemask swbytemask(.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), .HADDRD(LSUPAdrM),
.ByteMask(ByteMaskM));
// Compute byte masks
swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));
// Replicate data for subword writes
if (`XLEN == 64) begin:sww
// Handle subword writes
always_comb
case(LSUFunct3M[1:0])
2'b00: WriteDataSubwordDuplicated = {8{FinalAMOWriteDataM[7:0]}}; // sb
2'b01: WriteDataSubwordDuplicated = {4{FinalAMOWriteDataM[15:0]}}; // sh
2'b10: WriteDataSubwordDuplicated = {2{FinalAMOWriteDataM[31:0]}}; // sw
2'b11: WriteDataSubwordDuplicated = FinalAMOWriteDataM; // sw
2'b00: FinalWriteDataM = {8{AMOWriteDataM[7:0]}}; // sb
2'b01: FinalWriteDataM = {4{AMOWriteDataM[15:0]}}; // sh
2'b10: FinalWriteDataM = {2{AMOWriteDataM[31:0]}}; // sw
2'b11: FinalWriteDataM = AMOWriteDataM; // sw
endcase
always_comb begin
FinalWriteDataM='0;
if (ByteMaskM[0]) FinalWriteDataM[7:0] = WriteDataSubwordDuplicated[7:0];
if (ByteMaskM[1]) FinalWriteDataM[15:8] = WriteDataSubwordDuplicated[15:8];
if (ByteMaskM[2]) FinalWriteDataM[23:16] = WriteDataSubwordDuplicated[23:16];
if (ByteMaskM[3]) FinalWriteDataM[31:24] = WriteDataSubwordDuplicated[31:24];
if (ByteMaskM[4]) FinalWriteDataM[39:32] = WriteDataSubwordDuplicated[39:32];
if (ByteMaskM[5]) FinalWriteDataM[47:40] = WriteDataSubwordDuplicated[47:40];
if (ByteMaskM[6]) FinalWriteDataM[55:48] = WriteDataSubwordDuplicated[55:48];
if (ByteMaskM[7]) FinalWriteDataM[63:56] = WriteDataSubwordDuplicated[63:56];
end
end else begin:sww // 32-bit
// Handle subword writes
always_comb
case(LSUFunct3M[1:0])
2'b00: WriteDataSubwordDuplicated = {4{FinalAMOWriteDataM[7:0]}}; // sb
2'b01: WriteDataSubwordDuplicated = {2{FinalAMOWriteDataM[15:0]}}; // sh
2'b10: WriteDataSubwordDuplicated = FinalAMOWriteDataM; // sw
default: WriteDataSubwordDuplicated = FinalAMOWriteDataM; // shouldn't happen
2'b00: FinalWriteDataM = {4{AMOWriteDataM[7:0]}}; // sb
2'b01: FinalWriteDataM = {2{AMOWriteDataM[15:0]}}; // sh
2'b10: FinalWriteDataM = AMOWriteDataM; // sw
default: FinalWriteDataM = AMOWriteDataM; // shouldn't happen
endcase
always_comb begin
FinalWriteDataM='0;
if (ByteMaskM[0]) FinalWriteDataM[7:0] = WriteDataSubwordDuplicated[7:0];
if (ByteMaskM[1]) FinalWriteDataM[15:8] = WriteDataSubwordDuplicated[15:8];
if (ByteMaskM[2]) FinalWriteDataM[23:16] = WriteDataSubwordDuplicated[23:16];
if (ByteMaskM[3]) FinalWriteDataM[31:24] = WriteDataSubwordDuplicated[31:24];
end
end
endmodule

22
pipelined/src/lsu/swbytemask.sv
View File

@ -31,32 +31,32 @@
`include "wally-config.vh"
module swbytemask (
input logic [3:0] HSIZED,
input logic [2:0] HADDRD,
input logic [1:0] Size,
input logic [2:0] Adr,
output logic [`XLEN/8-1:0] ByteMask);
if(`XLEN == 64) begin
always_comb begin
case(HSIZED[1:0])
2'b00: begin ByteMask = 8'b00000000; ByteMask[HADDRD[2:0]] = 1; end // sb
2'b01: case (HADDRD[2:1])
case(Size[1:0])
2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb
2'b01: case (Adr[2:1])
2'b00: ByteMask = 8'b0000_0011;
2'b01: ByteMask = 8'b0000_1100;
2'b10: ByteMask = 8'b0011_0000;
2'b11: ByteMask = 8'b1100_0000;
endcase
2'b10: if (HADDRD[2]) ByteMask = 8'b11110000;
else ByteMask = 8'b00001111;
2'b10: if (Adr[2]) ByteMask = 8'b11110000;
else ByteMask = 8'b00001111;
2'b11: ByteMask = 8'b1111_1111;
endcase
end
end else begin
always_comb begin
case(HSIZED[1:0])
2'b00: begin ByteMask = 4'b0000; ByteMask[HADDRD[1:0]] = 1; end // sb
2'b01: if (HADDRD[1]) ByteMask = 4'b1100;
else ByteMask = 4'b0011;
case(Size[1:0])
2'b00: begin ByteMask = 4'b0000; ByteMask[Adr[1:0]] = 1; end // sb
2'b01: if (Adr[1]) ByteMask = 4'b1100;
else ByteMask = 4'b0011;
2'b10: ByteMask = 4'b1111;
default: ByteMask = 4'b1111;
endcase

6
pipelined/src/privileged/csrc.sv
View File

@ -64,12 +64,8 @@ module csrc #(parameter
);
if (`ZICOUNTERS_SUPPORTED) begin:counters
(* mark_debug = "true" *) logic [63:0] CYCLE_REGW, INSTRET_REGW;
logic [63:0] CYCLEPlusM, INSTRETPlusM;
logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
logic WriteCYCLEM, WriteINSTRETM;
logic [4:0] CounterNumM;
logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
(* mark_debug = "true" *) logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0];
logic InstrValidNotFlushedM;
logic LoadStallE, LoadStallM;

8
pipelined/src/privileged/privdec.sv
View File

@ -33,7 +33,8 @@
module privdec (
input logic [31:20] InstrM,
input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM, TrappedSRETM,
input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM,
input logic TrappedSRETM, WFITimeoutM,
input logic [1:0] PrivilegeModeW,
input logic STATUS_TSR,
output logic IllegalInstrFaultM,
@ -51,7 +52,6 @@ module privdec (
assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101);
assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001); // *** & (PrivilegedModeW == `M_MODE | ~STATUS_TVM); // *** does this work in U mode?
assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | TrappedSRETM; // *** generalize this for other instructions
// *** initially, wfi is nop
assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM |
TrappedSRETM | WFITimeoutM; // *** generalize this for other instructions
endmodule

33
pipelined/src/privileged/privileged.sv
View File

@ -104,6 +104,7 @@ module privileged (
logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW;
logic md;
logic StallMQ;
logic WFITimeoutM;
///////////////////////////////////////////
@ -114,24 +115,6 @@ module privileged (
assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]];
// PrivilegeMode FSM
/* -----\/----- EXCLUDED -----\/-----
always_comb begin
TrappedSRETM = 0;
if (mretM) NextPrivilegeModeM = STATUS_MPP;
else if (sretM)
if (STATUS_TSR & PrivilegeModeW == `S_MODE) begin
TrappedSRETM = 1;
NextPrivilegeModeM = PrivilegeModeW;
end else NextPrivilegeModeM = {1'b0, STATUS_SPP};
else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE))
NextPrivilegeModeM = `S_MODE;
else NextPrivilegeModeM = `M_MODE;
end else NextPrivilegeModeM = PrivilegeModeW;
end
-----/\----- EXCLUDED -----/\----- */
always_comb begin
if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE))
@ -149,14 +132,22 @@ module privileged (
flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW);
// *** WFI could be implemented here and depends on TW
///////////////////////////////////////////
// WFI timeout Privileged Spec 3.1.6.5
///////////////////////////////////////////
if (`U_SUPPORTED) begin
logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1;
assign WFICountPlus1 = WFICount + 1;
floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount); // count while in WFI
assign WFITimeoutM = STATUS_TW & PrivilegeModeW != `M_MODE & WFICount[`WFI_TIMEOUT_BIT];
end else assign WFITimeoutM = 0;
///////////////////////////////////////////
// decode privileged instructions
///////////////////////////////////////////
privdec pmd(.InstrM(InstrM[31:20]),
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM,
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM, .WFITimeoutM,
.PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM,
.sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM);
@ -233,7 +224,7 @@ module privileged (
.PCM,
.InstrMisalignedAdrM, .IEUAdrM,
.InstrM,
.InstrValidM, .CommittedM, .DivE,
.InstrValidM, .CommittedM, .DivE,
.TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
.InterruptM,
.ExceptionM,

2
pipelined/src/privileged/trap.sv
View File

@ -46,7 +46,7 @@ module trap (
input logic [`XLEN-1:0] PCM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
input logic [31:0] InstrM,
input logic InstrValidM, CommittedM, DivE,
input logic InstrValidM, CommittedM, DivE,
output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
output logic InterruptM,
output logic ExceptionM,

3
pipelined/src/uncore/clint.sv
View File

@ -66,8 +66,7 @@ module clint (
if (`XLEN==64) assign #2 entry = {HADDR[15:3], 3'b000};
else assign #2 entry = {HADDR[15:2], 2'b00};
swbytemask swbytemask(.HSIZED, .HADDRD(entryd[2:0]), .ByteMask(ByteMaskM));
swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(entryd[2:0]), .ByteMask(ByteMaskM));
// DH 2/20/21: Eventually allow MTIME to run off a separate clock
// This will require synchronizing MTIME to the system clock

2
pipelined/src/uncore/gpio.sv
View File

@ -146,7 +146,7 @@ module gpio (
// chip i/o
// connect OUT to IN for loopback testing
if (`GPIO_LOOPBACK_TEST) assign input0d = GPIOPinsOut & input_en & output_en;
if (`GPIO_LOOPBACK_TEST) assign input0d = GPIOPinsOut & output_en | (GPIOPinsIn & input_en);
else assign input0d = GPIOPinsIn & input_en;
flop #(32) sync1(HCLK,input0d,input1d);
flop #(32) sync2(HCLK,input1d,input2d);

2
pipelined/src/uncore/ram.sv
View File

@ -56,7 +56,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
logic memwrite;
logic [3:0] busycount;
swbytemask swbytemask(.HSIZED, .HADDRD(HWADDR[2:0]), .ByteMask(ByteMaskM));
swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HWADDR[2:0]), .ByteMask(ByteMaskM));
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);

30
pipelined/src/uncore/uartPC16550D.sv
View File

@ -54,14 +54,22 @@ module uartPC16550D(
output logic SOUT, RTSb, DTRb, OUT1b, OUT2b
);
// signal to watch
// rxparityerr, RXBR[upper 3 bits]
// LSR bits 1 to 4 are based on parity, overrun, and framing errors
// txstate, rxstate
// loop, fifoenabled
// IER, RCR, MCR, LSR, MSR, DLL, DLM, RBR
// transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
// Registers
logic [10:0] RBR;
logic [7:0] FCR, LCR, LSR, SCR, DLL, DLM;
logic [3:0] IER, MSR;
logic [4:0] MCR;
(* mark_debug = "true" *) logic [10:0] RBR;
(* mark_debug = "true" *) logic [7:0] FCR, LCR, LSR, SCR, DLL, DLM;
(* mark_debug = "true" *) logic [3:0] IER, MSR;
(* mark_debug = "true" *) logic [4:0] MCR;
// Syncrhonized and delayed UART signals
logic SINd, DSRbd, DCDbd, CTSbd, RIbd;
@ -78,7 +86,7 @@ module uartPC16550D(
logic [16+`UART_PRESCALE-1:0] baudcount;
logic [3:0] rxoversampledcnt, txoversampledcnt; // count oversampled-by-16
logic [3:0] rxbitsreceived, txbitssent;
statetype rxstate, txstate;
(* mark_debug = "true" *) statetype rxstate, txstate;
// shift registrs and FIFOs
logic [9:0] rxshiftreg;
@ -90,11 +98,11 @@ module uartPC16550D(
logic [3:0] rxbitsexpected, txbitsexpected;
// receive data
logic [10:0] RXBR;
(* mark_debug = "true" *) logic [10:0] RXBR;
logic [6:0] rxtimeoutcnt;
logic rxcentered;
logic rxparity, rxparitybit, rxstopbit;
logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
(* mark_debug = "true" *) logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
logic rxdataready;
logic rxfifoempty, rxfifotriggered, rxfifotimeout;
logic rxfifodmaready;
@ -145,7 +153,8 @@ module uartPC16550D(
if (`FPGA) begin
//DLL <= #1 8'd38; // 35Mhz
//DLL <= #1 8'd11; // 10 Mhz
DLL <= #1 8'd33; // 30 Mhz
//DLL <= #1 8'd33; // 30 Mhz
DLL <= #1 8'd8; // 30 Mhz 230400
DLM <= #1 8'b0;
end else begin
DLL <= #1 8'd1; // this cannot be zero with DLM also zer0.
@ -162,10 +171,13 @@ module uartPC16550D(
3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0];
-----/\----- EXCLUDED -----/\----- */
// *** BUG FIX ME for now for the divider to be 38. Our clock is 35 Mhz. 35Mhz /(38 * 16) ~= 57600 baud, which is close enough to 57600 baud
// dll = freq / (baud * 16)
// 30Mhz / (57600 * 16) = 32.5
// 30Mhz / (230400 * 16) = 8.13
// freq /baud / 16 = div
//3'b000: if (DLAB) DLL <= #1 8'd38; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
//3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in
3'b000: if (DLAB) DLL <= #1 8'd33; //else TXHR <= #1 Din; // TX handled in
3'b000: if (DLAB) DLL <= #1 8'd8; //else TXHR <= #1 Din; // TX handled in
3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0];
3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing

2
pipelined/testbench/testbench-linux.sv
View File

@ -662,7 +662,7 @@ module testbench;
`checkEQ("PCW",PCW,ExpectedPCW)
//`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of
// compressed to uncompressed conversion
`checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.INSTRET_REGW,InstrCountW)
`checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW)
#2; // delay 2 ns.
if(`DEBUG_TRACE >= 5) begin
$display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW);

4
pipelined/testbench/testbench.sv
View File

@ -361,8 +361,8 @@ module riscvassertions;
// assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM");
assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS.");
assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS.");
//assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS.");
//assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS.");
end
endmodule

10
pipelined/testbench/tests.vh
View File

@ -1467,11 +1467,17 @@ string imperas32f[] = '{
"rv64i_m/privilege/WALLY-MTVEC", "002090",
"rv64i_m/privilege/WALLY-MVENDORID", "004090", */
"rv64i_m/privilege/WALLY-PMA", "0050a0",
"rv64i_m/privilege/WALLY-PMP", "0050a0"
"rv64i_m/privilege/WALLY-PMP", "0050a0",
// "rv64i_m/privilege/WALLY-SCAUSE", "002090",
// "rv64i_m/privilege/WALLY-scratch-01", "0040a0",
// "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0",
// "rv64i_m/privilege/WALLY-trap-01", "0050a0"
"rv64i_m/privilege/WALLY-trap-01", "0050a0",
"rv64i_m/privilege/WALLY-MIE-01", "0050a0",
"rv64i_m/privilege/WALLY-mtvec-01", "0050a0",
"rv64i_m/privilege/WALLY-stvec-01", "0050a0",
"rv64i_m/privilege/WALLY-PIE-stack-01", "0050a0",
"rv64i_m/privilege/WALLY-PIE-stack-s-01", "0050a0",
"rv64i_m/privilege/WALLY-trap-sret-01", "0050a0"
// "rv64i_m/privilege/WALLY-STVEC", "002090",
// "rv64i_m/privilege/WALLY-UCAUSE", "002090",

39
synthDC/Makefile
View File

@ -24,9 +24,11 @@ export SAIFPOWER ?= 0
CONFIGDIR ?= ${WALLY}/pipelined/config
CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*)
CONFIGFILESTRIM = $(notdir $(CONFIGFILES))
FREQS = 25 50 100 150 200 250 300 350 400
k = 3 6
print:
echo $(k)
echo $(CONFIGFILESTRIM)
echo $(DIRS)
default:
@echo "Basic synthesis procedure for Wally:"
@ -39,24 +41,25 @@ rv%.log: rv%
echo $<
DIRS = rv32e #rv32gc rv64ic rv64gc rv32ic
DIRS = rv32e rv32gc rv64ic rv32ic rv64gc
# DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic
# CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig
bpred:
@$(foreach kval, $(k), rm -rf $(CONFIGDIR)/rv64gc_bpred_$(kval);)
@$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);)
@$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;)
@$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;)
copy:
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;)
@$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;)
@$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
@$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
@$(foreach dir, $(DIRS), sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;)
@$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
del:
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;)
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_FPUoff;)
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP16;)
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP0;)
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noVirtMem;)
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noMulDiv;)
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_*;)
configs: $(DIRS)
$(DIRS):
@ -76,23 +79,25 @@ $(DIRS):
cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0
sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh
# No Virtual Memory
rm -rf $(CONFIGDIR)/$@_noVirtMem
cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noVirtMem
sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh
#no muldiv
rm -rf $(CONFIGDIR)/$@_noMulDiv
cp -r $(CONFIGDIR)/$@_noVirtMem $(CONFIGDIR)/$@_noMulDiv
cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv
sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh
#no priv
rm -rf $(CONFIGDIR)/$@_noPriv
cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv
sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
freqs:
@$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e TECH=sky130 FREQ=$(freq) MAXCORES=1;)
allsynth: $(CONFIGFILESTRIM)
$(CONFIGFILESTRIM):
make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=500 MAXCORES=1
make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky130 FREQ=1000 MAXCORES=1
synth:
@echo "DC Synthesis"
@mkdir -p hdl/

99
synthDC/hdl/wally-shared.vh
View File

@ -1,99 +0,0 @@
//////////////////////////////////////////
// wally-shared.vh
//
// Written: david_harris@hmc.edu 7 June 2021
//
// Purpose: Shared and default configuration values common to all designs
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// include shared constants
`include "wally-constants.vh"
// macros to define supported modes
// NOTE: No hardware support fo Q yet
`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
`define E_SUPPORTED ((`MISA >> 4) % 2 == 1)
`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
`define I_SUPPORTED ((`MISA >> 8) % 2 == 1)
`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1)
`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
// logarithm of XLEN, used for number of index bits to select
`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
// Floating-point half-precision
`define ZFH_SUPPORTED 0
// Floating point constants for Quad, Double, Single, and Half precisions
`define Q_LEN 128
`define Q_NE 15
`define Q_NF 112
`define Q_BIAS 16383
`define D_LEN 64
`define D_NE 11
`define D_NF 52
`define D_BIAS 1023
`define S_LEN 32
`define S_NE 8
`define S_NF 23
`define S_BIAS 127
`define H_LEN 16
`define H_NE 5
`define H_NF 10
`define H_BIAS 15
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN)
`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE)
`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF)
`define FMT (`Q_SUPPORTED ? 3 : `D_SUPPORTED ? 1 : `F_SUPPORTED ? 0 : 2)
`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)
// Floating point constants needed for FPU paramerterization
`define FPSIZES (`Q_SUPPORTED+`D_SUPPORTED+`F_SUPPORTED+`ZFH_SUPPORTED)
`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN)
`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE)
`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF)
`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 0 : 2)
`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS)
`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN)
`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE)
`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF)
`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 0 : 2)
`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS)
// Disable spurious Verilator warnings
/* verilator lint_off STMTDLY */
/* verilator lint_off ASSIGNDLY */
/* verilator lint_off PINCONNECTEMPTY */

4
synthDC/runSynth.sh Normal file
View File

@ -0,0 +1,4 @@
rm -r runs/*
make clean
make freqs TECH=sky130
python3 scripts/extractSummary.py

50
synthDC/scripts/extractSummary.py Executable file
View File

@ -0,0 +1,50 @@
#!/usr/bin/python3
# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022
import glob
import re
import csv
import linecache
import os
def main():
data = []
curr_dir = os.path.dirname(os.path.abspath(__file__))
output_file = os.path.join(curr_dir,"..","Summary.csv")
runs_dir = os.path.join(curr_dir,"..","runs/*/reports/wallypipelinedcore_qor.rep")
search_strings = [
"Critical Path Length:", "Cell Area:", "Overall Compile Time:",
"Critical Path Clk Period:", "Critical Path Slack:"
]
for name in glob.glob(runs_dir):
f = open(name, 'r')
trimName = re.search("wallypipelinedcore_(.*?)_2022",name).group(1)
output = {'Name':trimName}
num_lines = len(f.readlines())
curr_line_index = 0
while curr_line_index < num_lines:
line = linecache.getline(name, curr_line_index)
for search_string in search_strings:
if search_string in line:
val = getVal(name,search_string,line,curr_line_index)
output[search_string] = val
curr_line_index +=1
data += [output]
with open(output_file, 'w') as csvfile:
writer = csv.DictWriter(csvfile, fieldnames=['Name'] + search_strings)
writer.writeheader()
writer.writerows(data)
def getVal(filename, search_string, line, line_index):
data = re.search(f"{search_string} *(.*?)\\n", line).group(1)
if data == '': #sometimes data is stored in two line
data = linecache.getline(filename, line_index+1).strip()
return data
if __name__=="__main__":
main()

1
tests/fp/run_all.sh
View File

@ -3,4 +3,3 @@
mkdir -p vectors
./create_vectors.sh
./remove_spaces.sh
./append_ctrlSig.sh

9
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
View File

@ -35,9 +35,10 @@ rv64i_sc_tests = \
WALLY-CSR-permission-s-01 \
WALLY-CSR-permission-u-01 \
WALLY-misa-01 \
WALLY-sscratch-s-01 \
WALLY-AMO \
WALLY-LRSC \
# WALLY-scratch-01 \
# WALLY-sscratch-s-01 \
# WALLY-scratch-01 \
@ -58,6 +59,12 @@ target_tests_nosim = \
WALLY-MVENDORID \
WALLY-CSR-PERMISSIONS-M \
WALLY-CSR-PERMISSIONS-S \
WALLY-mtvec-01 \
WALLY-stvec-01 \
WALLY-MIE-01 \
WALLY-PIE-stack-01 \
WALLY-PIE-stack-s-01 \
WALLY-trap-sret-01 \
WALLY-trap-01 \
# Have all 0's in references!
#WALLY-MEPC \

1024
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MIE-01.reference_output Normal file
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File diff suppressed because it is too large Load Diff

1024
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PIE-stack-01.reference_output Normal file
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1024
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PIE-stack-s-01.reference_output Normal file
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File diff suppressed because it is too large Load Diff

30
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output
View File

@ -1,3 +1,17 @@
00000aaa # Test 5.3.1.5: readback value of SIE after enabling all interrupts.
00000000
00000007 # mcause from m time interrupt
80000000
00000000 # mtval for mtime interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
0000000b # mcause from M mode ecall from test termination
00000000
00000000 # mtval of ecall (*** defined to be zero for now)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
deadbeef
deadbeef
deadbeef
@ -1007,18 +1021,4 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

80
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-stvec-01.reference_output
View File

@ -1,43 +1,43 @@
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
00000aaa # Test 5.3.1.5: readback value of MIE after enabling all interrupts.
00000000
00000222 # readback value of mideleg after attempting to delegate all interrupts.
00000000
0000000b # mcause from ecall for going from M mode to S mode
00000000
00000000 # mtval of ecall (*** defined to be zero for now)
00000000
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000001 # mcause from s soft interrupt
80000000
00000000 # mtval for ssoft interrupt (0x0)
00000000
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000009 # mcause from ecall for going from S mode to M mode
00000000
00000000 # mtval of ecall (*** defined to be zero for now)
00000000
00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
0000000b # mcause from ecall for going from M mode to U mode
00000000
00000000 # mtval of ecall (*** defined to be zero for now)
00000000
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000001 # mcause from s soft interrupt from user mode this time
80000000
00000000 # mtval for mtime interrupt (0x0)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000008 # mcause from U mode ecall from test termination
00000000
00000000 # mtval of ecall (*** defined to be zero for now)
00000000
00000000 # masked out mstatus.MPP = 00, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
deadbeef
deadbeef
deadbeef

180
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
View File

@ -1,5 +1,11 @@
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
00000000
00000000 # mcause from instruction addr misaligned fault
00000000
800003d2 # mtval of faulting instruction adress (0x800003d3)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
00000001 # mcause from an instruction access fault
00000000
00000000 # mtval of faulting instruction address (0x0)
@ -14,13 +20,13 @@
00000000
00000003 # mcause from Breakpoint
00000000
800003ec # mtval of breakpoint instruction adress (0x800003ec)
80000404 # mtval of breakpoint instruction adress (0x80000404)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
00000004 # mcause from load address misaligned
00000000
800003f5 # mtval of misaligned address (0x800003f5)
8000040d # mtval of misaligned address (0x8000040d)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
@ -32,7 +38,7 @@
00000000
00000006 # mcause from store misaligned
00000000
80000411 # mtval of address with misaligned store instr (0x80000410)
80000429 # mtval of address with misaligned store instr (0x80000429)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
@ -60,7 +66,31 @@
00000000
00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
000007ec # value to indicate a vectored interrupts
0007ec01 # value to indicate successful vectoring on s soft interrupt
00000000
00000001 # mcause value from s soft interrupt
80000000
00000000 # mtval for ssoft interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
0007ec03 # value to indicate successful vectoring on m soft interrupt
00000000
00000003 # mcause value from m soft interrupt
80000000
00000000 # mtval for msoft interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
0007ec05 # value to indicate successful vectoring on s time interrupt
00000000
00000005 # mcause value from s time interrupt
80000000
00000000 # mtval for stime interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
0007ec07 # value to indicate successful vectoring on m time interrupt
00000000
00000007 # mcause value from m time interrupt
80000000
@ -68,15 +98,15 @@
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
000007ec # value to indicate a vectored interrupts
0007ec09 # value to indicate successful vectoring on s ext interrupt
00000000
00000001 # mcause value from m soft interrupt
00000009 # mcause value from s ext interrupt
80000000
00000000 # mtval for msoft interrupt (0x0)
00000000 # mtval for sext interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
000007ec # value to indicate a vectored interrupts
0007ec0b # value to indicate successful vectoring on m ext interrupt
00000000
0000000b # mcause value from m ext interrupt
80000000
@ -84,11 +114,17 @@
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
0000b309 # medeleg after attempted write of all 1's (only some bits are writeable)
00000000
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
ffffffff
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
00000000
00000001 # Test 5.3.1.4: mcause from an instruction access fault
00000000 # mcause from instruction addr misaligned fault
00000000
800003d2 # mtval of faulting instruction adress (0x800003d3)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
00000001 # mcause from an instruction access fault
00000000
00000000 # mtval of faulting instruction address (0x0)
00000000
@ -102,13 +138,13 @@
00000000
00000003 # mcause from Breakpoint
00000000
800003ec # mtval of breakpoint instruction adress (0x800003ec)
80000404 # mtval of breakpoint instruction adress (0x80000404)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
00000004 # mcause from load address misaligned
00000000
800003f5 # mtval of misaligned address (0x800003f5)
8000040d # mtval of misaligned address (0x8000040d)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
@ -120,7 +156,7 @@
00000000
00000006 # mcause from store misaligned
00000000
80000411 # mtval of address with misaligned store instr (0x80000410)
80000429 # mtval of address with misaligned store instr (0x80000429)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
@ -136,23 +172,23 @@
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
000007ec # value to indicate a vectored interrupts
0007ec03 # value to indicate successful vectoring on m soft interrupt
00000000
00000007 # mcause value from time interrupt
80000000
00000000 # mtval for mtime interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
000007ec # value to indicate a vectored interrupts
00000000
00000001 # mcause value from m soft interrupt
00000003 # mcause value from m soft interrupt
80000000
00000000 # mtval for msoft interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
000007ec # value to indicate a vectored interrupts
0007ec07 # value to indicate successful vectoring on m time interrupt
00000000
00000007 # mcause value from m time interrupt
80000000
00000000 # mtval for mtime interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
0007ec0b # value to indicate successful vectoring on m ext interrupt
00000000
0000000b # mcause value from m ext interrupt
80000000
@ -978,97 +1014,3 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
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deadbeef

1024
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-sret-01.reference_output Normal file
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44
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIE-01.S Normal file
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@ -0,0 +1,44 @@
///////////////////////////////////////////
//
// WALLY-MIE
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1.
WRITE_READ_CSR mie, 0x0 // force zeroing out mie CSR.
// test 5.3.1.6 Interrupt enabling and priority tests
// note that none of these interrupts should be caught or handled.
jal cause_m_soft_interrupt
END_TESTS
TEST_STACK_AND_DATA

49
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-01.S Normal file
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@ -0,0 +1,49 @@
///////////////////////////////////////////
//
// WALLY-privilege-interrupt-enable-stack
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1
WRITE_READ_CSR mie, 0xFFF
// test 5.3.1.6 Interrupt enabling and priority tests
// Cause interrupt, ensuring that status.mie = 0 , status.mpie = 1, and status.mpp = 11 during trap handling
jal cause_m_soft_interrupt
li x28, 0x8
csrc mstatus, x28 // set mstatus.MIE bit to 0. interrupts from M mode should not happen
// attempt to cause interrupt, it should not go through
jal cause_m_soft_interrupt
END_TESTS
TEST_STACK_AND_DATA

53
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-s-01.S Normal file
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@ -0,0 +1,53 @@
///////////////////////////////////////////
//
// WALLY-privilege-interrupt-enable-stack
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1 // necessary so we can go to S mode
TRAP_HANDLER s, DEBUG=1 // neccessary to handle s mode interrupts.
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1
WRITE_READ_CSR mie, 0xFFF // enable all interrupts, including supervisor ones
WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode.
// test 5.3.1.6 Interrupt enabling and priority tests
GOTO_S_MODE
// Cause interrupt, ensuring that status.sie = 0 , status.spie = 1, and status.spp = 1 during trap handling
jal cause_s_soft_interrupt
li x28, 0x2
csrc sstatus, x28 // set sstatus.SIE bit to 0. interrupts from S mode should not happen
// attempt to cause interrupt, it should not go through
jal cause_s_soft_interrupt
END_TESTS
TEST_STACK_AND_DATA

161
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
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@ -84,7 +84,7 @@ cause_instr_access:
ret
cause_illegal_instr:
.word 0x00000000 // a 32 bit zros is an illegal instruction
.word 0x00000000 // 32 bit zero is an illegal instruction
ret
cause_breakpnt:
@ -118,7 +118,7 @@ cause_ecall:
ecall
ret
cause_time_interrupt:
cause_m_time_interrupt:
// The following code works for both RV32 and RV64.
// RV64 alone would be easier using double-word adds and stores
li x28, 0x30 // Desired offset from the present time
@ -132,23 +132,99 @@ cause_time_interrupt:
sw x31,4(x29) // store into most significant word of MTIMECMP
nowrap:
sw x28, 0(x29) // store into least significant word of MTIMECMP
loop:
wfi
j loop // wait until interrupt occurs
time_loop:
wfi
j time_loop // wait until interrupt occurs
ret
cause_soft_interrupt:
cause_s_time_interrupt:
li x28, 0x20
csrs mip, x28 // set supervisor time interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
nop // added extra nops in so the csrs can get through the pipeline before returning.
ret
cause_m_soft_interrupt:
la x28, 0x02000000 // MSIP register in CLINT
li x29, 1 // 1 in the lsb
sw x29, 0(x28) // Write MSIP bit
ret
cause_ext_interrupt:
cause_s_soft_interrupt:
li x28, 0x2
csrs sip, x28 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
ret
cause_m_ext_interrupt:
# ========== Configure PLIC ==========
# m priority threshold = 0
li x28, 0xC200000
li x29, 0
sw x29, 0(x28)
# source 3 (GPIO) priority = 1
li x28, 0xC000000
li x29, 1
sw x29, 0x0C(x28)
# enable source 3 in M Mode
li x28, 0x0C002000
li x29, 0b1000
sw x29, 0(x28)
li x28, 0x10060000 // load base GPIO memory location
li x29, 0x1
sw x29, 8(x28) // enable the first pin as an output
sw x29, 28(x28) // set first pin to high interrupt enable
sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
sw x29, 0x08(x28) // enable the first pin as an output
sw x0, 0x1C(x28) // clear rise_ip
sw x0, 0x24(x28) // clear fall_ip
sw x0, 0x2C(x28) // clear high_ip
sw x0, 0x34(x28) // clear low_ip
sw x29, 0x28(x28) // set first pin to interrupt on a rising value
sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt)
m_ext_loop:
wfi
lw x29, 0x8(x28)
bnez x28, m_ext_loop // go through this loop until the trap handler has disabled the GPIO output pins.
ret
cause_s_ext_interrupt_GPIO:
# ========== Configure PLIC ==========
# s priority threshold = 0
li x28, 0xC201000
li x29, 0
sw x29, 0(x28)
# m priority threshold = 7
li x28, 0xC200000
li x29, 7
sw x29, 0(x28)
# source 3 (GPIO) priority = 1
li x28, 0xC000000
li x29, 1
sw x29, 0x0C(x28)
# enable source 3 in S mode
li x28, 0x0C002080
li x29, 0b1000
sw x29, 0(x28)
li x28, 0x10060000 // load base GPIO memory location
li x29, 0x1
sw x29, 0x08(x28) // enable the first pin as an output
sw x0, 0x1C(x28) // clear rise_ip
sw x0, 0x24(x28) // clear fall_ip
sw x0, 0x2C(x28) // clear high_ip
sw x0, 0x34(x28) // clear low_ip
sw x29, 0x28(x28) // set first pin to interrupt on a rising value
sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt)
s_ext_loop:
wfi
lw x29, 0x8(x28)
bnez x28, s_ext_loop // go through this loop until the trap handler has disabled the GPIO output pins.
ret
cause_s_ext_interrupt_IP:
li x28, 0x200
csrs mip, x28 // set supervisor external interrupt pending.
ret
end_trap_triggers:
@ -216,7 +292,7 @@ end_trap_triggers:
//
// --------------------------------------------------------------------------------------------
.align 2
.align 3
trap_handler_\MODE\():
j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
@ -273,18 +349,19 @@ trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since w
// Respond to trap based on cause
// All interrupts should return after being logged
csrr x1, \MODE\()cause
slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
li x5, 0x8000000000000000 // if msb is set, it is an interrupt
and x5, x5, x1
bnez x5, interrupt_handler_\MODE\() // return from interrupt
// Other trap handling is specified in the vector Table
la x5, exception_vector_table_\MODE\()
slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
add x5, x5, x1 // compute address of vector in Table
ld x5, 0(x5) // fectch address of handler from vector Table
jr x5 // and jump to the handler
interrupt_handler_\MODE\():
la x5, interrupt_vector_table_\MODE\() // NOTE THIS IS NOT THE SAME AS VECTORED INTERRUPTS!!!
slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
add x5, x5, x1 // compute address of vector in Table
ld x5, 0(x5) // fectch address of handler from vector Table
jr x5 // and jump to the handler
@ -343,6 +420,7 @@ trapreturn_finished_\MODE\():
ld x7, -24(sp) // restore registers from stack before returning
ld x5, -16(sp)
ld x1, -8(sp)
csrrw sp, \MODE\()scratch, sp // switch sp and scratch stack back to restore the non-trap stack pointer
\MODE\()ret // return from trap
ecallhandler_\MODE\():
@ -364,7 +442,7 @@ ecallhandler_changetomachinemode_\MODE\():
ecallhandler_changetosupervisormode_\MODE\():
// Force status.MPP (bits 12:11) to 01 to enter supervisor mode after mret
li x1, 0b1100000000000
li x1, 0b1000000000000
csrc \MODE\()status, x1
li x1, 0b0100000000000
csrs \MODE\()status, x1
@ -440,23 +518,52 @@ vectored_int_end_\MODE\():
j trap_stack_saved_\MODE\()
soft_interrupt_\MODE\():
la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
sw x0, 0(x28)
j trapreturn_\MODE\()
la x5, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
sw x0, 0(x5)
csrci \MODE\()ip, 0x2 // clear supervisor software interrupt pending bit
ld x1, -8(sp) // load return address from stack into ra (the address to return to after causing this interrupt)
// Note: we do this because the mepc loads in the address of the instruction after the sw that causes the interrupt
// This means that this trap handler will return to the next address after that one, which might be unpredictable behavior.
j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
time_interrupt_\MODE\():
la x29, 0x02004000 // MTIMECMP register in CLINT
li x30, 0xFFFFFFFF
sd x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
la x5, 0x02004000 // MTIMECMP register in CLINT
li x7, 0xFFFFFFFF
sd x7, 0(x5) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
ld x1, -8(sp) // load return address from stack into ra (the address AFTER the jal to the faulting address)
li x5, 0x20
csrc \MODE\()ip, x5
ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete)
j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
ext_interrupt_\MODE\():
li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
sw x0, 8(x28) // disable the first pin as an output
sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
j trapreturn_\MODE\()
# reset PLIC to turn off external interrupts
# priority threshold = 7
li x28, 0xC200000
li x5, 0x7
sw x5, 0(x28)
# source 3 (GPIO) priority = 0
li x28, 0xC000000
li x5, 0
sw x5, 0x0C(x28)
# disable source 3
li x28, 0x0C002000
li x5, 0b0000
sw x5, 0(x28)
li x5, 0x200
csrc \MODE\()ip, x5
ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete)
j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
// Table of trap behavior
// lists what to do on each exception (not interrupts)
@ -485,17 +592,17 @@ exception_vector_table_\MODE\():
.align 3 // aligns this data table to an 8 byte boundary
interrupt_vector_table_\MODE\():
.8byte segfault_\MODE\() // 0: reserved
.8byte s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
.8byte soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
.8byte segfault_\MODE\() // 2: reserved
.8byte m_soft_vector_\MODE\() // 3: breakpoint
.8byte soft_interrupt_\MODE\() // 3: breakpoint
.8byte segfault_\MODE\() // 4: reserved
.8byte s_time_vector_\MODE\() // 5: load access fault
.8byte time_interrupt_\MODE\() // 5: load access fault
.8byte segfault_\MODE\() // 6: reserved
.8byte m_time_vector_\MODE\() // 7: store access fault
.8byte time_interrupt_\MODE\() // 7: store access fault
.8byte segfault_\MODE\() // 8: reserved
.8byte s_ext_vector_\MODE\() // 9: ecall from S-mode
.8byte ext_interrupt_\MODE\() // 9: ecall from S-mode
.8byte segfault_\MODE\() // 10: reserved
.8byte m_ext_vector_\MODE\() // 11: ecall from M-mode
.8byte ext_interrupt_\MODE\() // 11: ecall from M-mode
.align 3
trap_return_pagetype_table_\MODE\():

11
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S
View File

@ -25,20 +25,19 @@
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.5 Unvectored interrupt tests
TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
li x28, 0x8
csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
csrs mstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
WRITE_READ_CSR mie, 0xFFF
// cause traps, ensuring that we DONT go through the vectored part of the trap handler
// *** this assumes that interrupt code 0 remains reserved
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
jal cause_m_time_interrupt
END_TESTS

25
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S
View File

@ -25,30 +25,29 @@
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.5 Unvectored interrupt tests
TRAP_HANDLER m, VECTORED=0, DEBUG=1 // necessary to handle changing modes
TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
// li x28, 0x8
// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1
WRITE_READ_CSR mie, 0xFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
// cause traps, ensuring that we DONT go through the vectored part of the trap handler
GOTO_S_MODE
// cause traps, ensuring that we DONT go through the vectored part of the trap handler
// *** this assumes that interrupt code 0 remains reserved
jal cause_s_soft_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
GOTO_M_MODE
GOTO_U_MODE
jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
GOTO_U_MODE // Should cause software interrupt to fire off.
END_TESTS

28
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
View File

@ -35,7 +35,7 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented
// test 5.3.1.4 Basic trap tests
// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
jal cause_instr_addr_misaligned
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt
@ -47,16 +47,23 @@ GOTO_U_MODE // Causes M mode ecall
GOTO_S_MODE // Causes U mode ecall
GOTO_M_MODE // Causes S mode ecall
jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
jal cause_ext_interrupt
jal cause_s_soft_interrupt
jal cause_m_soft_interrupt
jal cause_s_time_interrupt
jal cause_m_time_interrupt
//jal cause_s_ext_interrupt_GPIO
jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO.
jal cause_m_ext_interrupt
// try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
jal cause_instr_addr_misaligned
jal cause_instr_access
jal cause_illegal_instr
jal cause_breakpnt
@ -66,9 +73,14 @@ jal cause_store_addr_misaligned
jal cause_store_acc
jal cause_ecall // M mode ecall
jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
jal cause_ext_interrupt
jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode.
jal cause_m_soft_interrupt
jal cause_s_time_interrupt
jal cause_m_time_interrupt
//jal cause_s_ext_interrupt_GPIO
jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO.
jal cause_m_ext_interrupt
END_TESTS

42
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S Normal file
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@ -0,0 +1,42 @@
///////////////////////////////////////////
//
// WALLY-trap-sret
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
TRAP_HANDLER m, DEBUG=1
// test 5.3.1.6 Interrupt enabling and priority tests
li x28, 0x400000
csrs mstatus, x28 // Set mstatus.tsr to 1.
GOTO_S_MODE
sret // attempt to run sret instruction.
// should cause illegal instruction exception despite being in s mode
END_TESTS
TEST_STACK_AND_DATA