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Added new asserts to testbench.

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Ross Thompson 2022-03-11 15:41:53 -06:00
parent e802deb4d6
commit d68446cf92
1 changed files with 2 additions and 0 deletions
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pipelined/testbench/testbench.sv
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@ -359,6 +359,8 @@ module riscvassertions;
// assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM");
assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS.");
assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS.");
end
endmodule