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Reduced complexity of the address selection during flush.

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This commit is contained in:
Ross Thompson 2022-02-11 22:27:27 -06:00
parent a0ee2f3d99
commit cb3d71a63d
2 changed files with 4 additions and 4 deletions
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4
pipelined/src/cache/cache.sv vendored
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@ -71,8 +71,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
logic [1:0] SelAdr;
logic [SETLEN-1:0] RAdr;
logic [LINELEN-1:0] CacheWriteData;
logic SetValid, ClearValid;
logic SetDirty, ClearDirty;
logic ClearValid;
logic ClearDirty;
logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0];
logic [NUMWAYS-1:0] WayHit;
logic CacheHit;

4
pipelined/src/cache/cachefsm.sv vendored
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@ -236,10 +236,10 @@ module cachefsm
(CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) |
resetDelay) ? 2'b01 :
((CurrState == STATE_FLUSH) |
(CurrState == STATE_FLUSH_CHECK & ~(VictimDirty & FlushFlag)) |
(CurrState == STATE_FLUSH_CHECK) |
(CurrState == STATE_FLUSH_INCR) |
(CurrState == STATE_FLUSH_WRITE_BACK) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag))) ? 2'b10 :
(CurrState == STATE_FLUSH_CLEAR_DIRTY)) ? 2'b10 :
2'b00;