mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
added CSR permission and minfor to 32 bit tests
This commit is contained in:
Kip Macsai-Goren
parent
5df0a9531f
commit
6c1383e2a0
@ -1550,7 +1550,9 @@ string wally32i[] = '{
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`WALLYTEST,
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"rv32i_m/privilege/WALLY-MMU-SV32", "4080",
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"rv32i_m/privilege/WALLY-PMP", "4080",
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"rv32i_m/privilege/WALLY-PMA", "4080"
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"rv32i_m/privilege/WALLY-CSR-permission-s-01", "5080",
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"rv32i_m/privilege/WALLY-CSR-permission-u-01", "5080",
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"rv32i_m/privilege/WALLY-minfo-01", "4080"
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};
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string wally32periph[] = '{
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@ -29,7 +29,10 @@
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rv32i_sc_tests = \
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WALLY-MMU-SV32 \
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WALLY-PMP
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WALLY-PMP \
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WALLY-CSR-permission-s-01 \
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WALLY-CSR-permission-u-01 \
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WALLY-minfo-01
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target_tests_nosim = WALLY-PMA \
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,157 @@
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///////////////////////////////////////////
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//
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// WALLY-CSR-permissions
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//
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// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
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//
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// Created 2022-02-05
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "WALLY-TEST-LIB-32.h"
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INIT_TESTS
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s_file_begin:
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# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode.
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# *** several of these appear not to be implemented in the assembler?
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# I get "assembler messages: error: unkown CSR" with many of them.
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GOTO_S_MODE 0x0, 0x0
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# Attempt to write 0xbad to each of these CSRs and read the value back
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# should result in an illegal instruction for the write and read, respectively
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# Machine information Registers
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WRITE_READ_CSR mvendorid, 0xbad
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WRITE_READ_CSR marchid, 0xbad
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WRITE_READ_CSR mimpid, 0xbad
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WRITE_READ_CSR mhartid, 0xbad
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# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
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# Machine Trap Setup
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WRITE_READ_CSR mstatus, 0xbad
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WRITE_READ_CSR misa, 0xbad
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WRITE_READ_CSR medeleg, 0xbad
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WRITE_READ_CSR mideleg, 0xbad
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WRITE_READ_CSR mie, 0xbad
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WRITE_READ_CSR mtvec, 0xbad
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WRITE_READ_CSR mcounteren, 0xbad
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# Machine Trap Handling
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WRITE_READ_CSR mscratch, 0xbad
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WRITE_READ_CSR mepc, 0xbad
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WRITE_READ_CSR mcause, 0xbad
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WRITE_READ_CSR mtval, 0xbad
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WRITE_READ_CSR mip, 0xbad
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# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
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# WRITE_READ_CSR mtval2, 0xbad
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# Machine Configuration
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# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
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# WRITE_READ_CSR mseccgf, 0xbad
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# Machine Memory Protection
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WRITE_READ_CSR pmpcfg0, 0xbad
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WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
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WRITE_READ_CSR pmpaddr0, 0xbad
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WRITE_READ_CSR pmpaddr1, 0xbad
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WRITE_READ_CSR pmpaddr2, 0xbad
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WRITE_READ_CSR pmpaddr3, 0xbad
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WRITE_READ_CSR pmpaddr4, 0xbad
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WRITE_READ_CSR pmpaddr5, 0xbad
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WRITE_READ_CSR pmpaddr6, 0xbad
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WRITE_READ_CSR pmpaddr7, 0xbad
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WRITE_READ_CSR pmpaddr8, 0xbad
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WRITE_READ_CSR pmpaddr9, 0xbad
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WRITE_READ_CSR pmpaddr10, 0xbad
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WRITE_READ_CSR pmpaddr11, 0xbad
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WRITE_READ_CSR pmpaddr12, 0xbad
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WRITE_READ_CSR pmpaddr13, 0xbad
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WRITE_READ_CSR pmpaddr14, 0xbad
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WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
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# Machine Counter/Timers
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WRITE_READ_CSR mcycle, 0xbad
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WRITE_READ_CSR minstret, 0xbad
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WRITE_READ_CSR mhpmcounter3, 0xbad
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WRITE_READ_CSR mhpmcounter4, 0xbad
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WRITE_READ_CSR mhpmcounter5, 0xbad
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WRITE_READ_CSR mhpmcounter6, 0xbad
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WRITE_READ_CSR mhpmcounter7, 0xbad
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WRITE_READ_CSR mhpmcounter8, 0xbad
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WRITE_READ_CSR mhpmcounter9, 0xbad
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WRITE_READ_CSR mhpmcounter10, 0xbad
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WRITE_READ_CSR mhpmcounter11, 0xbad
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WRITE_READ_CSR mhpmcounter12, 0xbad
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WRITE_READ_CSR mhpmcounter13, 0xbad
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WRITE_READ_CSR mhpmcounter14, 0xbad
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WRITE_READ_CSR mhpmcounter15, 0xbad
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WRITE_READ_CSR mhpmcounter16, 0xbad
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WRITE_READ_CSR mhpmcounter17, 0xbad
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WRITE_READ_CSR mhpmcounter18, 0xbad
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WRITE_READ_CSR mhpmcounter19, 0xbad
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WRITE_READ_CSR mhpmcounter20, 0xbad
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WRITE_READ_CSR mhpmcounter21, 0xbad
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WRITE_READ_CSR mhpmcounter22, 0xbad
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WRITE_READ_CSR mhpmcounter23, 0xbad
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WRITE_READ_CSR mhpmcounter24, 0xbad
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WRITE_READ_CSR mhpmcounter25, 0xbad
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WRITE_READ_CSR mhpmcounter26, 0xbad
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WRITE_READ_CSR mhpmcounter27, 0xbad
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WRITE_READ_CSR mhpmcounter28, 0xbad
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WRITE_READ_CSR mhpmcounter29, 0xbad
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WRITE_READ_CSR mhpmcounter30, 0xbad
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WRITE_READ_CSR mhpmcounter31, 0xbad
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# Machine Counter Setup
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WRITE_READ_CSR mcountinhibit, 0xbad
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WRITE_READ_CSR mhpmevent3, 0xbad
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WRITE_READ_CSR mhpmevent4, 0xbad
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WRITE_READ_CSR mhpmevent5, 0xbad
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WRITE_READ_CSR mhpmevent6, 0xbad
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WRITE_READ_CSR mhpmevent7, 0xbad
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WRITE_READ_CSR mhpmevent8, 0xbad
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WRITE_READ_CSR mhpmevent9, 0xbad
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WRITE_READ_CSR mhpmevent10, 0xbad
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WRITE_READ_CSR mhpmevent11, 0xbad
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WRITE_READ_CSR mhpmevent12, 0xbad
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WRITE_READ_CSR mhpmevent13, 0xbad
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WRITE_READ_CSR mhpmevent14, 0xbad
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WRITE_READ_CSR mhpmevent15, 0xbad
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WRITE_READ_CSR mhpmevent16, 0xbad
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WRITE_READ_CSR mhpmevent17, 0xbad
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WRITE_READ_CSR mhpmevent18, 0xbad
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WRITE_READ_CSR mhpmevent19, 0xbad
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WRITE_READ_CSR mhpmevent20, 0xbad
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WRITE_READ_CSR mhpmevent21, 0xbad
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WRITE_READ_CSR mhpmevent22, 0xbad
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WRITE_READ_CSR mhpmevent23, 0xbad
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WRITE_READ_CSR mhpmevent24, 0xbad
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WRITE_READ_CSR mhpmevent25, 0xbad
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WRITE_READ_CSR mhpmevent26, 0xbad
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WRITE_READ_CSR mhpmevent27, 0xbad
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WRITE_READ_CSR mhpmevent28, 0xbad
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WRITE_READ_CSR mhpmevent29, 0xbad
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WRITE_READ_CSR mhpmevent30, 0xbad
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WRITE_READ_CSR mhpmevent31, 0xbad
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END_TESTS
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TEST_STACK_AND_DATA
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@ -0,0 +1,173 @@
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///////////////////////////////////////////
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//
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// WALLY-CSR-permissions
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//
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// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
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//
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// Created 2022-02-05
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "WALLY-TEST-LIB-32.h"
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INIT_TESTS
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s_file_begin:
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# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode.
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GOTO_U_MODE 0x0, 0x0
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# Attempt to write 0xbad to each of these CSRs and read the value back
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# should result in an illegal instruction for the write and read, respectively
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# Supervisor Trap Setup
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WRITE_READ_CSR sstatus, 0xbad
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WRITE_READ_CSR sie, 0xbad
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WRITE_READ_CSR stvec, 0xbad
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WRITE_READ_CSR scounteren, 0xbad
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# Supervisor Configuration
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# WRITE_READ_CSR senvcfg, 0xbad # *** these appear not to be implemented in the compile step of make???
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# Supervisor Trap Handling
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WRITE_READ_CSR sscratch, 0xbad
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WRITE_READ_CSR sepc, 0xbad
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WRITE_READ_CSR scause, 0xbad
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WRITE_READ_CSR stval, 0xbad
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WRITE_READ_CSR sip, 0xbad
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# Supervisor Protection and Translation
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WRITE_READ_CSR satp, 0xbad
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# Machine information Registers
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WRITE_READ_CSR mvendorid, 0xbad
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WRITE_READ_CSR marchid, 0xbad
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WRITE_READ_CSR mimpid, 0xbad
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WRITE_READ_CSR mhartid, 0xbad
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# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
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# Machine Trap Setup
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WRITE_READ_CSR mstatus, 0xbad
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WRITE_READ_CSR misa, 0xbad
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WRITE_READ_CSR medeleg, 0xbad
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WRITE_READ_CSR mideleg, 0xbad
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WRITE_READ_CSR mie, 0xbad
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WRITE_READ_CSR mtvec, 0xbad
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WRITE_READ_CSR mcounteren, 0xbad
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# Machine Trap Handling
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WRITE_READ_CSR mscratch, 0xbad
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WRITE_READ_CSR mepc, 0xbad
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WRITE_READ_CSR mcause, 0xbad
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WRITE_READ_CSR mtval, 0xbad
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WRITE_READ_CSR mip, 0xbad
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# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in the compile step of make???
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# WRITE_READ_CSR mtval2, 0xbad
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# Machine Configuration
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# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make???
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# WRITE_READ_CSR mseccgf, 0xbad
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# Machine Memory Protection
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WRITE_READ_CSR pmpcfg0, 0xbad
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WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
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WRITE_READ_CSR pmpaddr0, 0xbad
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WRITE_READ_CSR pmpaddr1, 0xbad
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WRITE_READ_CSR pmpaddr2, 0xbad
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WRITE_READ_CSR pmpaddr3, 0xbad
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WRITE_READ_CSR pmpaddr4, 0xbad
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WRITE_READ_CSR pmpaddr5, 0xbad
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WRITE_READ_CSR pmpaddr6, 0xbad
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WRITE_READ_CSR pmpaddr7, 0xbad
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WRITE_READ_CSR pmpaddr8, 0xbad
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WRITE_READ_CSR pmpaddr9, 0xbad
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WRITE_READ_CSR pmpaddr10, 0xbad
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WRITE_READ_CSR pmpaddr11, 0xbad
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WRITE_READ_CSR pmpaddr12, 0xbad
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WRITE_READ_CSR pmpaddr13, 0xbad
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WRITE_READ_CSR pmpaddr14, 0xbad
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WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
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# Machine Counter/Timers
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WRITE_READ_CSR mcycle, 0xbad
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WRITE_READ_CSR minstret, 0xbad
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WRITE_READ_CSR mhpmcounter3, 0xbad
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WRITE_READ_CSR mhpmcounter4, 0xbad
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WRITE_READ_CSR mhpmcounter5, 0xbad
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WRITE_READ_CSR mhpmcounter6, 0xbad
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WRITE_READ_CSR mhpmcounter7, 0xbad
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WRITE_READ_CSR mhpmcounter8, 0xbad
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WRITE_READ_CSR mhpmcounter9, 0xbad
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WRITE_READ_CSR mhpmcounter10, 0xbad
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WRITE_READ_CSR mhpmcounter11, 0xbad
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WRITE_READ_CSR mhpmcounter12, 0xbad
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WRITE_READ_CSR mhpmcounter13, 0xbad
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WRITE_READ_CSR mhpmcounter14, 0xbad
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WRITE_READ_CSR mhpmcounter15, 0xbad
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WRITE_READ_CSR mhpmcounter16, 0xbad
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WRITE_READ_CSR mhpmcounter17, 0xbad
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WRITE_READ_CSR mhpmcounter18, 0xbad
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WRITE_READ_CSR mhpmcounter19, 0xbad
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WRITE_READ_CSR mhpmcounter20, 0xbad
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WRITE_READ_CSR mhpmcounter21, 0xbad
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WRITE_READ_CSR mhpmcounter22, 0xbad
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WRITE_READ_CSR mhpmcounter23, 0xbad
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WRITE_READ_CSR mhpmcounter24, 0xbad
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WRITE_READ_CSR mhpmcounter25, 0xbad
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WRITE_READ_CSR mhpmcounter26, 0xbad
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WRITE_READ_CSR mhpmcounter27, 0xbad
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WRITE_READ_CSR mhpmcounter28, 0xbad
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WRITE_READ_CSR mhpmcounter29, 0xbad
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WRITE_READ_CSR mhpmcounter30, 0xbad
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WRITE_READ_CSR mhpmcounter31, 0xbad
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# Machine Counter Setup
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WRITE_READ_CSR mcountinhibit, 0xbad
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WRITE_READ_CSR mhpmevent3, 0xbad
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WRITE_READ_CSR mhpmevent4, 0xbad
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WRITE_READ_CSR mhpmevent5, 0xbad
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WRITE_READ_CSR mhpmevent6, 0xbad
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WRITE_READ_CSR mhpmevent7, 0xbad
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WRITE_READ_CSR mhpmevent8, 0xbad
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WRITE_READ_CSR mhpmevent9, 0xbad
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WRITE_READ_CSR mhpmevent10, 0xbad
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WRITE_READ_CSR mhpmevent11, 0xbad
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WRITE_READ_CSR mhpmevent12, 0xbad
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WRITE_READ_CSR mhpmevent13, 0xbad
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WRITE_READ_CSR mhpmevent14, 0xbad
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WRITE_READ_CSR mhpmevent15, 0xbad
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WRITE_READ_CSR mhpmevent16, 0xbad
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WRITE_READ_CSR mhpmevent17, 0xbad
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WRITE_READ_CSR mhpmevent18, 0xbad
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WRITE_READ_CSR mhpmevent19, 0xbad
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WRITE_READ_CSR mhpmevent20, 0xbad
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WRITE_READ_CSR mhpmevent21, 0xbad
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WRITE_READ_CSR mhpmevent22, 0xbad
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WRITE_READ_CSR mhpmevent23, 0xbad
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WRITE_READ_CSR mhpmevent24, 0xbad
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WRITE_READ_CSR mhpmevent25, 0xbad
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WRITE_READ_CSR mhpmevent26, 0xbad
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WRITE_READ_CSR mhpmevent27, 0xbad
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WRITE_READ_CSR mhpmevent28, 0xbad
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WRITE_READ_CSR mhpmevent29, 0xbad
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WRITE_READ_CSR mhpmevent30, 0xbad
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WRITE_READ_CSR mhpmevent31, 0xbad
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END_TESTS
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TEST_STACK_AND_DATA
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@ -0,0 +1,39 @@
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///////////////////////////////////////////
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//
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// WALLY-MMU
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//
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// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
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//
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// Created 2022-01-25
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
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///////////////////////////////////////////
|
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#include "WALLY-TEST-LIB-32.h"
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INIT_TESTS
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s_file_begin:
|
||||
|
||||
// Test 5.2.3.1: testing Read-only access to Machine info CSRs
|
||||
CSR_R_ACCESS mvendorid
|
||||
CSR_R_ACCESS marchid
|
||||
CSR_R_ACCESS mimpid
|
||||
CSR_R_ACCESS mhartid
|
||||
# CSR_R_ACCESS mconfigptr # Unimplemented in spike as of 31 Jan 22
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
Loading…
Reference in New Issue
Block a user