Fixed bugs in ifu spills and missing reset on bus data register.

pipelined/src/ifu/spillsupport.sv

@@ -39,7 +39,7 @@ module spillsupport (
   input logic [`XLEN-1:0]  PCF,
   input logic [`XLEN-3:0]  PCPlusUpperF,
   input logic [`XLEN-1:0]  PCNextF,
-  logic [31:0]             InstrRawF,
+  input logic [31:0]       InstrRawF,
   input logic              IFUCacheBusStallF,
   output logic [`XLEN-1:0] PCNextFSpill,
   output logic [`XLEN-1:0] PCFSpill,

pipelined/src/lsu/busdp.sv

@@ -76,7 +76,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0)
   genvar                      index;
 
   for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
-    flopen #(`XLEN) fb(.clk, .en(LSUBusAck & LSUBusRead & (index == WordCount)),
+    flopenr #(`XLEN) fb(.clk, .reset, .en(LSUBusAck & LSUBusRead & (index == WordCount)),
                        .d(LSUBusHRDATA), .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
   end