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cvw
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d3e9703c19
cvw
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pipelined
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bbracker
d3e9703c19
change testbench-linux to by default use attempted instruction count for warning/error messages
2022-04-12 21:22:08 -07:00
..
config
Added missing ZFH macro to new configs
2022-04-06 07:13:51 +00:00
misc
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
regression
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-10 13:41:27 -05:00
src
Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.
2022-04-07 16:56:28 -05:00
srt
Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath
2022-02-28 20:50:51 +00:00
testbench
change testbench-linux to by default use attempted instruction count for warning/error messages
2022-04-12 21:22:08 -07:00
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