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../src/privileged/csrc.sv

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This commit is contained in:
David Harris 2022-05-31 21:12:17 +00:00
parent 8b493e16f5
commit 31815422d2
2 changed files with 6 additions and 7 deletions
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11
pipelined/src/privileged/privmode.sv
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@ -44,12 +44,11 @@ module privmode (
// PrivilegeMode FSM
always_comb begin
if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
if (`S_SUPPORTED & DelegateM)
NextPrivilegeModeM = `S_MODE;
else NextPrivilegeModeM = `M_MODE;
end else if (mretM) NextPrivilegeModeM = STATUS_MPP;
else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP};
else NextPrivilegeModeM = PrivilegeModeW;
if (`S_SUPPORTED & DelegateM) NextPrivilegeModeM = `S_MODE;
else NextPrivilegeModeM = `M_MODE;
end else if (mretM) NextPrivilegeModeM = STATUS_MPP;
else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP};
else NextPrivilegeModeM = PrivilegeModeW;
end
flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW);

2
pipelined/src/privileged/trap.sv
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@ -64,7 +64,7 @@ module trap (
assign IntPendingM = |PendingIntsM;
assign ValidIntsM = {12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW;
assign InterruptM = (|ValidIntsM) && InstrValidM && ~(CommittedM); // *** RT. CommittedM is a temporary hack to prevent integer division from having an interrupt during divide.
assign DelegateM = (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) &
assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) &
(PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE);
///////////////////////////////////////////