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Removing unused signals

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This commit is contained in:
David Harris 2022-05-12 14:36:15 +00:00
parent 15659b05e4
commit 8372bc86a7
10 changed files with 15 additions and 342 deletions
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2
addins/embench-iot

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Subproject commit 261a65e0a2d3e8d62d81b1d8fe7e309a096bc6a9
Subproject commit 2d2aaa7b85c60219c591555b647dfa1785ffe1b3

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addins/riscv-arch-test

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Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86
Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f

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addins/riscv-dv

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Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172
Subproject commit cb4295f9ce5da2881d7746015a6105adb8f09071

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addins/riscv-tests

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Subproject commit cf04274f50621fd9ef9147793cca6dd1657985c7
Subproject commit 3e2bf06b071a77ae62c09bf07c5229d1f9397d94

4
pipelined/regression/lint-wally
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@ -5,9 +5,9 @@ export PATH=$PATH:/usr/local/bin/
verilator=`which verilator`
basepath=$(dirname $0)/..
for config in rv32e rv64gc rv32gc rv32ic ; do
for config in rv64gc rv32e rv32gc rv32ic ; do
echo "$config linting..."
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then
if !($verilator --Wall --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then
echo "Exiting after $config lint due to errors or warnings"
exit 1
fi

1
pipelined/src/cache/sram1p1rw.sv vendored
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@ -43,7 +43,6 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
logic [WIDTH-1:0] StoredData[DEPTH-1:0];
logic [$clog2(DEPTH)-1:0] AdrD;
logic WriteEnableD;
always_ff @(posedge clk) AdrD <= Adr;

14
pipelined/src/fpu/fma.sv
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@ -41,7 +41,7 @@ module fma(
input logic [`NE-1:0] XExpE, YExpE, ZExpE, // input exponents - execute stage
input logic [`NF:0] XManE, YManE, ZManE, // input mantissa - execute stage
input logic XSgnM, YSgnM, // input signs - memory stage
input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents - memory stage
input logic [`NE-1:0] ZExpM, // input exponents - memory stage
input logic [`NF:0] XManM, YManM, ZManM, // input mantissa - memory stage
input logic XDenormE, YDenormE, ZDenormE, // is denorm
input logic XZeroE, YZeroE, ZZeroE, // is zero - execute stage
@ -85,7 +85,7 @@ module fma(
{AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE, FOpCtrlE[2]&~FOpCtrlE[1]&~FOpCtrlE[0]},
{AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM, Mult});
fma2 fma2(.XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM,
fma2 fma2(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM,
.FrmM, .FmtM, .ProdExpM, .AddendStickyM, .KillProdM, .SumM, .NegSumM, .InvZM, .NormCntM, .ZSgnEffM, .PSgnM,
.XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .XSNaNM, .YSNaNM, .ZSNaNM, .Mult,
.FMAResM, .FMAFlgM);
@ -283,6 +283,7 @@ module align(
// - Denormal numbers have a diffrent exponent value depending on the precision
assign ZExpVal = ZDenormE ? Denorm : ZExpE;
// assign AlignCnt = ProdExpE - {2'b0, ZExpVal} + (`NF+3);
// *** can we use ProdExpE instead of XExp/YExp to save an adder? DH 5/12/22
assign AlignCnt = XZeroE|YZeroE ? -1 : {2'b0, XExpVal} + {2'b0, YExpVal} - {2'b0, (`NE)'(`BIAS)} + `NF+3 - {2'b0, ZExpVal};
// Defualt Addition without shifting
@ -433,7 +434,7 @@ endmodule
module fma2(
input logic XSgnM, YSgnM, // input signs
input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents
input logic [`NE-1:0] ZExpM, // input exponents
input logic [`NF:0] XManM, YManM, ZManM, // input mantissas
input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single
@ -481,7 +482,7 @@ module fma2(
// Normalization
///////////////////////////////////////////////////////////////////////////////
normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum, .NegSumM,
normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum,
.SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm);
@ -529,7 +530,7 @@ module fma2(
// Select the result
///////////////////////////////////////////////////////////////////////////////
resultselect resultselect(.XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM,
resultselect resultselect(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM,
.FrmM, .FmtM, .AddendStickyM, .KillProdM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .RoundAdd,
.ZSgnEffM, .PSgnM, .ResultSgn, .CalcPlus1, .Invalid, .Overflow, .Underflow,
.ResultDenorm, .ResultExp, .ResultFrac, .FMAResM);
@ -577,7 +578,6 @@ module normalize(
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single
input logic KillProdM, // is the product set to zero
input logic AddendStickyM, // the sticky bit caclulated from the aligned addend
input logic NegSumM, // was the sum negitive
output logic [`NF+2:0] NormSum, // normalized sum
output logic SumZero, // is the sum zero
output logic NormSumSticky, UfSticky, // sticky bits
@ -1095,7 +1095,7 @@ endmodule
module resultselect(
input logic XSgnM, YSgnM, // input signs
input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents
input logic [`NE-1:0] ZExpM, // input exponents
input logic [`NF:0] XManM, YManM, ZManM, // input mantissas
input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single

4
pipelined/src/fpu/fpu.sv
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@ -87,7 +87,7 @@ module fpu (
logic XSgnE, YSgnE, ZSgnE; // input's sign - execute stage
logic XSgnM, YSgnM; // input's sign - memory stage
logic [10:0] XExpE, YExpE, ZExpE; // input's exponent - execute stage
logic [10:0] XExpM, YExpM, ZExpM; // input's exponent - memory stage
logic [10:0] ZExpM; // input's exponent - memory stage
logic [52:0] XManE, YManE, ZManE; // input's fraction - execute stage
logic [52:0] XManM, YManM, ZManM; // input's fraction - memory stage
logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
@ -189,7 +189,7 @@ module fpu (
fma fma (.clk, .reset, .FlushM, .StallM,
.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
.XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE,
.XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM,
.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM,
.XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM,
.XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM,
.FOpCtrlE,

2
pipelined/src/mmu/tlbcontrol.sv
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@ -58,8 +58,6 @@ module tlbcontrol #(parameter ITLB = 0) (
);
// Sections of the page table entry
logic [11:0] PageOffset;
logic [`SVMODE_BITS-1:0] SVMode;
logic [1:0] EffectivePrivilegeMode;
logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits

324
pipelined/src/ppa/ppa.sv
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@ -1,324 +0,0 @@
// ppa.sv
// Teo Ene & David_Harris@hmc.edu 11 May 2022
// & mmasserfrye@hmc.edu
// Measure PPA of various building blocks
module ppa_comparator_16 #(parameter WIDTH=16) (
input logic [WIDTH-1:0] a, b,
input logic sgnd,
output logic [1:0] flags);
ppa_comparator #(WIDTH) comp (.*);
endmodule
module ppa_comparator_32 #(parameter WIDTH=32) (
input logic [WIDTH-1:0] a, b,
input logic sgnd,
output logic [1:0] flags);
ppa_comparator #(WIDTH) comp (.*);
endmodule
module ppa_comparator_64 #(parameter WIDTH=64) (
input logic [WIDTH-1:0] a, b,
input logic sgnd,
output logic [1:0] flags);
ppa_comparator #(WIDTH) comp (.*);
endmodule
module ppa_comparator #(parameter WIDTH=16) (
input logic [WIDTH-1:0] a, b,
input logic sgnd,
output logic [1:0] flags);
logic eq, lt, ltu;
logic [WIDTH-1:0] af, bf;
// For signed numbers, flip most significant bit
assign af = {a[WIDTH-1] ^ sgnd, a[WIDTH-2:0]};
assign bf = {b[WIDTH-1] ^ sgnd, b[WIDTH-2:0]};
// behavioral description gives best results
assign eq = (af == bf);
assign lt = (af < bf);
assign flags = {eq, lt};
endmodule
module ppa_add_16 #(parameter WIDTH=16) (
input logic [WIDTH-1:0] a, b,
output logic [WIDTH-1:0] y);
assign y = a + b;
endmodule
module ppa_add_32 #(parameter WIDTH=32) (
input logic [WIDTH-1:0] a, b,
output logic [WIDTH-1:0] y);
assign y = a + b;
endmodule
module ppa_add_64 #(parameter WIDTH=64) (
input logic [WIDTH-1:0] a, b,
output logic [WIDTH-1:0] y);
assign y = a + b;
endmodule
module ppa_mult_16 #(parameter WIDTH=16) (
input logic [WIDTH-1:0] a, b,
output logic [WIDTH*2-1:0] y); //is this right width
assign y = a * b;
endmodule
module ppa_mult_32 #(parameter WIDTH=32) (
input logic [WIDTH-1:0] a, b,
output logic [WIDTH*2-1:0] y); //is this right width
assign y = a * b;
endmodule
module ppa_mult_64 #(parameter WIDTH=64) (
input logic [WIDTH-1:0] a, b,
output logic [WIDTH*2-1:0] y); //is this right width
assign y = a * b;
endmodule
module ppa_alu #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, B,
input logic [2:0] ALUControl,
input logic [2:0] Funct3,
output logic [WIDTH-1:0] Result,
output logic [WIDTH-1:0] Sum);
logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
logic Carry, Neg;
logic LT, LTU;
logic W64, SubArith, ALUOp;
logic [2:0] ALUFunct;
logic Asign, Bsign;
// Extract control signals
// W64 indicates RV64 W-suffix instructions acting on lower 32-bit word
// SubArith indicates subtraction
// ALUOp = 0 for address generation addition or 1 for regular ALU
assign {W64, SubArith, ALUOp} = ALUControl;
// addition
assign CondInvB = SubArith ? ~B : B;
assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
// Shifts
shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
// condition code flags based on subtract output Sum = A-B
// Overflow occurs when the numbers being subtracted have the opposite sign
// and the result has the opposite sign of A
assign Neg = Sum[WIDTH-1];
assign Asign = A[WIDTH-1];
assign Bsign = B[WIDTH-1];
assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; // simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow
assign LTU = ~Carry;
// SLT
assign SLT = {{(WIDTH-1){1'b0}}, LT};
assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
// Select appropriate ALU Result
assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
always_comb
casez (ALUFunct)
3'b000: FullResult = Sum; // add or sub
3'b?01: FullResult = Shift; // sll, sra, or srl
3'b010: FullResult = SLT; // slt
3'b011: FullResult = SLTU; // sltu
3'b100: FullResult = A ^ B; // xor
3'b110: FullResult = A | B; // or
3'b111: FullResult = A & B; // and
endcase
// support W-type RV64I ADDW/SUBW/ADDIW/Shifts that sign-extend 32-bit result to 64 bits
if (WIDTH==64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
else assign Result = FullResult;
endmodule
module ppa_shiftleft #(parameter WIDTH=32) (
input logic [WIDTH-1:0] a,
input logic [$clog2(WIDTH)-1:0] amt,
output logic [WIDTH-1:0] y);
assign y = a << amt;
endmodule
module ppa_shifter (
input logic [`XLEN-1:0] A,
input logic [`LOG_XLEN-1:0] Amt,
input logic Right, Arith, W64,
output logic [`XLEN-1:0] Y);
logic [2*`XLEN-2:0] z, zshift;
logic [`LOG_XLEN-1:0] amttrunc, offset;
// Handle left and right shifts with a funnel shifter.
// For RV32, only 32-bit shifts are needed.
// For RV64, 32 and 64-bit shifts are needed, with sign extension.
// funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
if (`XLEN==32) begin:shifter // RV32
always_comb // funnel mux
if (Right)
if (Arith) z = {{31{A[31]}}, A};
else z = {31'b0, A};
else z = {A, 31'b0};
assign amttrunc = Amt; // shift amount
end else begin:shifter // RV64
always_comb // funnel mux
if (W64) begin // 32-bit shifts
if (Right)
if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]};
else z = {95'b0, A[31:0]};
else z = {32'b0, A[31:0], 63'b0};
end else begin
if (Right)
if (Arith) z = {{63{A[63]}}, A};
else z = {63'b0, A};
else z = {A, 63'b0};
end
assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift
end
// opposite offset for right shfits
assign offset = Right ? amttrunc : ~amttrunc;
// funnel operation
assign zshift = z >> offset;
assign Y = zshift[`XLEN-1:0];
endmodule
module ppa_prioritythermometer #(parameter N = 8) (
input logic [N-1:0] a,
output logic [N-1:0] y);
// Carefully crafted so design compiler will synthesize into a fast tree structure
// Rather than linear.
// create thermometer code mask
genvar i;
assign y[0] = ~a[0];
for (i=1; i<N; i++) begin:therm
assign y[i] = y[i-1] & ~a[i];
end
endmodule
module ppa_priorityonehot #(parameter N = 8) (
input logic [N-1:0] a,
output logic [N-1:0] y);
logic [N-1:0] nolower;
// create thermometer code mask
ppa_prioritythermometer #(N) maskgen(.a({a[N-2:0], 1'b0}), .y(nolower));
assign y = a & nolower;
endmodule
module ppa_prioriyencoder #(parameter N = 8) (
input logic [N-1:0] a,
output logic [$clog2(N)-1:0] y);
// Carefully crafted so design compiler will synthesize into a fast tree structure
// Rather than linear.
// create thermometer code mask
genvar i;
for (i=0; i<N; i++) begin:pri
if (a[i]) y= i;
end
endmodule
module decoder (
input logic [$clog2(N)-1:0] a,
output logic [N-1:0] y);
always_comb begin
y = 0;
y[a] = 1;
end
endmodule
module mux2 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule
module mux3 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, d2,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? d2 : (s[0] ? d1 : d0);
endmodule
module mux4 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, d2, d3,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
endmodule
module mux6 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5,
input logic [2:0] s,
output logic [WIDTH-1:0] y);
assign y = s[2] ? (s[0] ? d5 : d4) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
endmodule
module mux8 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
input logic [2:0] s,
output logic [WIDTH-1:0] y);
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
endmodule
// *** some way to express data-critical inputs
module flop #(parameter WIDTH = 8) (
input logic clk,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
q <= #1 d;
endmodule
module flopr #(parameter WIDTH = 8) (
input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (reset) q <= #1 0;
else q <= #1 d;
endmodule
module floprasynnc #(parameter WIDTH = 8) (
input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk or posedge reset)
if (reset) q <= #1 0;
else q <= #1 d;
endmodule
module flopenr #(parameter WIDTH = 8) (
input logic clk, reset, en,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (reset) q <= #1 0;
else if (en) q <= #1 d;
endmodule