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Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt

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This commit is contained in:
David Harris 2022-05-11 15:08:33 +00:00
parent 91472eb948
commit a8c9f504fa
8 changed files with 18 additions and 18 deletions
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4
pipelined/src/privileged/csr.sv
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@ -42,7 +42,7 @@ module csr #(parameter
input logic [31:0] InstrM,
input logic [`XLEN-1:0] PCM, SrcAM,
input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, wfiM, InterruptM,
input logic TimerInt, MExtInt, SExtInt, SwInt,
input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT,
input logic InstrValidM, FRegWriteM, LoadStallD,
input logic BPPredDirWrongM,
@ -134,7 +134,7 @@ module csr #(parameter
csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW,
.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
.MExtInt, .SExtInt, .TimerInt, .SwInt,
.MExtInt, .SExtInt, .MTimerInt, .MSwInt,
.MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, .IP_REGW_writeable);
csrsr csrsr(.clk, .reset, .StallW,
.WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM,

4
pipelined/src/privileged/csri.sv
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@ -42,7 +42,7 @@ module csri #(parameter
input logic CSRMWriteM, CSRSWriteM,
input logic [`XLEN-1:0] CSRWriteValM,
input logic [11:0] CSRAdrM,
(* mark_debug = "true" *) input logic MExtInt, SExtInt, TimerInt, SwInt,
(* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt,
input logic [11:0] MIDELEG_REGW,
output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
(* mark_debug = "true" *) output logic [11:0] IP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
@ -80,7 +80,7 @@ module csri #(parameter
else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields
else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields
assign IP_REGW = {MExtInt,1'b0,SExtInt|IP_REGW_writeable[9],1'b0,TimerInt,1'b0,IP_REGW_writeable[5],1'b0,SwInt,1'b0,IP_REGW_writeable[1],1'b0};
assign IP_REGW = {MExtInt,1'b0,SExtInt|IP_REGW_writeable[9],1'b0,MTimerInt,1'b0,IP_REGW_writeable[5],1'b0,MSwInt,1'b0,IP_REGW_writeable[1],1'b0};
assign MIP_REGW = IP_REGW;
assign MIE_REGW = IE_REGW;

4
pipelined/src/privileged/privileged.sv
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@ -55,7 +55,7 @@ module privileged (
input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD,
input logic LoadMisalignedFaultM,
input logic StoreAmoMisalignedFaultM,
input logic TimerInt, MExtInt, SExtInt, SwInt,
input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT,
input logic [`XLEN-1:0] IEUAdrM,
input logic [4:0] SetFflagsM,
@ -161,7 +161,7 @@ module privileged (
.StallE, .StallM, .StallW,
.InstrM, .PCM, .SrcAM,
.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .wfiM, .InterruptM,
.TimerInt, .MExtInt, .SExtInt, .SwInt,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
.MTIME_CLINT,
.InstrValidM, .FRegWriteM, .LoadStallD,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,

6
pipelined/src/uncore/clint.sv
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@ -43,7 +43,7 @@ module clint (
output logic [`XLEN-1:0] HREADCLINT,
output logic HRESPCLINT, HREADYCLINT,
(* mark_debug = "true" *) output logic [63:0] MTIME,
output logic TimerInt, SwInt);
output logic MTimerInt, MSwInt);
logic MSIP;
@ -159,9 +159,9 @@ module clint (
end
// Software interrupt when MSIP is set
assign SwInt = MSIP;
assign MSwInt = MSIP;
// Timer interrupt when MTIME >= MTIMECMP
assign TimerInt = ({1'b0, MTIME} >= {1'b0, MTIMECMP}); // unsigned comparison
assign MTimerInt = ({1'b0, MTIME} >= {1'b0, MTIMECMP}); // unsigned comparison
endmodule

6
pipelined/src/uncore/uncore.sv
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@ -55,7 +55,7 @@ module uncore (
input logic [3:0] HSIZED,
input logic HWRITED,
// peripheral pins
output logic TimerInt, SwInt, MExtInt, SExtInt,
output logic MTimerInt, MSwInt, MExtInt, SExtInt,
input logic [31:0] GPIOPinsIn,
output logic [31:0] GPIOPinsOut, GPIOPinsEn,
input logic UARTSin,
@ -120,11 +120,11 @@ module uncore (
.HREADCLINT,
.HRESPCLINT, .HREADYCLINT,
.MTIME(MTIME_CLINT),
.TimerInt, .SwInt);
.MTimerInt, .MSwInt);
end else begin : clint
assign MTIME_CLINT = 0;
assign TimerInt = 0; assign SwInt = 0;
assign MTimerInt = 0; assign MSwInt = 0;
end
if (`PLIC_SUPPORTED == 1) begin : plic
plic plic(

4
pipelined/src/wally/wallypipelinedcore.sv
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@ -34,7 +34,7 @@
module wallypipelinedcore (
input logic clk, reset,
// Privileged
input logic TimerInt, MExtInt, SExtInt, SwInt,
input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT,
// Bus Interface
input logic [`AHBW-1:0] HRDATA,
@ -331,7 +331,7 @@ module wallypipelinedcore (
.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
.TimerInt, .MExtInt, .SExtInt, .SwInt,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
.MTIME_CLINT,
.IEUAdrM,
.SetFflagsM,

6
pipelined/src/wally/wallypipelinedsoc.sv
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@ -72,7 +72,7 @@ module wallypipelinedsoc (
// logic reset;
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
logic HRESP;
logic TimerInt, SwInt; // from CLINT
logic MTimerInt, MSwInt; // from CLINT
logic [63:0] MTIME_CLINT; // from CLINT to CSRs
logic MExtInt,SExtInt; // from PLIC
logic [2:0] HADDRD;
@ -84,7 +84,7 @@ module wallypipelinedsoc (
// instantiate processor and memories
wallypipelinedcore core(.clk, .reset,
.TimerInt, .MExtInt, .SExtInt, .SwInt,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
.MTIME_CLINT,
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
@ -94,7 +94,7 @@ module wallypipelinedsoc (
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
.HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,
.TimerInt, .SwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT,
.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT,
.HSELEXT,
.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK

2
pipelined/testbench/testbench-linux.sv
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@ -142,7 +142,7 @@ module testbench;
`define CSR_BASE `PRIV_BASE.csr
`define MEIP `PRIV_BASE.MExtInt
`define SEIP `PRIV_BASE.SExtInt
`define MTIP `PRIV_BASE.TimerInt
`define MTIP `PRIV_BASE.MTimerInt
`define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW
`define MEDELEG `CSR_BASE.csrm.deleg.MEDELEGreg.q
`define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q