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https://github.com/openhwgroup/cvw
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F Selection
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@ -93,11 +93,7 @@ module srt (
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otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot);
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<<<<<<< Updated upstream
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expcalc expcalc(.XExp, .YExp, .calcExp);
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=======
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expcalc expcalc(.XExp, .YExp, .calcExp, .Sqrt);
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>>>>>>> Stashed changes
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signcalc signcalc(.XSign, .YSign, .calcSign);
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endmodule
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@ -187,6 +183,26 @@ module qsel2 ( // *** eventually just change to 4 bits
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assign #1 qm = magnitude & sign;
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endmodule
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////////////////////////////////////
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// Adder Input Selection, Radix 2 //
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////////////////////////////////////
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module fsel2 (
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input logic sp, sn,
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input logic [`DIVLEN+3:0] C, S, SM,
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output logic [`DIVLEN+3:0] F
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);
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logic [`DIVLEN+3:0] FP, FN;
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// Generate for both positive and negative bits
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assign FP = ~S & C;
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assign FN = SM | (C & (~C << 2));
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// Choose which adder input will be used
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assign F = sp ? FP : (sn ? FN : (`DIVLEN+4){1'b0});
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endmodule
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///////////////////////////////////
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// On-The-Fly Converter, Radix 2 //
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///////////////////////////////////
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@ -234,6 +250,17 @@ module otfc2 #(parameter N=64) (
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endmodule
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///////////////////////////////
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// Square Root OTFC, Radix 2 //
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///////////////////////////////
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module softc2(
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input logic clk,
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input logic Start,
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input logic sp, sn,
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output logic S,
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);
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endmodule
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/////////////
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// counter //
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/////////////
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@ -301,13 +328,6 @@ endmodule
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// expcalc //
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//////////////
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module expcalc(
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<<<<<<< Updated upstream
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input logic [`NE-1:0] XExp, YExp,
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output logic [`NE-1:0] calcExp
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);
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assign calcExp = XExp - YExp + (`NE)'(`BIAS);
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=======
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input logic [`NE-1:0] XExp, YExp,
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input logic Sqrt,
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output logic [`NE-1:0] calcExp
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@ -317,7 +337,6 @@ module expcalc(
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assign SExp = {1'b0, SXExp[`NE-1:1]} + (`NE)'(`BIAS);
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assign DExp = XExp - YExp + (`NE)'(`BIAS);
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assign calcExp = Sqrt ? SExp : DExp;
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>>>>>>> Stashed changes
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endmodule
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@ -62,11 +62,6 @@ module testbench;
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// `define mema 255:192
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// FLOAT TEST SIZES
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<<<<<<< Updated upstream
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`define memr 63:0
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`define memb 127:64
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`define mema 191:128
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=======
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// `define memr 63:0
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// `define memb 127:64
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// `define mema 191:128
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@ -75,7 +70,6 @@ module testbench;
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`define memr 63:0
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`define mema 127:64
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`define memb 191:128
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>>>>>>> Stashed changes
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// Test logicisters
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logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
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@ -86,13 +80,9 @@ module testbench;
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logic rsign;
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integer testnum, errors;
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<<<<<<< Updated upstream
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assign Int = 1'b0;
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=======
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// Equip Int test or Sqrt test
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assign Int = 1'b0;
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assign Sqrt = 1'b1;
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>>>>>>> Stashed changes
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// Divider
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srt srt(.clk, .Start(req),
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@ -101,11 +91,7 @@ module testbench;
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.XSign(asign), .YSign(bsign), .rsign,
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.SrcXFrac(afrac), .SrcYFrac(bfrac),
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.SrcA(a), .SrcB(b), .Fmt(2'b00),
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<<<<<<< Updated upstream
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.W64(1'b1), .Signed(1'b0), .Int, .Sqrt(1'b0),
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=======
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.W64(1'b1), .Signed(1'b0), .Int, .Sqrt,
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>>>>>>> Stashed changes
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.Quot, .Rem(), .Flags(), .done);
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// Counter
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@ -125,11 +111,7 @@ module testbench;
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begin
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testnum = 0;
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errors = 0;
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<<<<<<< Updated upstream
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$readmemh ("testvectors", Tests);
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=======
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$readmemh ("sqrttestvectors", Tests);
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>>>>>>> Stashed changes
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Vec = Tests[testnum];
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a = Vec[`mema];
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{asign, aExp, afrac} = a;
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@ -183,17 +165,10 @@ module testbench;
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req <= #5 1;
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diffp = correctr[51:0] - r;
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diffn = r - correctr[51:0];
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<<<<<<< Updated upstream
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if (($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
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begin
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errors = errors + 1;
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$display("result was %h, should be %h %h %h\n", rSqrt, correctr, diffn, diffp);
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=======
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if (rExp !== correctr[62:52]) // check if accurate to 1 ulp
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begin
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errors = errors + 1;
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$display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp);
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>>>>>>> Stashed changes
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$display("failed\n");
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$stop;
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end
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