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Byte write enables are passing all configs now.

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This commit is contained in:
Ross Thompson 2022-03-10 17:26:32 -06:00
parent f7df3a0666
commit 50789f9ddd
7 changed files with 84 additions and 39 deletions
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10
pipelined/src/generic/flop/simpleram.sv
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@ -34,6 +34,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
input logic clk,
input logic [31:0] a,
input logic we,
input logic [`XLEN/8-1:0] FinalByteWENM,
input logic [`XLEN-1:0] wd,
output logic [`XLEN-1:0] rd
);
@ -45,9 +46,14 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
logic [31:adrlsb] adrmsbs;
assign adrmsbs = a[31:adrlsb];
always_ff @(posedge clk) begin
always_ff @(posedge clk)
rd <= RAM[adrmsbs];
if (we) RAM[adrmsbs] <= #1 wd;
genvar index;
for(index = 0; index < `XLEN/8; index++) begin
always_ff @(posedge clk) begin
if (we & FinalByteWENM[index]) RAM[adrmsbs][8*(index+1)-1:8*index] <= #1 wd[8*(index+1)-1:8*index];
end
end
endmodule

2
pipelined/src/ifu/ifu.sv
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@ -175,7 +175,7 @@ module ifu (
if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM
dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill),
.TrapM(1'b0), .FinalWriteDataM(),
.TrapM(1'b0), .FinalWriteDataM(), .FinalByteWENM('0),
.ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
.BusCommittedM(), .ReadDataWordMuxM(), .DCacheStallM(ICacheStallF),
.DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));

3
pipelined/src/lsu/dtim.sv
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@ -37,6 +37,7 @@ module dtim(
input logic [`XLEN-1:0] IEUAdrE,
input logic TrapM,
input logic [`XLEN-1:0] FinalWriteDataM,
input logic [`XLEN/8-1:0] FinalByteWENM,
output logic [`XLEN-1:0] ReadDataWordM,
output logic BusStall,
output logic LSUBusWrite,
@ -49,7 +50,7 @@ module dtim(
output logic DCacheAccess);
simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.clk,
.clk, .FinalByteWENM,
.a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently ***
.we(LSURWM[0] & ~TrapM), // have to ignore write if Trap.
.wd(FinalWriteDataM), .rd(ReadDataWordM));

10
pipelined/src/lsu/lsu.sv
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@ -194,7 +194,7 @@ module lsu (
// Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops
dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM,
.ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
.ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM,
.ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .FinalByteWENM,
.DCacheMiss, .DCacheAccess);
assign SelUncachedAdr = '0; // value does not matter.
end else begin : bus
@ -253,11 +253,9 @@ module lsu (
end
end
if(1) begin
subwordwrite subwordwrite(.HRDATA('0), .HADDRD(LSUPAdrM[2:0]),
.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}),
.HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteWEN(FinalByteWENM));
end
subwordwrite subwordwrite(.HADDRD(LSUPAdrM[2:0]),
.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}),
.HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteWEN(FinalByteWENM));
subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
.Funct3M(LSUFunct3M), .ReadDataM);

27
pipelined/src/uncore/ram.sv
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@ -106,32 +106,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
end // initial begin
end // if (FPGA)
if(`XLEN == 64) begin
always_comb begin
case(HSIZED[1:0])
2'b00: begin ByteMaskM = 8'b00000000; ByteMaskM[A[2:0]] = 1; end // sb
2'b01: case (A[2:1])
2'b00: ByteMaskM = 8'b0000_0011;
2'b01: ByteMaskM = 8'b0000_1100;
2'b10: ByteMaskM = 8'b0011_0000;
2'b11: ByteMaskM = 8'b1100_0000;
endcase
2'b10: if (A[2]) ByteMaskM = 8'b11110000;
else ByteMaskM = 8'b00001111;
2'b11: ByteMaskM = 8'b1111_1111;
endcase
end
end else begin
always_comb begin
case(HSIZED[1:0])
2'b00: begin ByteMaskM = 4'b0000; ByteMaskM[A[1:0]] = 1; end // sb
2'b01: if (A[1]) ByteMaskM = 4'b1100;
else ByteMaskM = 4'b0011;
2'b10: ByteMaskM = 4'b1111;
default: ByteMaskM = 4'b1111;
endcase
end
end
swbytemask swbytemask(.HSIZED, .HADDRD(A), .ByteMask(ByteMaskM));
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);

5
pipelined/src/uncore/subwordwrite.sv
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@ -31,7 +31,6 @@
`include "wally-config.vh"
module subwordwrite (
input logic [`XLEN-1:0] HRDATA,
input logic [2:0] HADDRD,
input logic [3:0] HSIZED,
input logic [`XLEN-1:0] HWDATAIN,
@ -70,7 +69,7 @@ module subwordwrite (
endcase
always_comb begin
HWDATA=HRDATA;
HWDATA='0;
if (ByteMaskM[0]) HWDATA[7:0] = WriteDataSubwordDuplicated[7:0];
if (ByteMaskM[1]) HWDATA[15:8] = WriteDataSubwordDuplicated[15:8];
if (ByteMaskM[2]) HWDATA[23:16] = WriteDataSubwordDuplicated[23:16];
@ -104,7 +103,7 @@ module subwordwrite (
endcase
always_comb begin
HWDATA=HRDATA;
HWDATA='0;
if (ByteMaskM[0]) HWDATA[7:0] = WriteDataSubwordDuplicated[7:0];
if (ByteMaskM[1]) HWDATA[15:8] = WriteDataSubwordDuplicated[15:8];
if (ByteMaskM[2]) HWDATA[23:16] = WriteDataSubwordDuplicated[23:16];

66
pipelined/src/uncore/swwbytemask.sv Normal file
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@ -0,0 +1,66 @@
///////////////////////////////////////////
// ram.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: On-chip RAM, external to core
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// MIT LICENSE
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify, merge,
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
// to whom the Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or
// substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
// OR OTHER DEALINGS IN THE SOFTWARE.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module swbytemask (
input logic [3:0] HSIZED,
input logic [31:0] HADDRD,
output logic [`XLEN/8-1:0] ByteMask);
if(`XLEN == 64) begin
always_comb begin
case(HSIZED[1:0])
2'b00: begin ByteMask = 8'b00000000; ByteMask[HADDRD[2:0]] = 1; end // sb
2'b01: case (HADDRD[2:1])
2'b00: ByteMask = 8'b0000_0011;
2'b01: ByteMask = 8'b0000_1100;
2'b10: ByteMask = 8'b0011_0000;
2'b11: ByteMask = 8'b1100_0000;
endcase
2'b10: if (HADDRD[2]) ByteMask = 8'b11110000;
else ByteMask = 8'b00001111;
2'b11: ByteMask = 8'b1111_1111;
endcase
end
end else begin
always_comb begin
case(HSIZED[1:0])
2'b00: begin ByteMask = 4'b0000; ByteMask[HADDRD[1:0]] = 1; end // sb
2'b01: if (HADDRD[1]) ByteMask = 4'b1100;
else ByteMask = 4'b0011;
2'b10: ByteMask = 4'b1111;
default: ByteMask = 4'b1111;
endcase
end
end
endmodule