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https://github.com/openhwgroup/cvw
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radix-4 early termination working for special cases - not working completely
This commit is contained in:
Katherine Parry
parent
adaee899bb
commit
a5fb60eb1a
@ -22,7 +22,7 @@ add wave -group {Divide} -noupdate /testbenchfp/srtradix4/*
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add wave -group {Divide} -noupdate /testbenchfp/srtradix4/qsel4/*
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add wave -group {Divide} -noupdate /testbenchfp/srtradix4/otfc4/*
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add wave -group {Divide} -noupdate /testbenchfp/srtradix4/preproc/*
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add wave -group {Divide} -noupdate /testbenchfp/srtradix4/divcounter/*
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add wave -group {Divide} -noupdate /testbenchfp/srtradix4/earlytermination/*
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add wave -group {Divide} -noupdate /testbenchfp/srtradix4/expcalc/*
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add wave -group {Testbench} -noupdate /testbenchfp/*
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add wave -group {Testbench} -noupdate /testbenchfp/readvectors/*
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@ -3,6 +3,8 @@
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module divshiftcalc(
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input logic [`DIVLEN+2:0] Quot,
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input logic [`NE+1:0] DivCalcExpM,
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input logic [`FMTBITS-1:0] FmtM,
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input logic [$clog2(`DIVLEN/2+3)-1:0] EarlyTermShiftDiv2M,
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output logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt,
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output logic [`NORMSHIFTSZ-1:0] DivShiftIn,
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output logic [`NE+1:0] CorrDivExp
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@ -10,30 +12,81 @@ module divshiftcalc(
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logic ResDenorm;
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logic [`NE+1:0] DenormShift;
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logic [`NE+1:0] NormShift;
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logic [`NE+1:0] Nf, NfPlus1;
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// is the result denromalized
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// if the exponent is 1 then the result needs to be normalized then the result is denormalizes
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assign ResDenorm = DivCalcExpM[`NE+1]|(~|DivCalcExpM[`NE+1:1]&~(DivCalcExpM[0]&Quot[`DIVLEN+2]));
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// select the proper fraction lengnth
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if (`FPSIZES == 1) begin
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assign Nf = (`NE+2)'(`NF);
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assign NfPlus1 = (`NE+2)'(`NF+1);
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end else if (`FPSIZES == 2) begin
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assign Nf = FmtM ? (`NE+2)'(`NF) : (`NE+2)'(`NF1);
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assign NfPlus1 = FmtM ? (`NE+2)'(`NF+1) : (`NE+2)'(`NF1+1);
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end else if (`FPSIZES == 3) begin
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always_comb
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case (FmtM)
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`FMT: begin
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Nf = (`NE+2)'(`NF);
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NfPlus1 = (`NE+2)'(`NF+1);
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end
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`FMT1: begin
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Nf = (`NE+2)'(`NF1);
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NfPlus1 = (`NE+2)'(`NF1+1);
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end
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`FMT2: begin
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Nf = (`NE+2)'(`NF2);
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NfPlus1 = (`NE+2)'(`NF2+1);
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end
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default: begin
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Nf = 1'bx;
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NfPlus1 = 1'bx;
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end
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endcase
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end else if (`FPSIZES == 4) begin
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always_comb
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case (FmtM)
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2'h3: begin
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Nf = (`NE+2)'(`Q_NF);
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NfPlus1 = (`NE+2)'(`Q_NF+1);
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end
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2'h1: begin
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Nf = (`NE+2)'(`D_NF);
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NfPlus1 = (`NE+2)'(`D_NF+1);
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end
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2'h0: begin
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Nf = (`NE+2)'(`S_NF);
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NfPlus1 = (`NE+2)'(`S_NF+1);
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end
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2'h2: begin
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Nf = (`NE+2)'(`H_NF);
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NfPlus1 = (`NE+2)'(`H_NF+1);
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end
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endcase
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end
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// if the result is denormalized
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// 00000000x.xxxxxx... Exp = DivCalcExp
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// .00000000xxxxxxx... >> NF+1 Exp = DivCalcExp+NF+1
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// .000xxxxxxxxxxxx... << DivCalcExp+NF+1 Exp = 0
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// .0000xxxxxxxxxxx... >> 1 Exp = 1
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// Left shift amount = DivCalcExp+NF+1-1
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assign DenormShift = (`NE+2)'(`NF)+DivCalcExpM;
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// if the result is denormalized
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assign DenormShift = Nf+DivCalcExpM;
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// if the result is normalized
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// 00000000x.xxxxxx... Exp = DivCalcExp
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// .00000000xxxxxxx... >> NF+1 Exp = DivCalcExp+NF+1
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// 00000000x.xxxxxx... << NF+1 Exp = DivCalcExp
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// 00000000xx.xxxxx... << 1? Exp = DivCalcExp-1
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// Left shift amount = NF+1 plus 1 if normalization required
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assign NormShift = (`NE+2)'(`NF+1) + {(`NE+1)'(0), ~Quot[`DIVLEN+2]};
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assign NormShift = NfPlus1 + {(`NE+1)'(0), ~Quot[`DIVLEN+2]};
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// if the shift amount is negitive then dont shift (keep sticky bit)
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assign DivShiftAmt = ResDenorm ? DenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0];
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assign DivShiftAmt = (ResDenorm ? DenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0])+{{$clog2(`NORMSHIFTSZ)-$clog2(`DIVLEN/2+3)-1{1'b0}}, EarlyTermShiftDiv2M, 1'b0};
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// *** may be able to reduce shifter size
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assign DivShiftIn = {{`NF{1'b0}}, Quot[`DIVLEN+2:0], {`NORMSHIFTSZ-`DIVLEN-3-`NF{1'b0}}};
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// the quotent is in the range [.5,2)
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// the quotent is in the range [.5,2) if there is no early termination
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// if the quotent < 1 and not denormal then subtract 1 to account for the normalization shift
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assign CorrDivExp = (ResDenorm&~DenormShift[`NE+1]) ? (`NE+2)'(0) : DivCalcExpM - {(`NE+1)'(0), ~Quot[`DIVLEN+2]};
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@ -127,6 +127,7 @@ module fpu (
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logic [`NE+1:0] DivCalcExpM;
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logic DivNegStickyM;
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logic DivStickyM;
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logic [$clog2(`DIVLEN/2+3)-1:0] EarlyTermShiftDiv2M;
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// result and flag signals
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logic [63:0] FDivResM, FDivResW; // divide/squareroot result
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@ -357,7 +358,7 @@ module fpu (
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assign FpLoadM = FResSelM[1];
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postprocess postprocess(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .FrmM, .FmtM, .ProdExpM,
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postprocess postprocess(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .FrmM, .FmtM, .ProdExpM, .EarlyTermShiftDiv2M,
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.AddendStickyM, .KillProdM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .Quot,
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.ZInfM, .XNaNM, .YNaNM, .ZNaNM, .XSNaNM, .YSNaNM, .ZSNaNM, .SumM, .DivCalcExpM,
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.NegSumM, .InvZM, .ZDenormM, .ZSgnEffM, .PSgnM, .FOpCtrlM, .FmaNormCntM, .DivNegStickyM,
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@ -49,6 +49,7 @@ module postprocess(
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input logic ZSgnEffM, // the modified Z sign - depends on instruction
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input logic PSgnM, // the product's sign
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input logic [2:0] FOpCtrlM, // choose which opperation (look below for values)
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input logic [$clog2(`DIVLEN/2+3)-1:0] EarlyTermShiftDiv2M,
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input logic [$clog2(3*`NF+7)-1:0] FmaNormCntM, // the normalization shift count
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input logic [`NE:0] CvtCalcExpM, // the calculated expoent
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input logic [`NE+1:0] DivCalcExpM, // the calculated expoent
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@ -143,7 +144,7 @@ module postprocess(
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.XZeroM, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
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fmashiftcalc fmashiftcalc(.SumM, .ZExpM, .ProdExpM, .FmaNormCntM, .FmtM, .KillProdM, .ConvNormSumExp,
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.ZDenormM, .SumZero, .PreResultDenorm, .FmaShiftAmt, .FmaShiftIn);
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divshiftcalc divshiftcalc(.Quot, .DivCalcExpM, .CorrDivExp, .DivShiftAmt, .DivShiftIn);
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divshiftcalc divshiftcalc(.FmtM, .Quot, .DivCalcExpM, .EarlyTermShiftDiv2M, .CorrDivExp, .DivShiftAmt, .DivShiftIn);
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always_comb
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case(PostProcSelM)
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@ -211,7 +211,7 @@ module resultselect(
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// - do so if the res underflows, is zero (the exp doesnt calculate correctly). or the integer input is 0
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// - dont set to zero if fp input is zero but not using the fp input
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// - dont set to zero if int input is zero but not using the int input
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assign KillRes = CvtOp ? (CvtResUf|(XZeroM&~IntToFp)|(IntZeroM&IntToFp)) : FullResExp[`NE+1] | (YInfM&DivOp&~XInfM);//Underflow & ~ResDenorm & (ResExp!=1);
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assign KillRes = CvtOp ? (CvtResUf|(XZeroM&~IntToFp)|(IntZeroM&IntToFp)) : FullResExp[`NE+1] | (((YInfM&~XInfM)|XZeroM)&DivOp);//Underflow & ~ResDenorm & (ResExp!=1);
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assign SelOfRes = Overflow|DivByZero|(InfIn&~(YInfM&DivOp));
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// output infinity with result sign if divide by zero
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if(`IEEE754) begin
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@ -36,11 +36,14 @@ module srtradix4 (
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input logic [`NE-1:0] XExpE, YExpE,
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input logic [`NF:0] XManE, YManE,
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input logic [`XLEN-1:0] SrcA, SrcB,
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input logic XZeroE,
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input logic XInfE, YInfE,
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input logic XZeroE, YZeroE,
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input logic XNaNE, YNaNE,
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input logic W64, // 32-bit ints on XLEN=64
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input logic Signed, // Interpret integers as signed 2's complement
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input logic Int, // Choose integer inputs
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input logic Sqrt, // perform square root, not divide
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output logic [$clog2(`DIVLEN/2+3)-1:0] EarlyTermShiftDiv2E,
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output logic DivDone,
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output logic DivStickyE,
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output logic DivNegStickyE,
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@ -49,10 +52,9 @@ module srtradix4 (
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output logic [`NE+1:0] DivCalcExpE
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);
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// logic qp, qz, qm; // quotient is +1, 0, or -1
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logic [3:0] q;
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logic [`NE+1:0] DivCalcExp;
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logic [`DIVLEN:0] X;
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logic [`DIVLEN-1:0] X;
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logic [`DIVLEN-1:0] Dpreproc;
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logic [`DIVLEN+3:0] WS, WSA, WSN;
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logic [`DIVLEN+3:0] WC, WCA, WCN;
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@ -68,13 +70,11 @@ module srtradix4 (
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// When start is asserted, the inputs are loaded into the divider.
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// Otherwise, the divisor is retained and the partial remainder
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// is fed back for the next iteration.
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// - assumed one is added here since all numbers are normlaized
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// *** wait what about zero? is that specal case? can the divider handle it?
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// - when the start signal is asserted X and 0 are loaded into WS and WC
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// - otherwise load WSA into the flipflop
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// *** what does N and A stand for?
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// *** change shift amount for radix4
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mux2 #(`DIVLEN+4) wsmux({WSA[`DIVLEN+1:0], 2'b0}, {3'b000, X}, DivStart, WSN);
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// - the assumed one is added to D since it's always normalized (and X/0 is a special case handeled by result selection)
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// - XZeroE is used as the assumed one to avoid creating a sticky bit - all other numbers are normalized
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mux2 #(`DIVLEN+4) wsmux({WSA[`DIVLEN+1:0], 2'b0}, {3'b000, ~XZeroE, X}, DivStart, WSN);
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flop #(`DIVLEN+4) wsflop(clk, WSN, WS);
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mux2 #(`DIVLEN+4) wcmux({WCA[`DIVLEN+1:0], 2'b0}, {`DIVLEN+4{1'b0}}, DivStart, WCN);
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flop #(`DIVLEN+4) wcflop(clk, WCN, WC);
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@ -117,12 +117,11 @@ module srtradix4 (
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//*** change for radix 4
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otfc4 otfc4(.clk, .DivStart, .q, .Quot);
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assign DivStickyE = (WS+WC) != 0; //replace with early termination
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assign DivNegStickyE = $signed(WS+WC) < 0; //replace with early termination
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expcalc expcalc(.XExpE, .YExpE, .XZeroE, .XZeroCnt, .YZeroCnt, .DivCalcExp);
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divcounter divcounter(clk, DivStart, DivDone);
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earlytermination earlytermination(.clk, .WC, .WS, .XZeroE, .YZeroE, .XInfE, .EarlyTermShiftDiv2E,
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.YInfE, .XNaNE, .YNaNE, .DivStickyE, .DivNegStickyE, .DivStart, .DivDone);
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endmodule
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@ -130,28 +129,35 @@ endmodule
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// Submodules //
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////////////////
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/////////////
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// counter //
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/////////////
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module divcounter(input logic clk,
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input logic DivStart,
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output logic DivDone);
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module earlytermination(
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input logic clk,
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input logic [`DIVLEN+3:0] WS, WC,
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input logic XInfE, YInfE,
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input logic XZeroE, YZeroE,
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input logic XNaNE, YNaNE,
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input logic DivStart,
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output logic [$clog2(`DIVLEN/2+3)-1:0] EarlyTermShiftDiv2E,
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output logic DivStickyE,
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output logic DivNegStickyE,
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output logic DivDone);
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logic [5:0] count;
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// This block of control logic sequences the divider
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// through its iterations. You may modify it if you
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// build a divider which completes in fewer iterations.
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// You are not responsible for the (trivial) circuit
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// design of the block.
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logic [$clog2(`DIVLEN/2+3)-1:0] Count;
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logic WZero;
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assign WZero = (WS+WC == 0)|XZeroE|YZeroE|XInfE|YInfE|XNaNE|YNaNE; //*** temporary
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// *** rather than Counting should just be able to check if one of the two msbs of the quotent is 1 then stop???
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assign DivDone = (DivStickyE | WZero);
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assign DivStickyE = ~|Count;
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assign DivNegStickyE = $signed(WS+WC) < 0;
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assign EarlyTermShiftDiv2E = Count;
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// +1 for setup
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// `DIVLEN/2 to get required number of bits
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// +1 for possible .5 and round bit
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// Count down Counter
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always @(posedge clk)
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begin
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DivDone = 0;
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if (count == `DIVLEN/2+1) DivDone <= #1 1;
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else if (DivDone | DivStart) DivDone <= #1 0;
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if (DivStart) count <= #1 0;
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else count <= #1 count+1;
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if (DivStart) Count <= #1 `DIVLEN/2+2;
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else Count <= #1 Count-1;
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end
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endmodule
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@ -237,7 +243,7 @@ module srtpreproc (
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input logic Signed, // Interpret integers as signed 2's complement
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input logic Int, // Choose integer inputs
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input logic Sqrt, // perform square root, not divide
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output logic [`DIVLEN:0] X,
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output logic [`DIVLEN-1:0] X,
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output logic [`DIVLEN-1:0] Dpreproc,
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output logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt,
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output logic [$clog2(`XLEN+1)-1:0] intExp, // Quotient integer exponent
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@ -245,7 +251,7 @@ module srtpreproc (
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);
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// logic [`XLEN-1:0] PosA, PosB;
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// logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY;
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logic [`DIVLEN:0] PreprocA, PreprocX;
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logic [`DIVLEN-1:0] PreprocA, PreprocX;
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logic [`DIVLEN-1:0] PreprocB, PreprocY;
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// assign PosA = (Signed & SrcA[`XLEN - 1]) ? -SrcA : SrcA;
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@ -263,7 +269,7 @@ module srtpreproc (
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// assign PreprocA = ExtraA << zeroCntA;
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// assign PreprocB = ExtraB << (zeroCntB + 1);
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assign PreprocX = {XManE<<XZeroCnt, {`DIVLEN-`NF{1'b0}}};
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assign PreprocX = {XManE[`NF-1:0]<<XZeroCnt, {`DIVLEN-`NF{1'b0}}};
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assign PreprocY = {YManE[`NF-1:0]<<YZeroCnt, {`DIVLEN-`NF{1'b0}}};
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@ -300,7 +306,7 @@ module otfc4 (
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// if starting a new divison set Q to 0 and QM to -1
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mux2 #(`DIVLEN+3) Qmux(QNext, {`DIVLEN+3{1'b0}}, DivStart, QMux);
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mux2 #(`DIVLEN+3) QMmux(QMNext, {`DIVLEN+3{1'b1}}, DivStart, QMMux);
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flop #(`DIVLEN+3) Qreg(clk, QMux, Quot);
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flop #(`DIVLEN+3) Qreg(clk, QMux, Quot); // *** have to connect Quot directly to M stage
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flop #(`DIVLEN+3) QMreg(clk, QMMux, QM);
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// shift Q (quotent) and QM (quotent-1)
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@ -331,8 +337,7 @@ module otfc4 (
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QMNext = {QMR, 2'b11};
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end
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end
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// Quot is in the range [.5, 2) so normalize the result if nesissary
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// assign Quot = Q[`DIVLEN+2] ? Q[`DIVLEN+1:2] : Q[`DIVLEN:1];
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// Final Quoteint is in the range [.5, 2)
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endmodule
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@ -371,7 +376,7 @@ module expcalc(
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output logic [`NE+1:0] DivCalcExp
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);
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// correct exponent for denormal shifts
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// correct exponent for denormalized input's normalization shifts
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assign DivCalcExp = (XExpE - XZeroCnt - YExpE + YZeroCnt + (`NE)'(`BIAS))&{`NE+2{~XZeroE}};
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endmodule
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@ -55,6 +55,7 @@ module testbenchfp;
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logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
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logic [`DIVLEN+2:0] Quot;
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logic CvtResDenormUfE;
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logic [$clog2(`DIVLEN/2+3)-1:0] EarlyTermShiftDiv2;
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logic DivStart, DivDone;
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@ -651,7 +652,7 @@ module testbenchfp;
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.XInfM(XInf), .YInfM(YInf), .ZInfM(ZInf), .CvtResSgnM(CvtResSgnE), .FWriteIntM(WriteIntVal),
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.XSNaNM(XSNaN), .YSNaNM(YSNaN), .ZSNaNM(ZSNaN), .CvtLzcInM(CvtLzcInE), .IntZeroM(IntZeroE),
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.KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE),
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.SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .FmaNormCntM(FmaNormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE), .FmtM(ModFmt), .FrmM(FrmVal),
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.SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .FmaNormCntM(FmaNormCntE), .EarlyTermShiftDiv2M(EarlyTermShiftDiv2), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE), .FmtM(ModFmt), .FrmM(FrmVal),
|
||||
.PostProcFlgM(Flg), .PostProcResM(FpRes), .FCvtIntResM(IntRes));
|
||||
|
||||
fcvt fcvt (.XSgnE(XSgn), .XExpE(XExp), .XManE(XMan), .ForwardedSrcAE(SrcA), .FWriteIntE(WriteIntVal),
|
||||
@ -660,9 +661,9 @@ module testbenchfp;
|
||||
fcmp fcmp (.FmtE(ModFmt), .FOpCtrlE(OpCtrlVal), .XSgnE(XSgn), .YSgnE(YSgn), .XExpE(XExp), .YExpE(YExp),
|
||||
.XManE(XMan), .YManE(YMan), .XZeroE(XZero), .YZeroE(YZero), .CmpIntResE(CmpRes),
|
||||
.XNaNE(XNaN), .YNaNE(YNaN), .XSNaNE(XSNaN), .YSNaNE(YSNaN), .FSrcXE(X), .FSrcYE(Y), .CmpNVE(CmpFlg[4]), .CmpFpResE(FpCmpRes));
|
||||
srtradix4 srtradix4(.clk, .DivStart, .XExpE(XExp), .YExpE(YExp), .DivCalcExpE(DivCalcExp), .XZeroE(XZero), .DivStickyE(DivSticky),
|
||||
.XManE(XMan), .YManE(YMan), .SrcA('0), .SrcB('0), .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(OpCtrlVal[0]),
|
||||
.DivNegStickyE(DivNegSticky), .DivDone, .Quot, .Rem());
|
||||
srtradix4 srtradix4(.clk, .DivStart, .XExpE(XExp), .YExpE(YExp), .DivCalcExpE(DivCalcExp), .XZeroE(XZero), .YZeroE(YZero), .DivStickyE(DivSticky),
|
||||
.XManE(XMan), .YManE(YMan), .SrcA('0), .SrcB('0), .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(OpCtrlVal[0]), .XNaNE(XNaN), .YNaNE(YNaN),
|
||||
.XInfE(XInf), .YInfE(YInf), .DivNegStickyE(DivNegSticky), .EarlyTermShiftDiv2E(EarlyTermShiftDiv2), .DivDone, .Quot, .Rem());
|
||||
|
||||
assign CmpFlg[3:0] = 0;
|
||||
|
||||
@ -815,8 +816,9 @@ end
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// check if the non-fma test is correct
|
||||
if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(DivDone^~(UnitVal == `DIVUNIT))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
|
||||
// check if result is correct
|
||||
// - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
|
||||
if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&((~DivStart&DivDone)^~(UnitVal == `DIVUNIT))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
|
||||
errors += 1;
|
||||
$display("There is an error in %s", Tests[TestNum]);
|
||||
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
|
||||
@ -839,7 +841,7 @@ end
|
||||
$stop;
|
||||
end
|
||||
|
||||
if(DivDone|(UnitVal != `DIVUNIT)) VectorNum += 1; // increment the vector
|
||||
if((~DivStart&DivDone)|(UnitVal != `DIVUNIT)) VectorNum += 1; // increment the vector
|
||||
|
||||
if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the end of file
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user