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Radix 2 Integer division working (without signs or remainder)
This commit is contained in:
cturek
parent
72e216d053
commit
2faa8847f4
BIN
pipelined/srt/inttestgen
Executable file
BIN
pipelined/srt/inttestgen
Executable file
Binary file not shown.
83
pipelined/srt/inttestgen.c
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83
pipelined/srt/inttestgen.c
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@ -0,0 +1,83 @@
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/* testgen.c */
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/* Written 10/31/96 by David Harris
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This program creates test vectors for mantissa component
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of an IEEE floating point divider.
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*/
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/* #includes */
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#include <stdio.h>
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#include <stdlib.h>
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#include <math.h>
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/* Constants */
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#define ENTRIES 10
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#define RANDOM_VECS 500
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/* Prototypes */
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void output(FILE *fptr, long a, long b, long r, long rem);
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void printhex(FILE *fptr, long x);
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double random_input(void);
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/* Main */
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void main(void)
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{
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FILE *fptr;
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long a, b, r, rem;
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long list[ENTRIES] = {1, 3, 5, 18, 25, 33, 42, 65, 103, 255};
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int i, j;
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if ((fptr = fopen("inttestvectors","w")) == NULL) {
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fprintf(stderr, "Couldn't write testvectors file\n");
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exit(1);
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}
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for (i=0; i<ENTRIES; i++) {
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b = list[i];
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for (j=0; j<ENTRIES; j++) {
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a = list[j];
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r = a/b;
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rem = a%b;
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output(fptr, a, b, r, rem);
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}
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}
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// for (i = 0; i< RANDOM_VECS; i++) {
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// a = random_input();
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// b = random_input();
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// r = a/b;
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// output(fptr, a, b, r);
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// }
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fclose(fptr);
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}
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/* Functions */
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void output(FILE *fptr, long a, long b, long r, long rem)
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{
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printhex(fptr, a);
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fprintf(fptr, "_");
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printhex(fptr, b);
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fprintf(fptr, "_");
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printhex(fptr, r);
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fprintf(fptr, "_");
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printhex(fptr, rem);
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fprintf(fptr, "\n");
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}
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void printhex(FILE *fptr, long m)
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{
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fprintf(fptr, "%016llx", m);
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}
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double random_input(void)
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{
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return 1.0 + rand()/32767.0;
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}
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@ -1,3 +1,5 @@
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add wave -noupdate /testbench/*
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add wave -noupdate /testbench/srt/*
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add wave -noupdate /testbench/srt/otfc2/*
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add wave -noupdate /testbench/srt/preproc/*
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add wave -noupdate /testbench/srt/divcounter/*
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@ -48,8 +48,8 @@ module srt (
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input logic Signed, // Interpret integers as signed 2's complement
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input logic Int, // Choose integer inputs
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input logic Sqrt, // perform square root, not divide
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output logic rsign,
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output logic [`DIVLEN-1:0] Quot, Rem, QuotOTFC, // *** later handle integers
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output logic rsign, done,
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output logic [`DIVLEN-1:0] Rem, Quot, // *** later handle integers
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output logic [`NE-1:0] rExp,
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output logic [3:0] Flags
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);
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@ -59,11 +59,10 @@ module srt (
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logic calcSign;
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logic [`DIVLEN-1:0] X, Dpreproc;
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logic [`DIVLEN+3:0] WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel;
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logic [`DIVLEN+2:0] rp, rm;
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logic [$clog2(`XLEN+1)-1:0] intExp;
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logic [$clog2(`XLEN+1)-1:0] intExp, dur, calcDur;
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logic intSign;
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srtpreproc preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc, intExp, intSign);
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srtpreproc preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc, intExp, calcDur, intSign);
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// Top Muxes and Registers
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// When start is asserted, the inputs are loaded into the divider.
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@ -78,25 +77,25 @@ module srt (
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// Quotient Selection logic
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// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
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qsel2 qsel2(WS[`DIVLEN+3:`DIVLEN], WC[`DIVLEN+3:`DIVLEN], qp, qz, qm);
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// Accumulate quotient digits in a shift register (now done in OTFC)
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qacc #(`DIVLEN+3) qacc(clk, Start, qp, qz, qm, rp, rm);
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flopen #(`NE) expflop(clk, Start, calcExp, rExp);
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flopen #(1) signflop(clk, Start, calcSign, rsign);
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flopen #(7) durflop(clk, Start, calcDur, dur);
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counter divcounter(clk, Start, dur, done);
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// Divisor Selection logic
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inv dinv(D, Db);
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assign Db = ~D;
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mux3onehot #(`DIVLEN) divisorsel(Db, {(`DIVLEN+4){1'b0}}, D, qp, qz, qm, Dsel);
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// Partial Product Generation
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csa #(`DIVLEN+4) csa(WS, WC, Dsel, qp, WSA, WCA);
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otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, QuotOTFC);
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otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot);
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expcalc expcalc(.XExp, .YExp, .calcExp);
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signcalc signcalc(.XSign, .YSign, .calcSign);
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srtpostproc postproc(rp, rm, Quot);
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endmodule
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////////////////
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@ -115,7 +114,7 @@ module srtpreproc (
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input logic Int, // Choose integer inputs
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input logic Sqrt, // perform square root, not divide
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output logic [`DIVLEN-1:0] X, D,
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output logic [$clog2(`XLEN+1)-1:0] intExp, // Quotient integer exponent
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output logic [$clog2(`XLEN+1)-1:0] intExp, dur, // Quotient integer exponent
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output logic intSign // Quotient integer sign
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);
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@ -132,8 +131,8 @@ module srtpreproc (
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assign ExtraA = {PosA, {`EXTRAINTBITS{1'b0}}};
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assign ExtraB = {PosB, {`EXTRAINTBITS{1'b0}}};
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assign PreprocA = ExtraA << zeroCntA;
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assign PreprocB = ExtraB << zeroCntB;
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assign PreprocA = ExtraA << (zeroCntA + 1);
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assign PreprocB = ExtraB << (zeroCntB + 1);
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assign PreprocX = {SrcXFrac, {`EXTRAFRACBITS{1'b0}}};
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assign PreprocY = {SrcYFrac, {`EXTRAFRACBITS{1'b0}}};
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@ -142,6 +141,8 @@ module srtpreproc (
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assign D = Int ? PreprocB : PreprocY;
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assign intExp = zeroCntB - zeroCntA + 1;
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assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]);
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assign dur = Int ? (intExp & {7{~intExp[6]}}) : (`DIVLEN + 2);
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endmodule
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/////////////////////////////////
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@ -179,38 +180,10 @@ module qsel2 ( // *** eventually just change to 4 bits
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assign #1 qm = magnitude & sign;
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endmodule
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//////////
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// qacc //
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//////////
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// To be replaced by OTFC
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module qacc #(parameter N=68) (
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input logic clk,
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input logic req,
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input logic qp, qz, qm,
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output logic [N-1:0] rp, rm
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);
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flopr #(N) rmreg(clk, req, {rm[N-2:0], qm}, rm);
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flopr #(N) rpreg(clk, req, {rp[N-2:0], qp}, rp);
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/* always @(posedge clk)
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begin
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if (req)
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begin
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rp <= #1 0;
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rm <= #1 0;
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end
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else
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begin
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rm <= #1 {rm[54:0], qm};
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rp <= #1 {rp[54:0], qp};
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end
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end */
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endmodule
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///////////////////////////////////
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// On-The-Fly Converter, Radix 2 //
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///////////////////////////////////
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module otfc2 #(parameter N=65) (
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module otfc2 #(parameter N=64) (
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input logic clk,
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input logic Start,
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input logic qp, qz, qm,
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@ -254,13 +227,29 @@ module otfc2 #(parameter N=65) (
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endmodule
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/////////
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// inv //
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/////////
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module inv(input logic [`DIVLEN+3:0] in,
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output logic [`DIVLEN+3:0] out);
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/////////////
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// counter //
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/////////////
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module counter(input logic clk,
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input logic req,
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input logic [$clog2(`XLEN+1)-1:0] dur,
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output logic done);
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logic [$clog2(`XLEN+1)-1:0] count;
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assign #1 out = ~in;
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// This block of control logic sequences the divider
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// through its iterations. You may modify it if you
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// build a divider which completes in fewer iterations.
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// You are not responsible for the (trivial) circuit
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// design of the block.
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always @(posedge clk)
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begin
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if (count == dur) done <= #1 1;
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else if (done | req) done <= #1 0;
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if (req) count <= #1 0;
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else count <= #1 count+1;
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end
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endmodule
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//////////
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@ -323,43 +312,4 @@ module signcalc(
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assign calcSign = XSign ^ YSign;
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endmodule
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////////////////////
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// Postprocessing //
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////////////////////
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module srtpostproc (
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input [`DIVLEN+2:0] rp, rm,
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output [`DIVLEN-1:0] Quot
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);
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//assign Quot = rp - rm;
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finaladd #(`DIVLEN+3) finaladd(rp, rm, Quot);
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endmodule
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//////////////
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// finaladd //
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//////////////
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module finaladd #(parameter N=68) (
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input logic [N-1:0] rp, rm,
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output logic [N-4:0] r
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);
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logic [N-1:0] diff;
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// this magic block performs the final addition for you
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// to convert the positive and negative quotient digits
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// into a normalized mantissa. It returns the 52 bit
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// mantissa after shifting to guarantee a leading 1.
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// You can assume this block operates in one cycle
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// and do not need to budget it in your area and power
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// calculations.
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// Since no rounding is performed, the result may be too
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// small by one unit in the least significant place (ulp).
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// The checker ignores such an error.
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assign #1 diff = rp - rm;
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assign #1 r = diff[N-1] ? diff[N-2:2] : diff[N-3:1];
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endmodule
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endmodule
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@ -3,26 +3,26 @@
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/////////////
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// counter //
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/////////////
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module counter(input logic clk,
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input logic req,
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output logic done);
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// module counter(input logic clk,
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// input logic req,
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// output logic done);
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logic [7:0] count;
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// logic [7:0] count;
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// This block of control logic sequences the divider
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// through its iterations. You may modify it if you
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// build a divider which completes in fewer iterations.
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// You are not responsible for the (trivial) circuit
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// design of the block.
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// // This block of control logic sequences the divider
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// // through its iterations. You may modify it if you
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// // build a divider which completes in fewer iterations.
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// // You are not responsible for the (trivial) circuit
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// // design of the block.
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always @(posedge clk)
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begin
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if (count == `DIVLEN + 2) done <= #1 1;
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else if (done | req) done <= #1 0;
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if (req) count <= #1 0;
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else count <= #1 count+1;
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end
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endmodule
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// always @(posedge clk)
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// begin
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// if (count == `DIVLEN + 2) done <= #1 1;
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// else if (done | req) done <= #1 0;
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// if (req) count <= #1 0;
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// else count <= #1 count+1;
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// end
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// endmodule
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///////////
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// clock //
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@ -42,21 +42,23 @@ module testbench;
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logic clk;
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logic req;
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logic done;
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logic Int;
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logic [63:0] a, b;
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logic [51:0] afrac, bfrac;
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logic [10:0] aExp, bExp;
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logic asign, bsign;
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logic [51:0] r, rOTFC;
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logic [`DIVLEN-1:0] Quot, QuotOTFC;
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logic [54:0] rp, rm; // positive quotient digits
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logic [51:0] r;
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logic [63:0] rInt;
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logic [`DIVLEN-1:0] Quot;
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// Test parameters
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parameter MEM_SIZE = 40000;
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parameter MEM_WIDTH = 64+64+64;
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parameter MEM_WIDTH = 64+64+64+64;
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`define memr 63:0
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`define memb 127:64
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`define mema 191:128
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`define memrem 63:0
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`define memr 127:64
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`define memb 191:128
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`define mema 255:192
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// Test logicisters
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logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
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@ -67,18 +69,20 @@ module testbench;
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logic rsign;
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integer testnum, errors;
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assign Int = 1'b1;
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// Divider
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srt srt(.clk, .Start(req),
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.Stall(1'b0), .Flush(1'b0),
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.XExp(aExp), .YExp(bExp), .rExp,
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.XSign(asign), .YSign(bsign), .rsign,
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.SrcXFrac(afrac), .SrcYFrac(bfrac),
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.SrcA('0), .SrcB('0), .Fmt(2'b00),
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.W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0),
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.Quot, .QuotOTFC, .Rem(), .Flags());
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.SrcA(a), .SrcB(b), .Fmt(2'b00),
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.W64(1'b1), .Signed(1'b0), .Int, .Sqrt(1'b0),
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.Quot, .Rem(), .Flags(), .done);
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// Counter
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counter counter(clk, req, done);
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// counter counter(clk, req, done);
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initial
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@ -94,7 +98,7 @@ module testbench;
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begin
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testnum = 0;
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errors = 0;
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$readmemh ("testvectors", Tests);
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$readmemh ("inttestvectors", Tests);
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Vec = Tests[testnum];
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a = Vec[`mema];
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{asign, aExp, afrac} = a;
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@ -102,7 +106,7 @@ module testbench;
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{bsign, bExp, bfrac} = b;
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nextr = Vec[`memr];
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r = Quot[(`DIVLEN - 1):(`DIVLEN - 52)];
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rOTFC = QuotOTFC[(`DIVLEN - 1):(`DIVLEN - 52)];
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rInt = Quot;
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req <= #5 1;
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end
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@ -111,45 +115,54 @@ module testbench;
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always @(posedge clk)
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begin
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r = Quot[(`DIVLEN - 1):(`DIVLEN - 52)];
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rOTFC = QuotOTFC[(`DIVLEN - 1):(`DIVLEN - 52)];
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if (done)
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begin
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req <= #5 1;
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diffp = correctr[51:0] - r;
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diffn = r - correctr[51:0];
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if ((rsign !== correctr[63]) | (rExp !== correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
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begin
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errors = errors+1;
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$display("result was %h_%h, should be %h %h %h\n", rExp, r, correctr, diffn, diffp);
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$display("failed\n");
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$stop;
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end
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if (r !== rOTFC) // Check if OTFC works
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begin
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errors = errors+1;
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$display("OTFC is %h, should be %h\n", rOTFC, r);
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$display("failed\n");
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// $stop;
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rInt = Quot;
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if (done) begin
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if (~Int) begin
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req <= #5 1;
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diffp = correctr[51:0] - r;
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diffn = r - correctr[51:0];
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if ((rsign !== correctr[63]) | (rExp !== correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
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begin
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errors = errors+1;
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$display("result was %h_%h, should be %h %h %h\n", rExp, r, correctr, diffn, diffp);
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$display("failed\n");
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$stop;
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end
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if (afrac === 52'hxxxxxxxxxxxxx)
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begin
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$display("%d Tests completed successfully", testnum);
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$stop;
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end
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end else begin
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req <= #5 1;
|
||||
diffp = correctr[63:0] - rInt;
|
||||
diffn = rInt - correctr[63:0];
|
||||
if (($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
|
||||
begin
|
||||
errors = errors+1;
|
||||
$display("result was %h, should be %h %h %h\n", rInt, correctr, diffn, diffp);
|
||||
$display("failed\n");
|
||||
$stop;
|
||||
end
|
||||
if (afrac === 52'hxxxxxxxxxxxxx)
|
||||
begin
|
||||
$display("%d Tests completed successfully", testnum);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
if (afrac === 52'hxxxxxxxxxxxxx)
|
||||
begin
|
||||
$display("%d Tests completed successfully", testnum);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
if (req)
|
||||
begin
|
||||
req <= #5 0;
|
||||
correctr = nextr;
|
||||
testnum = testnum+1;
|
||||
Vec = Tests[testnum];
|
||||
$display("a = %h b = %h",a,b);
|
||||
a = Vec[`mema];
|
||||
{asign, aExp, afrac} = a;
|
||||
b = Vec[`memb];
|
||||
{bsign, bExp, bfrac} = b;
|
||||
nextr = Vec[`memr];
|
||||
end
|
||||
if (req) begin
|
||||
req <= #5 0;
|
||||
correctr = nextr;
|
||||
testnum = testnum+1;
|
||||
Vec = Tests[testnum];
|
||||
$display("a = %h b = %h",a,b);
|
||||
a = Vec[`mema];
|
||||
{asign, aExp, afrac} = a;
|
||||
b = Vec[`memb];
|
||||
{bsign, bExp, bfrac} = b;
|
||||
nextr = Vec[`memr];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user