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Fixed bug.

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It was possible for DTLBMissM to prevent a dcache flush.
This commit is contained in:
Ross Thompson 2022-02-11 14:00:01 -06:00
parent b1cba4be2b
commit c8e6884926
3 changed files with 8 additions and 6 deletions
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2
bugs.txt Normal file
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@ -0,0 +1,2 @@
1. [X] Cache is suppressing d cache flush if there is a dtlb miss.
1. Fixed by disabling mmu's address translation on flush.

10
pipelined/src/cache/cachefsm.sv vendored
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@ -113,8 +113,8 @@ module cachefsm
// using both IgnoreRequestTLB and IgnoreRequestTrapM. Otherwise we can just use IgnoreRequestTLB.
// need to re organize all of these. Low priority though.
assign DoFlush = FlushCache & ~IgnoreRequest;
assign AMO = Atomic[1] & (&RW);
assign DoFlush = FlushCache & ~IgnoreRequestTrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation.
assign AMO = Atomic[1] & (&RW);
assign DoAMO = AMO & ~IgnoreRequest;
assign DoAMOHit = DoAMO & CacheHit;
assign DoAMOMiss = DoAMO & ~CacheHit;
@ -188,7 +188,7 @@ module cachefsm
// com back to CPU
assign CacheCommitted = CurrState != STATE_READY;
assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAMOMiss | DoReadMiss | DoWriteMiss)) |
assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAMOMiss | DoReadMiss | DoWriteMiss)) |
(CurrState == STATE_MISS_FETCH_WDV) |
(CurrState == STATE_MISS_FETCH_DONE) |
(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
@ -224,8 +224,8 @@ module cachefsm
(CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayFlag & ~FlushAdrFlag);
assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag));
assign FlushAdrCntRst = (CurrState == STATE_READY & DoFlush);
assign FlushWayCntRst = (CurrState == STATE_READY & DoFlush) | (CurrState == STATE_FLUSH_INCR);
assign FlushAdrCntRst = (CurrState == STATE_READY);
assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR);
// Bus interface controls
assign CacheFetchLine = (CurrState == STATE_READY & (DoAMOMiss | DoWriteMiss | DoReadMiss));
assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) |

2
pipelined/src/lsu/lsu.sv
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@ -139,7 +139,7 @@ module lsu (
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .DisableTranslation(SelHPTW),
.PrivilegeModeW, .DisableTranslation(SelHPTW | FlushDCacheM),
.PAdr(PreLSUPAdrM),
.VAdr(IEUAdrM),
.Size(LSUFunct3M[1:0]),