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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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resolved merge conflict
This commit is contained in:
mmasserfrye 2022-05-16 15:42:59 +00:00
commit c8e43e9798
20 changed files with 277 additions and 119 deletions
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6
pipelined/src/ppa/ppa.sv
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@ -291,9 +291,9 @@ module ppa_prioriyencoder #(parameter N = 8) (
end
endmodule
module ppa_decoder #(parameter N = 8) (
input logic [$clog2(N)-1:0] a,
output logic [N-1:0] y);
module ppa_decoder #(parameter WIDTH = 8) (
input logic [$clog2(WIDTH)-1:0] a,
output logic [WIDTH-1:0] y);
always_comb begin
y = 0;
y[a] = 1;

77
pipelined/src/privileged/csr.sv
View File

@ -40,8 +40,8 @@ module csr #(parameter
input logic FlushE, FlushM, FlushW,
input logic StallE, StallM, StallW,
input logic [31:0] InstrM,
input logic [`XLEN-1:0] PCM, SrcAM,
input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, mretM, sretM, wfiM, InterruptM,
input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM,
input logic CSRReadM, CSRWriteM, TrapM, mretM, sretM, wfiM, InterruptM,
input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT,
input logic InstrValidM, FRegWriteM, LoadStallD,
@ -55,11 +55,10 @@ module csr #(parameter
input logic ICacheMiss,
input logic ICacheAccess,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
input logic [`LOG_XLEN-1:0] CauseM,
input logic SelHPTW,
output logic [1:0] STATUS_MPP,
output logic STATUS_SPP, STATUS_TSR, STATUS_TVM,
output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW,
output logic [`XLEN-1:0] MEDELEG_REGW,
output logic [`XLEN-1:0] SATP_REGW,
output logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
@ -71,7 +70,7 @@ module csr #(parameter
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW,
output logic [`XLEN-1:0] CSRReadValW,
output logic [`XLEN-1:0] CSRReadValW, PrivilegedNextPCM,
output logic IllegalCSRAccessM, BigEndianM
);
@ -83,6 +82,9 @@ module csr #(parameter
(* mark_debug = "true" *) logic [`XLEN-1:0] CSRWriteValM;
(* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
logic [`XLEN-1:0] STVEC_REGW, MTVEC_REGW;
logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW;
logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
logic CSRMWriteM, CSRSWriteM, CSRUWriteM;
@ -91,16 +93,65 @@ module csr #(parameter
logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM;
logic [11:0] CSRAdrM;
//logic [11:0] UIP_REGW, UIE_REGW = 0; // N user-mode exceptions not supported
logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, InsufficientCSRPrivilegeM;
logic IllegalCSRMWriteReadonlyM;
logic [`XLEN-1:0] CSRReadVal2M;
logic [11:0] MIP_REGW_writeable;
logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector, NextFaultMtvalM;
logic MTrapM, STrapM;
logic InstrValidNotFlushedM;
assign InstrValidNotFlushedM = ~StallW & ~FlushW;
// modify CSRs
///////////////////////////////////////////
// MTVAL
///////////////////////////////////////////
always_comb
if (InterruptM) NextFaultMtvalM = 0;
else case (CauseM)
12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint
2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault
0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults
default: NextFaultMtvalM = 0; // Ecall, interrupts
endcase
///////////////////////////////////////////
// Trap Vectoring
///////////////////////////////////////////
//
// POSSIBLE OPTIMIZATION:
// From 20190608 privielegd spec page 27 (3.1.7)
// > Allowing coarser alignments in Vectored mode enables vectoring to be
// > implemented without a hardware adder circuit.
// For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with
// [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000}
// However, this is program dependent, so not implemented at this time.
always_comb
if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW;
else PrivilegedTrapVector = MTVEC_REGW;
if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
always_comb
if (PrivilegedTrapVector[1:0] == 2'b01 & InterruptM)
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM}, 2'b00};
else
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
end
else begin
assign PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
end
always_comb
if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector;
else if (mretM) PrivilegedNextPCM = MEPC_REGW;
else PrivilegedNextPCM = SEPC_REGW;
///////////////////////////////////////////
// CSRWriteValM
///////////////////////////////////////////
always_comb begin
// Choose either rs1 or uimm[4:0] as source
CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
@ -121,15 +172,23 @@ module csr #(parameter
endcase
end
// write CSRs
///////////////////////////////////////////
// CSR Write values
///////////////////////////////////////////
assign CSRAdrM = InstrM[31:20];
assign UnalignedNextEPCM = TrapM ? ((wfiM & InterruptM) ? PCM+4 : PCM) : CSRWriteValM;
assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
assign NextCauseM = TrapM ? CauseM : CSRWriteValM;
assign NextCauseM = TrapM ? {InterruptM, {(`XLEN-`LOG_XLEN-1){1'b0}}, CauseM}: CSRWriteValM;
assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);
assign CSRUWriteM = CSRWriteM;
assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
///////////////////////////////////////////
// CSRs
///////////////////////////////////////////
csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW,
.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,

47
pipelined/src/privileged/privileged.sv
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@ -81,20 +81,18 @@ module privileged (
output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM
);
logic [`XLEN-1:0] CauseM, NextFaultMtvalM;
logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW;
logic [`LOG_XLEN-1:0] CauseM;
logic [`XLEN-1:0] MEDELEG_REGW;
logic [11:0] MIDELEG_REGW;
logic sretM, mretM, sfencevmaM;
logic IllegalCSRAccessM;
logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM;
logic IllegalIEUInstrFaultM;
logic IllegalFPUInstrM;
logic InstrPageFaultD, InstrPageFaultE, InstrPageFaultM;
logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM;
logic InstrPageFaultM;
logic InstrAccessFaultM;
logic IllegalInstrFaultM;
logic MTrapM, STrapM;
(* mark_debug = "true" *) logic InterruptM;
logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM;
@ -106,7 +104,7 @@ module privileged (
// track the current privilege level
///////////////////////////////////////////
privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .CauseM,
privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .InterruptM, .CauseM,
.MEDELEG_REGW, .MIDELEG_REGW, .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
///////////////////////////////////////////
@ -125,18 +123,17 @@ module privileged (
csr csr(.clk, .reset,
.FlushE, .FlushM, .FlushW,
.StallE, .StallM, .StallW,
.InstrM, .PCM, .SrcAM,
.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .mretM, .sretM, .wfiM, .InterruptM,
.InstrM, .PCM, .SrcAM, .IEUAdrM,
.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .InterruptM,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
.MTIME_CLINT,
.InstrValidM, .FRegWriteM, .LoadStallD,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
.BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
.NextPrivilegeModeM, .PrivilegeModeW,
.CauseM, .NextFaultMtvalM, .SelHPTW,
.CauseM, .SelHPTW,
.STATUS_MPP,
.STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
.MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW,
.MEDELEG_REGW,
.SATP_REGW,
.MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
@ -146,37 +143,27 @@ module privileged (
.PMPADDR_ARRAY_REGW,
.SetFflagsM,
.FRM_REGW,
.CSRReadValW,
.CSRReadValW,.PrivilegedNextPCM,
.IllegalCSRAccessM, .BigEndianM);
// pipeline fault signals
flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
{InstrPageFaultF, InstrAccessFaultF},
{InstrPageFaultD, InstrAccessFaultD});
flopenrc #(4) faultregE(clk, reset, FlushE, ~StallE,
{IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD, IllegalFPUInstrD}, // ** vs IllegalInstrFaultInD
{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE});
flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM,
{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
// *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
.InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
.IllegalFPUInstrE,
.InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUInstrFaultM, .IllegalFPUInstrM);
trap trap(.reset,
.InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
.BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
.LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
.LoadPageFaultM, .StoreAmoPageFaultM,
.mretM, .sretM,
.PrivilegeModeW, .NextPrivilegeModeM,
.MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW,
.PrivilegeModeW,
.MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
.STATUS_MIE, .STATUS_SIE,
.PCM,
.IEUAdrM,
.InstrM,
.InstrValidM, .CommittedM,
.TrapM, .MTrapM, .STrapM, .RetM,
.TrapM, .RetM,
.InterruptM, .IntPendingM,
.PrivilegedNextPCM, .CauseM, .NextFaultMtvalM);
.CauseM);
endmodule

7
pipelined/src/privileged/privmode.sv
View File

@ -33,8 +33,9 @@
module privmode (
input logic clk, reset,
input logic StallW, TrapM, mretM, sretM,
input logic [`XLEN-1:0] CauseM, MEDELEG_REGW,
input logic StallW, TrapM, mretM, sretM, InterruptM,
input logic [`LOG_XLEN-1:0] CauseM,
input logic [`XLEN-1:0] MEDELEG_REGW,
input logic [11:0] MIDELEG_REGW,
input logic [1:0] STATUS_MPP,
input logic STATUS_SPP,
@ -45,7 +46,7 @@ module privmode (
logic md;
// get bits of DELEG registers based on CAUSE
assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]];
assign md = InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM];
// PrivilegeMode FSM
always_comb begin

58
pipelined/src/privileged/privpiperegs.sv Normal file
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@ -0,0 +1,58 @@
///////////////////////////////////////////
// privpiperegs.sv
//
// Written: David_Harris@hmc.edu 12 May 2022
// Modified:
//
// Purpose: Pipeline registers for early exceptions
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// MIT LICENSE
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify, merge,
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
// to whom the Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or
// substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
// OR OTHER DEALINGS IN THE SOFTWARE.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module privpiperegs (
input logic clk, reset,
input logic StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM,
input logic InstrPageFaultF, InstrAccessFaultF,
input logic IllegalIEUInstrFaultD, IllegalFPUInstrD,
output logic IllegalFPUInstrE,
output logic InstrPageFaultM, InstrAccessFaultM,
output logic IllegalIEUInstrFaultM, IllegalFPUInstrM
);
logic InstrPageFaultD, InstrAccessFaultD;
logic InstrPageFaultE, InstrAccessFaultE;
logic IllegalIEUInstrFaultE;
// pipeline fault signals
flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
{InstrPageFaultF, InstrAccessFaultF},
{InstrPageFaultD, InstrAccessFaultD});
flopenrc #(4) faultregE(clk, reset, FlushE, ~StallE,
{IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD, IllegalFPUInstrD},
{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE});
flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM,
{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
endmodule

83
pipelined/src/privileged/trap.sv
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@ -38,26 +38,18 @@ module trap (
(* mark_debug = "true" *) input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM,
(* mark_debug = "true" *) input logic LoadPageFaultM, StoreAmoPageFaultM,
(* mark_debug = "true" *) input logic mretM, sretM,
input logic [1:0] PrivilegeModeW, NextPrivilegeModeM,
(* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW,
input logic [1:0] PrivilegeModeW,
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
input logic STATUS_MIE, STATUS_SIE,
input logic [`XLEN-1:0] PCM,
input logic [`XLEN-1:0] IEUAdrM,
input logic [31:0] InstrM,
input logic InstrValidM, CommittedM,
output logic TrapM, MTrapM, STrapM, RetM,
output logic TrapM, RetM,
output logic InterruptM, IntPendingM,
output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
// input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM
output logic [`LOG_XLEN-1:0] CauseM
);
logic MIntGlobalEnM, SIntGlobalEnM;
logic ExceptionM;
(* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM;
//logic InterruptM;
logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
///////////////////////////////////////////
// Determine pending enabled interrupts
@ -82,61 +74,27 @@ module trap (
InstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM |
BreakpointFaultM | EcallFaultM |
LoadAccessFaultM | StoreAmoAccessFaultM;
assign TrapM = ExceptionM | InterruptM; // *** clean this up later DH
assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
assign TrapM = ExceptionM | InterruptM;
assign RetM = mretM | sretM;
always_comb
if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW;
else PrivilegedTrapVector = MTVEC_REGW;
///////////////////////////////////////////
// Handle vectored traps (when mtvec/stvec csr value has bits [1:0] == 01)
// For vectored traps, set program counter to _tvec value + 4 times the cause code
///////////////////////////////////////////
//
// POSSIBLE OPTIMIZATION:
// From 20190608 privielegd spec page 27 (3.1.7)
// > Allowing coarser alignments in Vectored mode enables vectoring to be
// > implemented without a hardware adder circuit.
// For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with
// [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000}
// However, this is program dependent, so not implemented at this time.
if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
always_comb
if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1)
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00};
else
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
end
else begin
assign PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
end
always_comb
if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector;
else if (mretM) PrivilegedNextPCM = MEPC_REGW;
else PrivilegedNextPCM = SEPC_REGW;
///////////////////////////////////////////
// Cause priority defined in table 3.7 of 20190608 privileged spec
// Exceptions are of lower priority than all interrupts (3.1.9)
///////////////////////////////////////////
always_comb
if (reset) CauseM = 0; // hard reset 3.3
else if (ValidIntsM[11]) CauseM = (1 << (`XLEN-1)) + 11; // Machine External Int
else if (ValidIntsM[3]) CauseM = (1 << (`XLEN-1)) + 3; // Machine Sw Int
else if (ValidIntsM[7]) CauseM = (1 << (`XLEN-1)) + 7; // Machine Timer Int
else if (ValidIntsM[9]) CauseM = (1 << (`XLEN-1)) + 9; // Supervisor External Int
else if (ValidIntsM[1]) CauseM = (1 << (`XLEN-1)) + 1; // Supervisor Sw Int
else if (ValidIntsM[5]) CauseM = (1 << (`XLEN-1)) + 5; // Supervisor Timer Int
else if (ValidIntsM[11]) CauseM = 11; // Machine External Int
else if (ValidIntsM[3]) CauseM = 3; // Machine Sw Int
else if (ValidIntsM[7]) CauseM = 7; // Machine Timer Int
else if (ValidIntsM[9]) CauseM = 9; // Supervisor External Int
else if (ValidIntsM[1]) CauseM = 1; // Supervisor Sw Int
else if (ValidIntsM[5]) CauseM = 5; // Supervisor Timer Int
else if (InstrPageFaultM) CauseM = 12;
else if (InstrAccessFaultM) CauseM = 1;
else if (IllegalInstrFaultM) CauseM = 2;
else if (InstrMisalignedFaultM) CauseM = 0;
else if (BreakpointFaultM) CauseM = 3;
else if (EcallFaultM) CauseM = {{(`XLEN-2){1'b0}}, PrivilegeModeW} + 8;
else if (EcallFaultM) CauseM = {{(`LOG_XLEN-4){1'b0}}, {2'b10}, PrivilegeModeW};
else if (LoadMisalignedFaultM) CauseM = 4;
else if (StoreAmoMisalignedFaultM) CauseM = 6;
else if (LoadPageFaultM) CauseM = 13;
@ -144,23 +102,4 @@ module trap (
else if (LoadAccessFaultM) CauseM = 5;
else if (StoreAmoAccessFaultM) CauseM = 7;
else CauseM = 0;
///////////////////////////////////////////
// MTVAL
///////////////////////////////////////////
always_comb
if (InstrPageFaultM) NextFaultMtvalM = PCM;
else if (InstrAccessFaultM) NextFaultMtvalM = PCM;
else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};
else if (InstrMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
else if (EcallFaultM) NextFaultMtvalM = 0;
else if (BreakpointFaultM) NextFaultMtvalM = PCM;
else if (LoadMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
else if (StoreAmoMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
else if (LoadPageFaultM) NextFaultMtvalM = IEUAdrM;
else if (StoreAmoPageFaultM) NextFaultMtvalM = IEUAdrM;
else if (LoadAccessFaultM) NextFaultMtvalM = IEUAdrM;
else if (StoreAmoAccessFaultM) NextFaultMtvalM = IEUAdrM;
else NextFaultMtvalM = 0;
endmodule

2
pipelined/testbench/testbench.sv
View File

@ -208,7 +208,7 @@ logic [3:0] dummy;
always @(negedge clk)
begin
if (TEST == "coremark")
if (dut.core.priv.priv.ecallM) begin
if (dut.core.priv.priv.EcallFaultM) begin
$display("Benchmark: coremark is done.");
$stop;
end

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma.reference_output
View File

@ -1018,3 +1018,7 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

9
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output
View File

@ -1013,3 +1013,12 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

12
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output
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@ -1010,3 +1010,15 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

9
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output
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@ -1013,3 +1013,12 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

6
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
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@ -1016,3 +1016,9 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

6
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
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@ -1016,3 +1016,9 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

6
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output
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@ -1016,3 +1016,9 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output
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@ -1021,4 +1021,4 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

12
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma.reference_output
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@ -1010,3 +1010,15 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output
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@ -1018,3 +1018,7 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

12
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
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@ -1010,3 +1010,15 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

22
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output
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@ -1000,3 +1000,25 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
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deadbeef
deadbeef
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deadbeef
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deadbeef
deadbeef
deadbeef

12
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output
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@ -1010,3 +1010,15 @@ deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef