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Minor cleanup of lsu.

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This commit is contained in:
Ross Thompson 2022-02-21 12:46:06 -06:00
parent f48b12b089
commit 56fc6d0d7c
3 changed files with 14 additions and 13 deletions
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4
pipelined/src/lsu/lsu.sv
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@ -119,7 +119,7 @@ module lsu (
.DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
.TrapM, .DCacheStallM, .SATP_REGW, .PCF,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
.ReadDataM, .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrM,
.ReadDataM, .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
.IEUAdrExtM, .PTE, .LSUWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE,
.LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW,
.IgnoreRequestTLB, .IgnoreRequestTrapM);
@ -221,7 +221,7 @@ module lsu (
.s(SelUncachedAdr), .y(LSUBusHWDATA));
mux2 #(`PA_BITS) WordAdrrMux(.d0(LSUPAdrM),
.d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit),
.y(WordOffsetAddr));
.y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset.
if(`DMEM == `MEM_CACHE) begin : dcache

9
pipelined/src/lsu/lsuvirtmen.sv
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@ -53,7 +53,6 @@ module lsuvirtmem(
input logic [6:0] Funct7M,
output logic [6:0] LSUFunct7M,
input logic [`XLEN-1:0] IEUAdrE,
input logic [`XLEN-1:0] IEUAdrM,
output logic [`XLEN-1:0] PTE,
output logic [`XLEN-1:0] LSUWriteDataM,
output logic [1:0] PageType,
@ -88,7 +87,7 @@ module lsuvirtmem(
.DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM,
.InterlockStall, .SelReplayCPURequest, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM);
hptw hptw( // *** remove logic from (), mention this in style guide CH3
.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM, .MemRWM, .AtomicM,
.clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
.ITLBMissF(ITLBMissOrDAFaultF & ~TrapM), .DTLBMissM(DTLBMissOrDAFaultM & ~TrapM), // *** Fix me. *** I'm not sure ITLBMiss should be suppressed on TrapM.
.PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM),
@ -100,9 +99,11 @@ module lsuvirtmem(
mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);
mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE);
mux2 #(12) replaymux(PreLSUAdrE, IEUAdrM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw.
mux2 #(12) replaymux(PreLSUAdrE, IEUAdrExtM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw. *** redudant with mux in cache.
mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM);
mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, LSUWriteDataM);
if(`HPTW_WRITES_SUPPORTED)
mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, LSUWriteDataM);
else assign LSUWriteDataM = WriteDataM;
// always block interrupts when using the hardware page table walker.
assign CPUBusy = StallW & ~SelHPTW;

14
pipelined/src/mmu/hptw.sv
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@ -34,7 +34,8 @@ module hptw
(
input logic clk, reset,
input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
input logic [`XLEN-1:0] PCF, IEUAdrM, // addresses to translate
input logic [`XLEN-1:0] PCF, // addresses to translate
input logic [`XLEN+1:0] IEUAdrExtM, // addresses to translate
input logic [1:0] MemRWM, AtomicM,
// system status
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
@ -84,7 +85,7 @@ module hptw
assign TLBMiss = (DTLBMissM | ITLBMissF);
// Determine which address to translate
assign TranslationVAdr = DTLBWalk ? IEUAdrM : PCF;
assign TranslationVAdr = DTLBWalk ? IEUAdrExtM[`XLEN-1:0] : PCF;
assign CurrentPPN = PTE[`PPN_BITS+9:10];
// State flops
@ -116,11 +117,11 @@ module hptw
logic SetDirty;
logic Dirty, Accessed;
assign NextPTE = UpdatePTE ? {PTE[`XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]} : HPTWReadPTE; // This will be HPTWReadPTE if not handling DAPageFault.
assign NextPTE = UpdatePTE ? {PTE[`XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]} : HPTWReadPTE;
flopenr #(`PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
assign SaveHPTWAdr = WalkerState == L0_ADR;
assign SelHPTWWriteAdr = UpdatePTE | HPTWWrite;
mux2 #(`PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr); // HPTWAdr = HPTWReadAdr if not handling DAPageFault.
mux2 #(`PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr);
assign {Dirty, Accessed} = PTE[7:6];
@ -132,7 +133,7 @@ module hptw
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
((EffectivePrivilegeMode == `S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk));
// *** turn into module
// *** turn into module common with code in tlbcontrol.
if (`XLEN==64) begin:rv64
assign SV39Mode = (SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS] == `SV39);
// page fault if upper bits aren't all the same
@ -150,12 +151,11 @@ module hptw
assign OtherPageFault = DTLBWalk? ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequalPageFault | Misaligned | ~Valid :
ImproperPrivilege | ~Executable | UpperBitsUnequalPageFault | Misaligned | ~Valid;
// hptw needs to know if there is a Dirty or Access fault occuring on this
// memory access. If there is the PTE needs to be updated seting Access
// and possibly also Dirty. Dirty is set if the operation is a store/amo.
// However any other fault should not cause the update.
assign DAPageFault = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault; // set to 0 if not handling DAPageFault.
assign DAPageFault = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault;
assign HPTWWrite = (WalkerState == UPDATE_PTE);
assign UpdatePTE = WalkerState == LEAF & DAPageFault;