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https://github.com/openhwgroup/cvw
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srt batch files
This commit is contained in:
David Harris
parent
caa4d83e57
commit
3598e05998
1
pipelined/srt/lint-srt
Executable file
1
pipelined/srt/lint-srt
Executable file
@ -0,0 +1 @@
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verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv
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@ -1 +1 @@
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vsim -c -do srt.do
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vsim -c -do "do srt.do"
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@ -17,7 +17,7 @@ if [file exists work] {
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}
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vlib work
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vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv
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vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv
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vopt +acc work.testbench -o workopt
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vsim workopt
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@ -273,135 +273,3 @@ module finaladd(
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assign #1 r = diff[54] ? diff[53:2] : diff[52:1];
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endmodule
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/////////////
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// counter //
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/////////////
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module counter(input logic clk,
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input logic req,
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output logic done);
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logic [5:0] count;
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// This block of control logic sequences the divider
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// through its iterations. You may modify it if you
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// build a divider which completes in fewer iterations.
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// You are not responsible for the (trivial) circuit
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// design of the block.
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always @(posedge clk)
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begin
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if (count == 54) done <= #1 1;
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else if (done | req) done <= #1 0;
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if (req) count <= #1 0;
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else count <= #1 count+1;
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end
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endmodule
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///////////
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// clock //
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///////////
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module clock(clk);
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output clk;
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// Internal clk signal
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logic clk;
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endmodule
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//////////
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// testbench //
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//////////
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module testbench;
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logic clk;
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logic req;
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logic done;
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logic [51:0] a;
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logic [51:0] b;
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logic [51:0] r;
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logic [54:0] rp, rm; // positive quotient digits
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// Test parameters
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parameter MEM_SIZE = 40000;
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parameter MEM_WIDTH = 52+52+52;
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`define memr 51:0
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`define memb 103:52
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`define mema 155:104
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// Test logicisters
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logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
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logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a
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// bit field of an array
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logic [51:0] correctr, nextr, diffn, diffp;
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integer testnum, errors;
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// Divider
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srt #(52) srt(.clk, .Start(req),
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.Stall(1'b0), .Flush(1'b0),
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.SrcXFrac(a), .SrcYFrac(b),
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.SrcA('0), .SrcB('0), .Fmt(2'b00),
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.W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0),
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.Quot(r), .Rem(), .Flags());
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// Counter
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counter counter(clk, req, done);
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initial
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forever
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begin
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clk = 1; #17;
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clk = 0; #16;
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end
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// Read test vectors from disk
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initial
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begin
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testnum = 0;
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errors = 0;
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$readmemh ("testvectors", Tests);
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Vec = Tests[testnum];
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a = Vec[`mema];
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b = Vec[`memb];
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nextr = Vec[`memr];
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req <= #5 1;
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end
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// Apply directed test vectors read from file.
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always @(posedge clk)
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begin
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if (done)
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begin
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req <= #5 1;
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diffp = correctr - r;
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diffn = r - correctr;
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if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
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begin
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errors = errors+1;
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$display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp);
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$display("failed\n");
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$stop;
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end
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if (a === 52'hxxxxxxxxxxxxx)
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begin
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$display("%d Tests completed successfully", testnum);
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$stop;
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end
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end
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if (req)
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begin
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req <= #5 0;
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correctr = nextr;
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testnum = testnum+1;
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Vec = Tests[testnum];
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$display("a = %h b = %h",a,b);
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a = Vec[`mema];
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b = Vec[`memb];
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nextr = Vec[`memr];
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end
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end
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endmodule
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132
pipelined/srt/testbench.sv
Normal file
132
pipelined/srt/testbench.sv
Normal file
@ -0,0 +1,132 @@
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/////////////
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// counter //
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/////////////
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module counter(input logic clk,
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input logic req,
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output logic done);
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logic [5:0] count;
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// This block of control logic sequences the divider
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// through its iterations. You may modify it if you
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// build a divider which completes in fewer iterations.
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// You are not responsible for the (trivial) circuit
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// design of the block.
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always @(posedge clk)
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begin
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if (count == 54) done <= #1 1;
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else if (done | req) done <= #1 0;
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if (req) count <= #1 0;
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else count <= #1 count+1;
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end
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endmodule
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///////////
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// clock //
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///////////
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module clock(clk);
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output clk;
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// Internal clk signal
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logic clk;
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endmodule
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//////////
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// testbench //
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//////////
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module testbench;
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logic clk;
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logic req;
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logic done;
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logic [51:0] a;
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logic [51:0] b;
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logic [51:0] r;
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logic [54:0] rp, rm; // positive quotient digits
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// Test parameters
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parameter MEM_SIZE = 40000;
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parameter MEM_WIDTH = 52+52+52;
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`define memr 51:0
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`define memb 103:52
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`define mema 155:104
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// Test logicisters
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logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
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logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a
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// bit field of an array
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logic [51:0] correctr, nextr, diffn, diffp;
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integer testnum, errors;
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// Divider
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srt #(52) srt(.clk, .Start(req),
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.Stall(1'b0), .Flush(1'b0),
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.SrcXFrac(a), .SrcYFrac(b),
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.SrcA('0), .SrcB('0), .Fmt(2'b00),
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.W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0),
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.Quot(r), .Rem(), .Flags());
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// Counter
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counter counter(clk, req, done);
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initial
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forever
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begin
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clk = 1; #17;
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clk = 0; #16;
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end
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// Read test vectors from disk
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initial
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begin
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testnum = 0;
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errors = 0;
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$readmemh ("testvectors", Tests);
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Vec = Tests[testnum];
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a = Vec[`mema];
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b = Vec[`memb];
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nextr = Vec[`memr];
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req <= #5 1;
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end
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// Apply directed test vectors read from file.
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always @(posedge clk)
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begin
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if (done)
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begin
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req <= #5 1;
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diffp = correctr - r;
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diffn = r - correctr;
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if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
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begin
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errors = errors+1;
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$display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp);
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$display("failed\n");
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$stop;
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end
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if (a === 52'hxxxxxxxxxxxxx)
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begin
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$display("%d Tests completed successfully", testnum);
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$stop;
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end
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end
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if (req)
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begin
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req <= #5 0;
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correctr = nextr;
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testnum = testnum+1;
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Vec = Tests[testnum];
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$display("a = %h b = %h",a,b);
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a = Vec[`mema];
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b = Vec[`memb];
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nextr = Vec[`memr];
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end
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end
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endmodule
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