Ross Thompson 27042f028e Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.		2022-02-16 15:22:19 -06:00
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config	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 14:22:19 -06:00
fpu-testfloat/FMA/tbgen	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	update bugfinder script to new file organization	2022-02-15 22:58:18 +00:00
src	Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.	2022-02-16 15:22:19 -06:00
srt	srt fixes	2022-02-14 18:40:27 +00:00
testbench	added CSR permission and minfor to 32 bit tests	2022-02-15 20:19:14 +00:00