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https://github.com/openhwgroup/cvw
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1st attempt at multiple channel PLIC
This commit is contained in:
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@ -101,10 +101,12 @@ then
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set logging on
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# Priority Levels for sources 1 thru 63
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x/63xw 0x0C000004
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# Interrupt Enables
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# Interrupt Enables for sources 1 thru 63 for contexts 0 and 1
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x/2xw 0x0C020000
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# Global Priority Threshold
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x/2xw 0x0C020080
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# Global Priority Threshold for contexts 0 and 1
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x/1xw 0x0C200000
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x/1xw 0x0C201000
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set logging off
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shell echo \"GDB storing RAM to $rawRamFile\"
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dump binary memory $rawRamFile 0x80000000 0xffffffff
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@ -1,5 +1,6 @@
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#! /usr/bin/python3
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import sys, os
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from functools import reduce
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################
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# Helper Funcs #
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@ -21,6 +22,9 @@ def tokenize(string):
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token = token + char
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return tokens
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def strip0x(num):
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return num[2:]
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def stripZeroes(num):
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num = num.strip('0')
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if num=='':
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@ -42,7 +46,7 @@ if not os.path.exists(rawPlicStateFile):
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sys.exit('Error input file '+rawPlicStateFile+'not found')
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with open(rawPlicStateFile, 'r') as rawPlicStateFile:
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plicIntPriorityArray=[]
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plicIntPriorityArray = [] # iterates over number of different sources
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# 0x0C000004 thru 0x0C000010
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plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
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# 0x0C000014 thru 0x0C000020
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@ -76,20 +80,30 @@ with open(rawPlicStateFile, 'r') as rawPlicStateFile:
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# 0x0C0000f4 thru 0x0C0000fc
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plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
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plicIntEnableArray = [] # iterates over number of different contexts
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# 0x0C020000 thru 0x0C020004
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plicIntEnable = tokenize(rawPlicStateFile.readline())[1:]
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plicIntEnable = map(strip0x,plicIntEnable)
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plicIntEnableArray.append(reduce(lambda x,y: x+y,plicIntEnable))
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# 0x0C020080 thru 0x0C020084
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plicIntEnable = tokenize(rawPlicStateFile.readline())[1:]
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plicIntEnable = map(strip0x,plicIntEnable)
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plicIntEnableArray.append(reduce(lambda x,y: x+y,plicIntEnable))
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plicIntPriorityThresholdArray = [] # iterates over number of different contexts
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# 0x0C200000
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plicIntPriorityThreshold = tokenize(rawPlicStateFile.readline())[1:]
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plicIntPriorityThresholdArray += tokenize(rawPlicStateFile.readline())[1:]
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# 0x0C201000
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plicIntPriorityThresholdArray += tokenize(rawPlicStateFile.readline())[1:]
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with open(outDir+'checkpoint-PLIC_INT_PRIORITY', 'w') as outFile:
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for word in plicIntPriorityArray:
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outFile.write(stripZeroes(word[2:])+'\n')
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with open(outDir+'checkpoint-PLIC_INT_ENABLE', 'w') as outFile:
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for word in plicIntEnable:
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outFile.write(stripZeroes(word[2:]))
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for word in plicIntEnableArray:
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outFile.write(word+'\n')
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with open(outDir+'checkpoint-PLIC_THRESHOLD', 'w') as outFile:
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for word in plicIntPriorityThreshold:
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for word in plicIntPriorityThresholdArray:
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outFile.write(stripZeroes(word[2:])+'\n')
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print("Finished parsing PLIC state!")
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@ -43,13 +43,13 @@ module csr #(parameter
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input logic [31:0] InstrM,
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input logic [`XLEN-1:0] PCM, SrcAM,
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input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM,
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input logic TimerIntM, ExtIntM, SwIntM,
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input logic TimerIntM, ExtIntM, ExtIntS, SwIntM,
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input logic [63:0] MTIME_CLINT,
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input logic InstrValidM, FRegWriteM, LoadStallD,
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input logic BPPredDirWrongM,
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input logic BTBPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic BPPredClassNonCFIWrongM,
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input logic BPPredDirWrongM,
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input logic BTBPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic BPPredClassNonCFIWrongM,
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input logic [4:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheAccess,
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@ -123,7 +123,7 @@ module csr #(parameter
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assign CSRUWriteM = CSRWriteM;
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csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRMWriteM, .CSRSWriteM,
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.CSRAdrM, .ExtIntM, .TimerIntM, .SwIntM,
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.CSRAdrM, .ExtIntM, .ExtIntS, .TimerIntM, .SwIntM,
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.MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM);
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csrsr csrsr(.clk, .reset, .StallW,
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.WriteMSTATUSM, .WriteSSTATUSM,
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@ -167,7 +167,7 @@ module csr #(parameter
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// merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient
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assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 & PrivilegeModeW != `M_MODE) |
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(CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == `U_MODE);
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(CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == `U_MODE);
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assign IllegalCSRAccessM = ((IllegalCSRCAccessM & IllegalCSRMAccessM &
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IllegalCSRSAccessM & IllegalCSRUAccessM |
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InsufficientCSRPrivilegeM) & CSRReadM) | IllegalCSRMWriteReadonlyM;
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@ -41,7 +41,7 @@ module csri #(parameter
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input logic InstrValidNotFlushedM, StallW,
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input logic CSRMWriteM, CSRSWriteM,
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input logic [11:0] CSRAdrM,
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input logic ExtIntM, TimerIntM, SwIntM,
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input logic ExtIntM, ExtIntS, TimerIntM, SwIntM,
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input logic [`XLEN-1:0] MIDELEG_REGW,
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output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
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input logic [`XLEN-1:0] CSRWriteValM
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@ -57,12 +57,12 @@ module csri #(parameter
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always_comb begin
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IntInM = 0;
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IntInM[11] = ExtIntM;; // MEIP
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IntInM[9] = ExtIntM & MIDELEG_REGW[9]; // SEIP
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IntInM[7] = TimerIntM; // MTIP
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IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP
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IntInM[3] = SwIntM; // MSIP
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IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP
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IntInM[11] = ExtIntM; // MEIP
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IntInM[9] = ExtIntS | (ExtIntM & MIDELEG_REGW[9]); // SEIP
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IntInM[7] = TimerIntM; // MTIP
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IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP
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IntInM[3] = SwIntM; // MSIP
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IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP
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end
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// Interrupt Write Enables
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@ -82,21 +82,19 @@ module csri #(parameter
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assign MIP_WRITE_MASK = 12'h000;
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assign SIP_WRITE_MASK = 12'h000;
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end
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always @(posedge clk) //, posedge reset) begin // *** I strongly feel that IntInM should go directly to IP_REGW -- Ben 9/7/21
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always @(posedge clk)
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if (reset) IP_REGW_writeable <= 10'b0;
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else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable
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else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable
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// else if (WriteUIPM) IP_REGW = (CSRWriteValM & 12'hBBB) | (NextIPM & 12'h080); // MTIP unclearable
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else IP_REGW_writeable <= IP_REGW_writeable | IntInM[9:0]; // *** check this turns off interrupts properly even when MIDELEG changes
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always @(posedge clk) //, posedge reset) begin
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else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | {1'b0,IntInM[8:0]}; // MTIP unclearable
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else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | {1'b0,IntInM[8:0]}; // MTIP unclearable
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else IP_REGW_writeable <= IP_REGW_writeable | {1'b0, IntInM[8:0]}; // *** check this turns off interrupts properly even when MIDELEG changes
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always @(posedge clk)
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if (reset) IE_REGW <= 12'b0;
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else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'hAAA); // MIE controls M and S fields
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else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields
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// else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field
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// restricted views of registers
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// Add MEIP read-only signal
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assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable};
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// Add ExtIntM read-only signal
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assign IP_REGW = {ExtIntM,1'b0,ExtIntS,9'b0} | {2'b0,IP_REGW_writeable};
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// Machine Mode
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assign MIP_REGW = IP_REGW;
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@ -55,7 +55,7 @@ module privileged (
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input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD,
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input logic LoadMisalignedFaultM,
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input logic StoreAmoMisalignedFaultM,
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input logic TimerIntM, ExtIntM, SwIntM,
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input logic TimerIntM, ExtIntM, ExtIntS, SwIntM,
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input logic [63:0] MTIME_CLINT,
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input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
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input logic [4:0] SetFflagsM,
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@ -150,7 +150,7 @@ module privileged (
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.StallE, .StallM, .StallW,
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.InstrM, .PCM, .SrcAM,
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.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM,
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.TimerIntM, .ExtIntM, .SwIntM,
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.TimerIntM, .ExtIntM, .ExtIntS, .SwIntM,
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.MTIME_CLINT,
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.InstrValidM, .FRegWriteM, .LoadStallD,
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
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@ -37,6 +37,15 @@
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`include "wally-config.vh"
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`define N `PLIC_NUM_SRC
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// number of interrupt sources
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// does not include source 0, which does not connect to anything according to spec
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// up to 63 sources supported; *** in the future, allow up to 1023 sources
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`define C 2
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// number of conexts
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// hardcoded to 2 contexts for now; *** later upgrade to arbitrary (up to 15872) contexts
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module plic (
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input logic HCLK, HRESETn,
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input logic HSELPLIC,
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@ -48,25 +57,26 @@ module plic (
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input logic UARTIntr,GPIOIntr,
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output logic [`XLEN-1:0] HREADPLIC,
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output logic HRESPPLIC, HREADYPLIC,
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output logic ExtIntM);
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localparam N=`PLIC_NUM_SRC; // should not exceed 63; does not inlcude source 0, which does not connect to anything according to spec
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output logic ExtIntM, ExtIntS);
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logic memwrite, memread, initTrans;
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logic [23:0] entry, entryd;
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logic [31:0] Din, Dout;
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logic [N:1] requests;
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logic [2:0] intPriority[N:1];
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logic [2:0] intThreshold;
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logic [N:1] intPending, nextIntPending, intEn, intInProgress;
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logic [5:0] intClaim; // ID's are 6 bits if we stay within 63 sources
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logic [N:1] pendingArray[7:1];
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logic [7:1] pendingPGrouped;
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logic [7:1] pendingMaxP;
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logic [N:1] pendingRequestsAtMaxP;
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logic [7:1] threshMask;
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// context-independent signals
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logic [`N:1] requests;
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logic [`N:1][2:0] intPriority;
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logic [`N:1] intInProgress, intPending, nextIntPending;
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// context-dependent signals
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logic [`C-1:0][2:0] intThreshold;
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logic [`C-1:0][`N:1] intEn;
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logic [`C-1:0][5:0] intClaim; // ID's are 6 bits if we stay within 63 sources
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logic [`C-1:0][7:1][`N:1] irqMatrix;
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logic [`C-1:0][7:1] priorities_with_irqs;
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logic [`C-1:0][7:1] max_priority_with_irqs;
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logic [`C-1:0][`N:1] irqs_at_max_priority;
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logic [`C-1:0][7:1] threshMask;
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// =======
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// AHB I/O
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@ -82,12 +92,12 @@ module plic (
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// account for subword read/write circuitry
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// -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
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if (`XLEN == 64) begin
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if (`XLEN == 64) begin
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assign Din = entryd[2] ? HWDATA[63:32] : HWDATA[31:0];
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assign HREADPLIC = entryd[2] ? {Dout,32'b0} : {32'b0,Dout};
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end else begin // 32-bit
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assign Din = HWDATA[31:0];
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assign HREADPLIC = Dout;
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assign Din = HWDATA[31:0];
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end
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// ==================
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@ -96,43 +106,56 @@ module plic (
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always @(posedge HCLK,negedge HRESETn) begin
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// resetting
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if (~HRESETn) begin
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intPriority <= #1 '{default:3'b0};
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intEn <= #1 {N{1'b0}};
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intThreshold <= #1 3'b0;
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intInProgress <= #1 {N{1'b0}};
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intPriority <= #1 {`N{3'b0}};
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intEn <= #1 {2{`N'b0}};
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intThreshold <= #1 {2{3'b0}};
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intInProgress <= #1 `N'b0;
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// writing
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end else begin
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if (memwrite)
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casez(entryd)
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24'h0000??: intPriority[entryd[7:2]] <= #1 Din[2:0];
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`ifdef PLIC_NUM_SRC_LT_32
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24'h002000: intEn[N:1] <= #1 Din[N:1];
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`ifdef PLIC_NUM_SRC_LT_32 // *** switch to a generate for loop so as to deprecate PLIC_NUM_SRC_LT_32 and allow up to 1023 sources
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24'h002000: intEn[0][`N:1] <= #1 Din[`N:1];
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24'h002080: intEn[1][`N:1] <= #1 Din[`N:1];
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`endif
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`ifndef PLIC_NUM_SRC_LT_32
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24'h002000: intEn[31:1] <= #1 Din[31:1];
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24'h002004: intEn[N:32] <= #1 Din[31:0];
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24'h002000: intEn[0][31:1] <= #1 Din[31:1];
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24'h002004: intEn[0][`N:32] <= #1 Din[31:0];
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24'h002080: intEn[1][31:1] <= #1 Din[31:1];
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24'h002084: intEn[1][`N:32] <= #1 Din[31:0];
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`endif
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24'h200000: intThreshold[2:0] <= #1 Din[2:0];
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24'h200004: intInProgress <= #1 intInProgress & ~(`PLIC_NUM_SRC'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion
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24'h200000: intThreshold[0] <= #1 Din[2:0];
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24'h200004: intInProgress <= #1 intInProgress & ~(`N'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion
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24'h201000: intThreshold[1] <= #1 Din[2:0];
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24'h201004: intInProgress <= #1 intInProgress & ~(`N'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion
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endcase
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// reading
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if (memread)
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casez(entry)
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24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]};
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`ifdef PLIC_NUM_SRC_LT_32
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24'h001000: Dout <= #1 {{(31-N){1'b0}},intPending[N:1],1'b0};
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24'h002000: Dout <= #1 {{(31-N){1'b0}},intEn[N:1],1'b0};
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24'h001000: Dout <= #1 {{(31-`N){1'b0}},intPending,1'b0};
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24'h002000: Dout <= #1 {{(31-`N){1'b0}},intEn[0],1'b0};
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24'h002080: Dout <= #1 {{(31-`N){1'b0}},intEn[1],1'b0};
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`endif
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`ifndef PLIC_NUM_SRC_LT_32
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24'h001000: Dout <= #1 {intPending[31:1],1'b0};
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24'h001004: Dout <= #1 {{(63-N){1'b0}},intPending[N:32]};
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24'h002000: Dout <= #1 {intEn[31:1],1'b0};
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24'h002004: Dout <= #1 {{(63-N){1'b0}},intEn[N:32]};
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24'h001004: Dout <= #1 {{(63-`N){1'b0}},intPending[`N:32]};
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24'h002000: Dout <= #1 {intEn[0][31:1],1'b0};
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24'h002004: Dout <= #1 {{(63-`N){1'b0}},intEn[0][`N:32]};
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24'h002080: Dout <= #1 {intEn[0][31:1],1'b0};
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24'h002084: Dout <= #1 {{(63-`N){1'b0}},intEn[1][`N:32]};
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`endif
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24'h200000: Dout <= #1 {29'b0,intThreshold[2:0]};
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24'h200000: Dout <= #1 {29'b0,intThreshold[0]};
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24'h200004: begin
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Dout <= #1 {26'b0,intClaim};
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intInProgress <= #1 intInProgress | (`PLIC_NUM_SRC'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed
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Dout <= #1 {26'b0,intClaim[0]};
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intInProgress <= #1 intInProgress | (`N'b1 << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed
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end
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24'h201000: Dout <= #1 {29'b0,intThreshold[1]};
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24'h201004: begin
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Dout <= #1 {26'b0,intClaim[1]};
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intInProgress <= #1 intInProgress | (`N'b1 << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed
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end
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||||
default: Dout <= #1 32'h0; // invalid access
|
||||
endcase
|
||||
@ -143,7 +166,7 @@ module plic (
|
||||
|
||||
// connect sources to requests
|
||||
always_comb begin
|
||||
requests = {N{1'b0}};
|
||||
requests = `N'b0;
|
||||
`ifdef PLIC_GPIO_ID
|
||||
requests[`PLIC_GPIO_ID] = GPIOIntr;
|
||||
`endif
|
||||
@ -152,66 +175,88 @@ module plic (
|
||||
`endif
|
||||
end
|
||||
|
||||
// pending updates
|
||||
// *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered)
|
||||
assign nextIntPending = (intPending | (requests & ~intInProgress)) & // requests should raise intPending except when their service routine is already in progress
|
||||
~({N{((entry == 24'h200004) & memread)}} << (intClaim-1)); // clear pending bit when claim register is read
|
||||
flopr #(N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
|
||||
// pending interrupt requests
|
||||
assign nextIntPending =
|
||||
(intPending | // existing pending requests
|
||||
(requests & ~intInProgress)) & // assert new requests (if they aren't already being serviced)
|
||||
~({`N{((entry == 24'h200004) & memread)}} << (intClaim[0]-1)) & // deassert requests that just completed
|
||||
~({`N{((entry == 24'h201004) & memread)}} << (intClaim[1]-1));
|
||||
flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
|
||||
|
||||
// pending array - indexed by priority_lvl x source_ID
|
||||
genvar i, j;
|
||||
for (j=1; j<=7; j++) begin: pending
|
||||
for (i=1; i<=N; i=i+1) begin: pendingbit
|
||||
assign pendingArray[j][i] = (intPriority[i]==j) & intEn[i] & intPending[i];
|
||||
// context-dependent signals
|
||||
genvar ctx;
|
||||
for (ctx=0; ctx<`C; ctx++) begin
|
||||
// request matrix
|
||||
// priority level (rows) X source ID (columns)
|
||||
//
|
||||
// irqMatrix[ctx][pri][src] is high if source <src>
|
||||
// has priority level <pri> and has an "active" interrupt request
|
||||
// ("active" meaning it is enabled in context <ctx> and is pending)
|
||||
genvar src, pri;
|
||||
for (pri=1; pri<=7; pri++) begin
|
||||
for (src=1; src<=`N; src++) begin
|
||||
assign irqMatrix[ctx][pri][src] = (intPriority[src]==pri) & intPending[src] & intEn[ctx][src];
|
||||
end
|
||||
end
|
||||
end
|
||||
// pending array, except grouped by priority
|
||||
assign pendingPGrouped[7:1] = {|pendingArray[7],
|
||||
|pendingArray[6],
|
||||
|pendingArray[5],
|
||||
|pendingArray[4],
|
||||
|pendingArray[3],
|
||||
|pendingArray[2],
|
||||
|pendingArray[1]};
|
||||
//assign pendingPGrouped = pendingArray.or;
|
||||
|
||||
// pendingPGrouped, except only topmost priority is active
|
||||
assign pendingMaxP[7:1] = {pendingPGrouped[7],
|
||||
pendingPGrouped[6] & ~|pendingPGrouped[7],
|
||||
pendingPGrouped[5] & ~|pendingPGrouped[7:6],
|
||||
pendingPGrouped[4] & ~|pendingPGrouped[7:5],
|
||||
pendingPGrouped[3] & ~|pendingPGrouped[7:4],
|
||||
pendingPGrouped[2] & ~|pendingPGrouped[7:3],
|
||||
pendingPGrouped[1] & ~|pendingPGrouped[7:2]};
|
||||
// select the pending requests at that priority
|
||||
assign pendingRequestsAtMaxP[N:1] = ({N{pendingMaxP[7]}} & pendingArray[7])
|
||||
| ({N{pendingMaxP[6]}} & pendingArray[6])
|
||||
| ({N{pendingMaxP[5]}} & pendingArray[5])
|
||||
| ({N{pendingMaxP[4]}} & pendingArray[4])
|
||||
| ({N{pendingMaxP[3]}} & pendingArray[3])
|
||||
| ({N{pendingMaxP[2]}} & pendingArray[2])
|
||||
| ({N{pendingMaxP[1]}} & pendingArray[1]);
|
||||
// find the lowest ID amongst active interrupts at the highest priority
|
||||
logic [5:0] k;
|
||||
always_comb begin
|
||||
intClaim = 6'b0;
|
||||
for (k=N; k>0; k=k-1) begin
|
||||
if (pendingRequestsAtMaxP[k]) intClaim = k;
|
||||
// which prority levels have one or more active requests?
|
||||
assign priorities_with_irqs[ctx][7:1] = {
|
||||
|irqMatrix[ctx][7],
|
||||
|irqMatrix[ctx][6],
|
||||
|irqMatrix[ctx][5],
|
||||
|irqMatrix[ctx][4],
|
||||
|irqMatrix[ctx][3],
|
||||
|irqMatrix[ctx][2],
|
||||
|irqMatrix[ctx][1]
|
||||
};
|
||||
|
||||
// get the highest priority level that has active requests
|
||||
assign max_priority_with_irqs[ctx][7:1] = {
|
||||
priorities_with_irqs[ctx][7],
|
||||
priorities_with_irqs[ctx][6] & ~|priorities_with_irqs[ctx][7],
|
||||
priorities_with_irqs[ctx][5] & ~|priorities_with_irqs[ctx][7:6],
|
||||
priorities_with_irqs[ctx][4] & ~|priorities_with_irqs[ctx][7:5],
|
||||
priorities_with_irqs[ctx][3] & ~|priorities_with_irqs[ctx][7:4],
|
||||
priorities_with_irqs[ctx][2] & ~|priorities_with_irqs[ctx][7:3],
|
||||
priorities_with_irqs[ctx][1] & ~|priorities_with_irqs[ctx][7:2]
|
||||
};
|
||||
|
||||
// of the sources at the highest priority level that has active requests,
|
||||
// which sources have active requests?
|
||||
assign irqs_at_max_priority[ctx][`N:1] =
|
||||
({`N{max_priority_with_irqs[ctx][7]}} & irqMatrix[ctx][7]) |
|
||||
({`N{max_priority_with_irqs[ctx][6]}} & irqMatrix[ctx][6]) |
|
||||
({`N{max_priority_with_irqs[ctx][5]}} & irqMatrix[ctx][5]) |
|
||||
({`N{max_priority_with_irqs[ctx][4]}} & irqMatrix[ctx][4]) |
|
||||
({`N{max_priority_with_irqs[ctx][3]}} & irqMatrix[ctx][3]) |
|
||||
({`N{max_priority_with_irqs[ctx][2]}} & irqMatrix[ctx][2]) |
|
||||
({`N{max_priority_with_irqs[ctx][1]}} & irqMatrix[ctx][1]);
|
||||
|
||||
// of the sources at the highest priority level that has active requests,
|
||||
// choose the source with the lowest source ID to be the most urgent
|
||||
// and set intClaim to the source ID of the most urgent active request
|
||||
integer k;
|
||||
always_comb begin
|
||||
intClaim[ctx] = 6'b0;
|
||||
for (k=`N; k>0; k--) begin
|
||||
if (irqs_at_max_priority[ctx][k]) intClaim[ctx] = k[5:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// create threshold mask
|
||||
always_comb begin
|
||||
threshMask[7] = (intThreshold != 7);
|
||||
threshMask[6] = (intThreshold != 6) & threshMask[7];
|
||||
threshMask[5] = (intThreshold != 5) & threshMask[6];
|
||||
threshMask[4] = (intThreshold != 4) & threshMask[5];
|
||||
threshMask[3] = (intThreshold != 3) & threshMask[4];
|
||||
threshMask[2] = (intThreshold != 2) & threshMask[3];
|
||||
threshMask[1] = (intThreshold != 1) & threshMask[2];
|
||||
end
|
||||
// is the max priority > threshold?
|
||||
// *** would it be any better to first priority encode maxPriority into binary and then ">" with threshold?
|
||||
assign ExtIntM = |(threshMask & pendingPGrouped);
|
||||
|
||||
// create threshold mask
|
||||
always_comb begin
|
||||
threshMask[ctx][7] = (intThreshold[ctx] != 7);
|
||||
threshMask[ctx][6] = (intThreshold[ctx] != 6) & threshMask[ctx][7];
|
||||
threshMask[ctx][5] = (intThreshold[ctx] != 5) & threshMask[ctx][6];
|
||||
threshMask[ctx][4] = (intThreshold[ctx] != 4) & threshMask[ctx][5];
|
||||
threshMask[ctx][3] = (intThreshold[ctx] != 3) & threshMask[ctx][4];
|
||||
threshMask[ctx][2] = (intThreshold[ctx] != 2) & threshMask[ctx][3];
|
||||
threshMask[ctx][1] = (intThreshold[ctx] != 1) & threshMask[ctx][2];
|
||||
end
|
||||
// is the max priority > threshold?
|
||||
// *** would it be any better to first priority encode maxPriority into binary and then ">" with threshold?
|
||||
end
|
||||
assign ExtIntM = |(threshMask[0] & priorities_with_irqs[0]);
|
||||
assign ExtIntS = |(threshMask[1] & priorities_with_irqs[1]);
|
||||
endmodule
|
||||
|
||||
|
||||
@ -55,7 +55,7 @@ module uncore (
|
||||
input logic [3:0] HSIZED,
|
||||
input logic HWRITED,
|
||||
// peripheral pins
|
||||
output logic TimerIntM, SwIntM, ExtIntM,
|
||||
output logic TimerIntM, SwIntM, ExtIntM, ExtIntS,
|
||||
input logic [31:0] GPIOPinsIn,
|
||||
output logic [31:0] GPIOPinsOut, GPIOPinsEn,
|
||||
input logic UARTSin,
|
||||
@ -133,9 +133,10 @@ module uncore (
|
||||
.HWRITE, .HREADY, .HTRANS, .HWDATA,
|
||||
.UARTIntr, .GPIOIntr,
|
||||
.HREADPLIC, .HRESPPLIC, .HREADYPLIC,
|
||||
.ExtIntM);
|
||||
.ExtIntM, .ExtIntS);
|
||||
end else begin : plic
|
||||
assign ExtIntM = 0;
|
||||
assign ExtIntS = 0;
|
||||
end
|
||||
if (`GPIO_SUPPORTED == 1) begin : gpio
|
||||
gpio gpio(
|
||||
|
||||
@ -32,137 +32,137 @@
|
||||
/* verilator lint_on UNUSED */
|
||||
|
||||
module wallypipelinedcore (
|
||||
input logic clk, reset,
|
||||
input logic clk, reset,
|
||||
// Privileged
|
||||
input logic TimerIntM, ExtIntM, SwIntM,
|
||||
input logic [63:0] MTIME_CLINT,
|
||||
input logic TimerIntM, ExtIntM, ExtIntS, SwIntM,
|
||||
input logic [63:0] MTIME_CLINT,
|
||||
// Bus Interface
|
||||
input logic [`AHBW-1:0] HRDATA,
|
||||
input logic HREADY, HRESP,
|
||||
output logic HCLK, HRESETn,
|
||||
output logic [31:0] HADDR,
|
||||
input logic HREADY, HRESP,
|
||||
output logic HCLK, HRESETn,
|
||||
output logic [31:0] HADDR,
|
||||
output logic [`AHBW-1:0] HWDATA,
|
||||
output logic HWRITE,
|
||||
output logic [2:0] HSIZE,
|
||||
output logic [2:0] HBURST,
|
||||
output logic [3:0] HPROT,
|
||||
output logic [1:0] HTRANS,
|
||||
output logic HMASTLOCK,
|
||||
output logic HWRITE,
|
||||
output logic [2:0] HSIZE,
|
||||
output logic [2:0] HBURST,
|
||||
output logic [3:0] HPROT,
|
||||
output logic [1:0] HTRANS,
|
||||
output logic HMASTLOCK,
|
||||
// Delayed signals for subword write
|
||||
output logic [2:0] HADDRD,
|
||||
output logic [3:0] HSIZED,
|
||||
output logic HWRITED
|
||||
output logic [2:0] HADDRD,
|
||||
output logic [3:0] HSIZED,
|
||||
output logic HWRITED
|
||||
);
|
||||
|
||||
// logic [1:0] ForwardAE, ForwardBE;
|
||||
logic StallF, StallD, StallE, StallM, StallW;
|
||||
logic FlushF, FlushD, FlushE, FlushM, FlushW;
|
||||
logic RetM;
|
||||
logic StallF, StallD, StallE, StallM, StallW;
|
||||
logic FlushF, FlushD, FlushE, FlushM, FlushW;
|
||||
logic RetM;
|
||||
(* mark_debug = "true" *) logic TrapM;
|
||||
|
||||
// new signals that must connect through DP
|
||||
logic MDUE, W64E;
|
||||
logic CSRReadM, CSRWriteM, PrivilegedM;
|
||||
logic [1:0] AtomicE;
|
||||
logic [1:0] AtomicM;
|
||||
logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE;
|
||||
logic [`XLEN-1:0] SrcAM;
|
||||
logic [2:0] Funct3E;
|
||||
logic MDUE, W64E;
|
||||
logic CSRReadM, CSRWriteM, PrivilegedM;
|
||||
logic [1:0] AtomicE;
|
||||
logic [1:0] AtomicM;
|
||||
logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE;
|
||||
logic [`XLEN-1:0] SrcAM;
|
||||
logic [2:0] Funct3E;
|
||||
// logic [31:0] InstrF;
|
||||
logic [31:0] InstrD, InstrW;
|
||||
(* mark_debug = "true" *) logic [31:0] InstrM;
|
||||
logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] PCM;
|
||||
logic [`XLEN-1:0] CSRReadValW, MDUResultW;
|
||||
logic [`XLEN-1:0] PrivilegedNextPCM;
|
||||
(* mark_debug = "true" *) logic [1:0] MemRWM;
|
||||
(* mark_debug = "true" *) logic InstrValidM;
|
||||
logic InstrMisalignedFaultM;
|
||||
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
|
||||
logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
|
||||
logic LoadMisalignedFaultM, LoadAccessFaultM;
|
||||
logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
|
||||
logic [`XLEN-1:0] InstrMisalignedAdrM;
|
||||
logic [31:0] InstrD, InstrW;
|
||||
(* mark_debug = "true" *) logic [31:0] InstrM;
|
||||
logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] PCM;
|
||||
logic [`XLEN-1:0] CSRReadValW, MDUResultW;
|
||||
logic [`XLEN-1:0] PrivilegedNextPCM;
|
||||
(* mark_debug = "true" *) logic [1:0] MemRWM;
|
||||
(* mark_debug = "true" *) logic InstrValidM;
|
||||
logic InstrMisalignedFaultM;
|
||||
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
|
||||
logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
|
||||
logic LoadMisalignedFaultM, LoadAccessFaultM;
|
||||
logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
|
||||
logic [`XLEN-1:0] InstrMisalignedAdrM;
|
||||
logic InvalidateICacheM, FlushDCacheM;
|
||||
logic PCSrcE;
|
||||
logic CSRWritePendingDEM;
|
||||
logic DivBusyE;
|
||||
logic PCSrcE;
|
||||
logic CSRWritePendingDEM;
|
||||
logic DivBusyE;
|
||||
logic DivE;
|
||||
logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
|
||||
logic SquashSCW;
|
||||
logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
|
||||
logic SquashSCW;
|
||||
// floating point unit signals
|
||||
logic [2:0] FRM_REGW;
|
||||
logic [2:0] FRM_REGW;
|
||||
logic [4:0] RdM, RdW;
|
||||
logic FStallD;
|
||||
logic FWriteIntE;
|
||||
logic [`XLEN-1:0] FWriteDataE;
|
||||
logic [`XLEN-1:0] FIntResM;
|
||||
logic FDivBusyE;
|
||||
logic IllegalFPUInstrD, IllegalFPUInstrE;
|
||||
logic FRegWriteM;
|
||||
logic FPUStallD;
|
||||
logic [4:0] SetFflagsM;
|
||||
logic FStallD;
|
||||
logic FWriteIntE;
|
||||
logic [`XLEN-1:0] FWriteDataE;
|
||||
logic [`XLEN-1:0] FIntResM;
|
||||
logic FDivBusyE;
|
||||
logic IllegalFPUInstrD, IllegalFPUInstrE;
|
||||
logic FRegWriteM;
|
||||
logic FPUStallD;
|
||||
logic [4:0] SetFflagsM;
|
||||
|
||||
// memory management unit signals
|
||||
logic ITLBWriteF;
|
||||
logic ITLBFlushF, DTLBFlushM;
|
||||
logic ITLBMissF;
|
||||
logic [`XLEN-1:0] SATP_REGW;
|
||||
logic ITLBWriteF;
|
||||
logic ITLBFlushF, DTLBFlushM;
|
||||
logic ITLBMissF;
|
||||
logic [`XLEN-1:0] SATP_REGW;
|
||||
logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
|
||||
logic [1:0] STATUS_MPP;
|
||||
logic [1:0] PrivilegeModeW;
|
||||
logic [`XLEN-1:0] PTE;
|
||||
logic [1:0] PageType;
|
||||
logic [1:0] PrivilegeModeW;
|
||||
logic [`XLEN-1:0] PTE;
|
||||
logic [1:0] PageType;
|
||||
|
||||
// PMA checker signals
|
||||
var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
|
||||
var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
|
||||
|
||||
// IMem stalls
|
||||
logic IFUStallF;
|
||||
logic LSUStallM;
|
||||
logic IFUStallF;
|
||||
logic LSUStallM;
|
||||
|
||||
|
||||
|
||||
// cpu lsu interface
|
||||
logic [2:0] Funct3M;
|
||||
logic [`XLEN-1:0] IEUAdrE;
|
||||
logic [2:0] Funct3M;
|
||||
logic [`XLEN-1:0] IEUAdrE;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM;
|
||||
logic [`XLEN-1:0] ReadDataW;
|
||||
logic CommittedM;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM;
|
||||
logic [`XLEN-1:0] ReadDataW;
|
||||
logic CommittedM;
|
||||
|
||||
// AHB ifu interface
|
||||
logic [`PA_BITS-1:0] IFUBusAdr;
|
||||
logic [`XLEN-1:0] IFUBusHRDATA;
|
||||
logic IFUBusRead;
|
||||
logic IFUBusAck;
|
||||
logic [`PA_BITS-1:0] IFUBusAdr;
|
||||
logic [`XLEN-1:0] IFUBusHRDATA;
|
||||
logic IFUBusRead;
|
||||
logic IFUBusAck;
|
||||
|
||||
// AHB LSU interface
|
||||
logic [`PA_BITS-1:0] LSUBusAdr;
|
||||
logic LSUBusRead;
|
||||
logic LSUBusWrite;
|
||||
logic LSUBusAck;
|
||||
logic [`XLEN-1:0] LSUBusHRDATA;
|
||||
logic [`XLEN-1:0] LSUBusHWDATA;
|
||||
logic [`PA_BITS-1:0] LSUBusAdr;
|
||||
logic LSUBusRead;
|
||||
logic LSUBusWrite;
|
||||
logic LSUBusAck;
|
||||
logic [`XLEN-1:0] LSUBusHRDATA;
|
||||
logic [`XLEN-1:0] LSUBusHWDATA;
|
||||
|
||||
logic BPPredWrongE;
|
||||
logic BPPredDirWrongM;
|
||||
logic BTBPredPCWrongM;
|
||||
logic RASPredPCWrongM;
|
||||
logic BPPredClassNonCFIWrongM;
|
||||
logic [4:0] InstrClassM;
|
||||
logic InstrAccessFaultF;
|
||||
logic [2:0] LSUBusSize;
|
||||
logic BPPredWrongE;
|
||||
logic BPPredDirWrongM;
|
||||
logic BTBPredPCWrongM;
|
||||
logic RASPredPCWrongM;
|
||||
logic BPPredClassNonCFIWrongM;
|
||||
logic [4:0] InstrClassM;
|
||||
logic InstrAccessFaultF;
|
||||
logic [2:0] LSUBusSize;
|
||||
|
||||
logic ExceptionM;
|
||||
logic PendingInterruptM;
|
||||
logic DCacheMiss;
|
||||
logic DCacheAccess;
|
||||
logic ICacheMiss;
|
||||
logic ICacheAccess;
|
||||
logic BreakpointFaultM, EcallFaultM;
|
||||
logic ExceptionM;
|
||||
logic PendingInterruptM;
|
||||
logic DCacheMiss;
|
||||
logic DCacheAccess;
|
||||
logic ICacheMiss;
|
||||
logic ICacheAccess;
|
||||
logic BreakpointFaultM, EcallFaultM;
|
||||
logic InstrDAPageFaultF;
|
||||
|
||||
ifu ifu(
|
||||
@ -203,8 +203,8 @@ module wallypipelinedcore (
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.InstrAccessFaultF,
|
||||
.InstrDAPageFaultF
|
||||
|
||||
); // instruction fetch unit: PC, branch prediction, instruction cache
|
||||
|
||||
); // instruction fetch unit: PC, branch prediction, instruction cache
|
||||
|
||||
ieu ieu(
|
||||
.clk, .reset,
|
||||
@ -221,7 +221,7 @@ module wallypipelinedcore (
|
||||
// Memory stage interface
|
||||
.SquashSCW, // from LSU
|
||||
.MemRWM, // read/write control goes to LSU
|
||||
.AtomicE, // atomic control goes to LSU
|
||||
.AtomicE, // atomic control goes to LSU
|
||||
.AtomicM, // atomic control goes to LSU
|
||||
.WriteDataM, // Write data to LSU
|
||||
.Funct3M, // size and signedness to LSU
|
||||
@ -245,41 +245,41 @@ module wallypipelinedcore (
|
||||
|
||||
lsu lsu(
|
||||
.clk, .reset, .StallM, .FlushM, .StallW,
|
||||
.FlushW,
|
||||
// CPU interface
|
||||
.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
|
||||
.AtomicM, .TrapM,
|
||||
.CommittedM, .DCacheMiss, .DCacheAccess,
|
||||
.SquashSCW,
|
||||
//.DataMisalignedM(DataMisalignedM),
|
||||
.IEUAdrE, .IEUAdrM, .WriteDataM,
|
||||
.ReadDataM, .FlushDCacheM,
|
||||
// connected to ahb (all stay the same)
|
||||
.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck,
|
||||
.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize,
|
||||
.FlushW,
|
||||
// CPU interface
|
||||
.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
|
||||
.AtomicM, .TrapM,
|
||||
.CommittedM, .DCacheMiss, .DCacheAccess,
|
||||
.SquashSCW,
|
||||
//.DataMisalignedM(DataMisalignedM),
|
||||
.IEUAdrE, .IEUAdrM, .WriteDataM,
|
||||
.ReadDataM, .FlushDCacheM,
|
||||
// connected to ahb (all stay the same)
|
||||
.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck,
|
||||
.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize,
|
||||
|
||||
// connect to csr or privilege and stay the same.
|
||||
.PrivilegeModeW, // connects to csr
|
||||
.PMPCFG_ARRAY_REGW, // connects to csr
|
||||
.PMPADDR_ARRAY_REGW, // connects to csr
|
||||
// hptw keep i/o
|
||||
.SATP_REGW, // from csr
|
||||
.STATUS_MXR, // from csr
|
||||
.STATUS_SUM, // from csr
|
||||
.STATUS_MPRV, // from csr
|
||||
.STATUS_MPP, // from csr
|
||||
// connect to csr or privilege and stay the same.
|
||||
.PrivilegeModeW, // connects to csr
|
||||
.PMPCFG_ARRAY_REGW, // connects to csr
|
||||
.PMPADDR_ARRAY_REGW, // connects to csr
|
||||
// hptw keep i/o
|
||||
.SATP_REGW, // from csr
|
||||
.STATUS_MXR, // from csr
|
||||
.STATUS_SUM, // from csr
|
||||
.STATUS_MPRV, // from csr
|
||||
.STATUS_MPP, // from csr
|
||||
|
||||
.DTLBFlushM, // connects to privilege
|
||||
.LoadPageFaultM, // connects to privilege
|
||||
.StoreAmoPageFaultM, // connects to privilege
|
||||
.LoadMisalignedFaultM, // connects to privilege
|
||||
.LoadAccessFaultM, // connects to privilege
|
||||
.StoreAmoMisalignedFaultM, // connects to privilege
|
||||
.StoreAmoAccessFaultM, // connects to privilege
|
||||
.DTLBFlushM, // connects to privilege
|
||||
.LoadPageFaultM, // connects to privilege
|
||||
.StoreAmoPageFaultM, // connects to privilege
|
||||
.LoadMisalignedFaultM, // connects to privilege
|
||||
.LoadAccessFaultM, // connects to privilege
|
||||
.StoreAmoMisalignedFaultM, // connects to privilege
|
||||
.StoreAmoAccessFaultM, // connects to privilege
|
||||
.InstrDAPageFaultF,
|
||||
|
||||
.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF,
|
||||
.LSUStallM); // change to LSUStallM
|
||||
.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF,
|
||||
.LSUStallM); // change to LSUStallM
|
||||
|
||||
|
||||
// *** Ross: please make EBU conditional when only supporting internal memories
|
||||
@ -306,13 +306,13 @@ module wallypipelinedcore (
|
||||
.LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
|
||||
.LSUStallM, .IFUStallF,
|
||||
.FPUStallD, .FStallD,
|
||||
.DivBusyE, .FDivBusyE,
|
||||
.EcallFaultM, .BreakpointFaultM,
|
||||
.DivBusyE, .FDivBusyE,
|
||||
.EcallFaultM, .BreakpointFaultM,
|
||||
.InvalidateICacheM,
|
||||
// Stall & flush outputs
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW,
|
||||
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW
|
||||
); // global stall and flush control
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW,
|
||||
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW
|
||||
); // global stall and flush control
|
||||
|
||||
if (`ZICSR_SUPPORTED) begin:priv
|
||||
privileged priv(
|
||||
@ -331,7 +331,7 @@ module wallypipelinedcore (
|
||||
.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
|
||||
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
|
||||
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
|
||||
.TimerIntM, .ExtIntM, .SwIntM,
|
||||
.TimerIntM, .ExtIntM, .ExtIntS, .SwIntM,
|
||||
.MTIME_CLINT,
|
||||
.InstrMisalignedAdrM, .IEUAdrM,
|
||||
.SetFflagsM,
|
||||
|
||||
@ -74,7 +74,7 @@ module wallypipelinedsoc (
|
||||
logic HRESP;
|
||||
logic TimerIntM, SwIntM; // from CLINT
|
||||
logic [63:0] MTIME_CLINT; // from CLINT to CSRs
|
||||
logic ExtIntM; // from PLIC
|
||||
logic ExtIntM,ExtIntS; // from PLIC
|
||||
logic [2:0] HADDRD;
|
||||
logic [3:0] HSIZED;
|
||||
logic HWRITED;
|
||||
@ -84,7 +84,7 @@ module wallypipelinedsoc (
|
||||
|
||||
// instantiate processor and memories
|
||||
wallypipelinedcore core(.clk, .reset,
|
||||
.TimerIntM, .ExtIntM, .SwIntM,
|
||||
.TimerIntM, .ExtIntM, .ExtIntS, .SwIntM,
|
||||
.MTIME_CLINT,
|
||||
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,
|
||||
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
|
||||
@ -94,7 +94,7 @@ module wallypipelinedsoc (
|
||||
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
|
||||
.HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
|
||||
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,
|
||||
.TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT,
|
||||
.TimerIntM, .SwIntM, .ExtIntM, .ExtIntS, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT,
|
||||
.HSELEXT,
|
||||
.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK
|
||||
|
||||
|
||||
@ -334,8 +334,8 @@ module testbench;
|
||||
//`INIT_CHECKPOINT_VAL(UART_MSR, [7:0]);
|
||||
`INIT_CHECKPOINT_VAL(UART_SCR, [7:0]);
|
||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1);
|
||||
`INIT_CHECKPOINT_VAL(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1]);
|
||||
`INIT_CHECKPOINT_VAL(PLIC_THRESHOLD, [2:0]);
|
||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1],1,0);
|
||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_THRESHOLD, [2:0],1,0);
|
||||
|
||||
integer memFile;
|
||||
integer readResult;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user