Jordan Carlin
6f7a802b86
Merge branch 'main' of https://github.com/openhwgroup/cvw into fround_fixes
2024-05-26 14:40:26 -07:00
Jordan Carlin
b830d20f2d
Modify Fround Tmask to work for X=1
2024-05-25 12:56:02 -07:00
Jordan Carlin
fb77440a64
Update fpctrl fmt to work for fround instructions
2024-05-24 15:33:45 -07:00
Jordan Carlin
ae29a9b861
Update control bits for froundnx
2024-05-24 15:19:20 -07:00
Rose Thompson
dc09e1c0c5
Modified names so they don't conflict with FPGA's axi signals.
2024-05-24 16:38:47 -05:00
Rose Thompson
73261e7f89
More cleanup. Close to the simpliest it can be.
2024-05-24 16:34:33 -05:00
Rose Thompson
bd2ec879d2
Removed unused axi signals from packetizer.
2024-05-24 16:31:27 -05:00
David Harris
a95977590d
AES cleanup
2024-05-24 14:28:30 -07:00
Rose Thompson
263be86119
Packetizer cleanup.
2024-05-24 16:27:09 -05:00
David Harris
b2689b4f01
AES cleanup
2024-05-24 14:13:57 -07:00
Rose Thompson
1f7d732dca
Moved the rvvisynth code to testbench since I only want this for simulation and fpga.
2024-05-24 16:10:58 -05:00
Rose Thompson
d341974c5b
Have rvvi to ethernet working.
...
Now it is time to move the hardware to the FPGA.
Ideally I don't want Wally to actually have any of this code since it's entirely
debug code so it will move to the fpga/src directory.
Then we'll need to add additional logic to the mmcm to generate the correct clocks.
Finally we'll update the I/O to add ethernet.
2024-05-24 15:52:13 -05:00
David Harris
ec5c67a5c1
AES cleanup
2024-05-24 13:48:53 -07:00
Rose Thompson
bf9f45d319
We have a simulation of the ethernet transmission working.
...
This commit does not include the source files for the ethernet as it does not belong to cvw.
I'll want to fork that repo and make it a submodule as I need to change the source a bit.
2024-05-24 11:25:42 -05:00
David Harris
e626052ec9
simplified AES32de mixcolumns because input is only one byte
2024-05-23 22:30:25 -07:00
David Harris
b0d1344121
Commented sha instructions
2024-05-23 22:06:37 -07:00
David Harris
ac153bc4ed
More simplifying sha512_32
2024-05-23 05:46:56 -07:00
David Harris
d9a1691c83
Simplified sha512_32
2024-05-23 05:39:50 -07:00
David Harris
c160ced2d2
Zk* cleanup
2024-05-22 15:01:20 -07:00
David Harris
3ad815ce34
Reordered Zicond support in ALU
2024-05-22 08:29:08 -07:00
Rose Thompson
e5b8fd35b0
Successfully added RVVIStall for back pressure to slow down the pipeline if the ethernet or host computer running imperasDV can't keep up.
2024-05-22 09:56:12 -05:00
David Harris
a17204b0fe
Continued bmu cleanup
2024-05-22 00:48:04 -07:00
David Harris
88eb7bd045
Pulled brev8 out of byteop so redundant byteop logic is not needed in zbkb
2024-05-22 00:22:53 -07:00
Rose Thompson
b116c0c902
Lots of progress on the rvvisynth to ethernet packetizer.
...
Almost producing axi4 commands.
2024-05-21 18:23:42 -05:00
Rose Thompson
d1141237ee
Removed prefix from rvvi hierarchy so it works without testbench.
2024-05-21 16:20:53 -05:00
Rose Thompson
8fd278b322
Fixed some references to rvvi.
2024-05-21 16:15:05 -05:00
Rose Thompson
ea5d780adf
Closer to synthesized rvvi
2024-05-21 12:42:43 -05:00
Rose Thompson
b127c19242
Merge branch 'main' into rvvi
2024-05-20 16:31:06 -05:00
Jordan Carlin
1d8ffee20c
Certain Zcb instructions are dependent on other extensions, not the entire extension
2024-05-15 19:16:43 -07:00
Jordan Carlin
3df5a5abdd
Remove additional bitwise operator
2024-05-15 09:29:54 -07:00
Rose Thompson
e295454948
Merge pull request #798 from jordancarlin/newConfig
...
Update config to derive MISA from macros and update MISA bits based on the spec
2024-05-15 10:28:44 -05:00
Jordan Carlin
291d1e62d5
M implies Zmmul
2024-05-14 19:38:34 -07:00
Jordan Carlin
4a72922087
update config to derive MISA from macros
...
- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
2024-05-14 06:49:18 -07:00
David Harris
175c18da01
Parameterized FMA. However, some offsets are not parameterized. See PR #793 for list of changes
2024-05-13 15:16:00 -07:00
David Harris
2dfada0687
Started parameterizing FMA
2024-05-13 14:01:36 -07:00
David Harris
c2b9e326ca
Fround cleanup
2024-05-13 13:27:29 -07:00
David Harris
e87a269f59
Fix fcvt.lu.s bug and lint issue in packoutput
2024-05-12 11:31:27 -07:00
David Harris
380d88fc68
Merged config-shared after fma fix
2024-05-12 11:10:55 -07:00
David Harris
009d251433
Fixed cvtint bug by adding 2 bits to convert width; initial implementation of fround passes basic regression but fails some nightly regression cases
2024-05-11 22:32:51 -07:00
Katherine Parry
807ef44772
fixed fma testfloat issue #578
2024-05-10 18:12:11 -07:00
Rose Thompson
b027fa44ef
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:53:00 -05:00
Rose Thompson
10b08f8039
Updated brach predictor names to more logical names and match textbook.
2024-05-10 08:51:12 -05:00
David Harris
77137f0f60
ZAAMO and ZALRSC implemented but not tested
2024-05-07 16:45:49 -07:00
David Harris
fcd75fd6b6
Fixed shiftcorrection typo causing failure on testfloat fcvt tests
2024-05-07 14:27:44 -07:00
David Harris
bdc2ad494f
Shared AND gate in ALU for extract / and paths
2024-05-03 09:07:33 -07:00
David Harris
4d5ac3b869
Turned off BMUSubArith for bext/bexti
2024-05-03 08:59:40 -07:00
David Harris
4639e92fda
Turned off BMUSubArith for bext/bexti
2024-05-03 08:56:14 -07:00
David Harris
c0afb44ed4
Tied dangling signals to 0 for some configs to make VCS lint happy
2024-04-28 22:50:36 -07:00
David Harris
7695ad4755
More fround stub code to keep VCS happy
2024-04-28 22:21:51 -07:00
David Harris
06e34b7be4
Fixed byte enables for synthesis
2024-04-27 06:25:24 -07:00
David Harris
1274ec55af
Resolved merge conflict
2024-04-26 16:15:23 -07:00
David Harris
4faf44c4c6
Named zknde block in bitmanipalu
2024-04-25 17:24:00 -07:00
Rose Thompson
6c0b860742
Fixed the cache miss counter.
2024-04-24 16:14:51 -05:00
David Harris
235a3dcfca
ROM preload compatible with Verilator lint, sim, and Design Compiler
2024-04-24 08:44:37 -07:00
David Harris
32b6e6a8ab
fround progress
2024-04-24 04:42:47 -07:00
David Harris
6415bfc3c2
Code and testbench cleanup
2024-04-23 10:17:44 -07:00
David Harris
cc236bdb25
Resolved merge conflicts
2024-04-22 12:16:06 -07:00
David Harris
03f49dea3f
regression printing improvements
2024-04-21 19:45:09 -07:00
David Harris
3f195884e9
Defined bit sizes more precisely to help VCS lint and conform to coding style
2024-04-21 08:40:11 -07:00
David Harris
be15a11622
Fixed conflicts on getenv
2024-04-21 08:38:13 -07:00
David Harris
0419b5484a
parameterized register names in peripherals
2024-04-21 07:43:01 -07:00
David Harris
00a1c0fc57
Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors
2024-04-21 00:02:15 -07:00
David Harris
fd6a6b2249
environment variable cleanup
2024-04-20 22:52:08 -07:00
David Harris
f39e240082
Spacing cleanup
2024-04-20 20:53:49 -07:00
David Harris
25a26656b6
Removed unnecessary ZBB from BMU extract mux
2024-04-20 20:53:14 -07:00
David Harris
338f37b570
Moved getenv/getenvval declaration to config-shared so lint and regression both run
2024-04-20 17:19:42 -07:00
David Harris
571b67f565
Merging PR738
2024-04-20 17:15:17 -07:00
slmnemo
f0229e970b
Fixed getenvvar verilator bug in rom1p1r, Removed unused system function from testbench.
2024-04-20 17:07:54 -07:00
David Harris
ea344fe2fa
Fixed getenvval lint error in rom1p1r
2024-04-20 15:55:52 -07:00
David Harris
a3db61b2b2
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-04-20 15:41:42 -07:00
David Harris
9ec4c752f1
Fixed bugs in Zcb compressed loads and stores
2024-04-20 13:16:31 -07:00
Kunlin Han
08dd2eac74
Add getenvval for rom. Related to issue #723 .
2024-04-17 23:26:09 -07:00
David Harris
3ea16c6057
Removed note about store stall being depricated
2024-04-17 03:34:11 -07:00
David Harris
db330b35b2
Removed unnecessary muxes from shiftcorrection; changed flag to --nightly in lint-wally
2024-04-16 20:57:49 -07:00
slmnemo
39ae26a897
Added documentation for known Verilator hierarchy bug
2024-04-15 15:58:09 -07:00
slmnemo
4b80457f3e
Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory
2024-04-12 21:58:20 -07:00
David Harris
499e4d6a6e
Changed 2 to 1 in FmaPreResultSubnorm logic, fixing issue 655 about multiply on f/fh. Not entirely confident this is the right change, but can't find any failures. See https://docs.google.com/document/d/1p7zb4Vvd1LMBLRgEpXjHyp7etCaFaiBVrBZJM8jediE/edit
2024-04-03 17:28:31 -07:00
David Harris
79cccfca82
Progress toward run_vcs
2024-04-03 14:05:07 -07:00
Rose Thompson
4eb522123f
Changed D suffix to Delay in ebufsmarb.
2024-03-28 16:24:45 -05:00
Rose Thompson
5b4d3f49b0
Fixed #689 caused by removal of #1 delays. For some reason the #1 were not removed from cacheLRU.sv.
2024-03-26 12:26:03 -05:00
David Harris
fc158689ad
Shared amoalu max/min comparator hardware and removed input sign extend muxes
2024-03-24 17:15:46 -07:00
David Harris
f0b29d3083
AMO max/min comparator optimization
2024-03-24 17:05:32 -07:00
David Harris
bae52cf13d
Merge pull request #678 from Karl-Han/latest
...
[Resolved Conflict] Remove all #delay from non-testbench
2024-03-23 15:18:04 -07:00
Kunlin Han
22b59138f0
Remove all #delay from non-testbench.
2024-03-16 11:20:32 -07:00
David Harris
35f1c1d971
Restructured rconlut for modularity
2024-03-16 07:26:40 -07:00
David Harris
fedd23a3c0
Renamed aes blocks based on size
2024-03-16 07:12:36 -07:00
David Harris
c01e4495b1
AES simplification
2024-03-16 07:00:56 -07:00
Jordan Carlin
cbd61d008f
fix size of CVTLEN to support fcvtmod.w.d; add max macro to config-shared.vh
2024-03-14 14:07:15 -07:00
Kunlin Han
8c67a76912
Remove all #delay from non-testbench.
2024-03-13 10:31:40 -07:00
James Stine
41ab94c9a3
fix elements forgot to delete from zknh32.sv
2024-03-12 11:42:26 -05:00
James Stine
55863bda1b
Update K extension in SHA to remove redundant logic and optimize hierarchy to reduce structure/area
2024-03-12 11:10:45 -05:00
David Harris
7132d306b4
Simplified ZKNH64
2024-03-11 09:41:36 -07:00
David Harris
dbfe44a54b
Renamed aes and sha directories
2024-03-11 09:06:51 -07:00
David Harris
019458a63d
Shared sbox between aes64ks1i and aes64e
2024-03-11 08:58:10 -07:00
David Harris
096f4090ac
Final cleanup tonight
2024-03-11 01:40:47 -07:00
David Harris
8af25a45e6
AES32 sharing logic
2024-03-11 01:36:46 -07:00
David Harris
a714904696
Simplifying AES32 logic
2024-03-11 01:25:44 -07:00
David Harris
10d1ff61b6
Merged ZKNDEResult into a single BMU result mux input
2024-03-11 01:18:39 -07:00
David Harris
39c0d0cdda
AES64 simplification
2024-03-11 01:15:16 -07:00
David Harris
b7f5ce6ed3
AES64 simplification
2024-03-11 01:12:24 -07:00
David Harris
64d7f778da
AES64 simplification
2024-03-11 01:01:20 -07:00
David Harris
7d87c4f6c5
AES64 simplification
2024-03-11 00:53:39 -07:00
David Harris
87ed778763
Starting to merge decrypt and encrypt for AES64
2024-03-11 00:45:38 -07:00
David Harris
ef896797fd
Optimized out aes64im hardware; sharing with aes64d
2024-03-11 00:36:10 -07:00
David Harris
5257d3d8fd
AES64 cleanup
2024-03-11 00:20:50 -07:00
David Harris
7ee3145fc1
Simplified muxing for AES64
2024-03-11 00:14:38 -07:00
David Harris
d22306ab9f
Shared haredware for aes64e
2024-03-11 00:01:46 -07:00
David Harris
b53e873a11
shared hardware for AES 64 decode
2024-03-10 23:51:32 -07:00
David Harris
f950067600
Shared middle and final round aes32 to cut size 50%
2024-03-10 23:40:12 -07:00
David Harris
f72e5048de
Defined rotate module and formatted AES modules more densely
2024-03-10 23:09:11 -07:00
David Harris
3d72ccac60
AES simplification
2024-03-10 22:37:50 -07:00
David Harris
9a1fdba077
Added more Zbkb tests shared with Zbb
2024-03-10 22:24:16 -07:00
David Harris
2580d37fc0
ZK cleanup, check no LLEN > XLEN without D$, add half and quad float load/store to instruction name decoder
2024-03-10 22:03:57 -07:00
David Harris
837abf1d9e
ZK simplifcations
2024-03-10 21:44:11 -07:00
David Harris
d0dd30822e
ZK simplification
2024-03-10 21:35:20 -07:00
David Harris
955c131bd9
Crypto rename inputs and outputs to a and y
2024-03-10 21:27:11 -07:00
David Harris
ea6846ffcc
Crypto commenting cleanup
2024-03-10 20:58:57 -07:00
David Harris
e4724b8d0e
Crypto formatting cleanup
2024-03-10 20:45:27 -07:00
David Harris
34058ddbf0
Crypto formatting cleanup
2024-03-10 20:36:29 -07:00
David Harris
39ca7093bf
Merged AES changes
2024-03-10 19:17:01 -07:00
Rose Thompson
3cf6a19729
Merge branch 'main' into main
2024-03-10 10:48:21 -05:00
James E. Stine
047291ef49
add header for bmuctrl.sv
2024-03-09 22:09:31 -06:00
James E. Stine
54fec7c31f
fix bitmanipalu.sv typo on missing semicolon
2024-03-09 22:07:40 -06:00
James E. Stine
1573c890d0
Update bitmanipalu.sv for K extension
2024-03-09 22:01:20 -06:00
James E. Stine
ac3aa823e7
fix underscore in bmu directory
2024-03-09 20:19:46 -06:00
James E. Stine
1aa1608a18
fix space in kmu
2024-03-09 19:41:29 -06:00
James E. Stine
ad12def935
fix underscore in instantiation
2024-03-09 19:38:10 -06:00
James E. Stine
bd5741b4f1
fix space at beginning of file in bmu
2024-03-09 19:10:43 -06:00
James E. Stine
55e019c9dd
update removal of underscores from kmu
2024-03-09 19:00:31 -06:00
James E. Stine
3b16238a37
update removal of underscores from sha_instructions
2024-03-09 18:51:01 -06:00
James E. Stine
08c7ddd61d
update removal of underscores from aes_instructions
2024-03-09 13:28:47 -06:00
James E. Stine
8821386fe5
update removal of underscores from aes_common
2024-03-09 13:06:36 -06:00
Rose Thompson
29db2cd931
Basic hardware tracer works!
...
Next step is to package the buses into packets to ethernet transmission.
2024-03-08 12:38:27 -06:00
Rose Thompson
140e64772e
Merge branch 'main' into rvvi
2024-03-08 10:16:31 -06:00
David Harris
eb87a4a5c3
UM comments in fdivsqrtotfc
2024-03-06 15:53:14 -08:00
David Harris
2c6588d4ae
Timinig optimization for radix 4 division, added missing derived config
2024-03-06 15:05:04 -08:00
David Harris
c7c12cc3a8
Fixed Lint issue on cacheLRU
2024-03-06 14:00:57 -08:00
Rose Thompson
54c1d28c8b
Fixed missing case in the align AccesByteOffset Mux.
2024-03-06 15:43:55 -06:00
Rose Thompson
0d8c251fa4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-03-06 15:35:34 -06:00
Rose Thompson
2f94be5e79
Revert "Optimized the align logic for loads."
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This reverts commit 1fd678b433
2024-03-06 15:19:17 -06:00
Rose Thompson
57aab52dc2
Revert "Partially working optimized subwordwrite for misaligned."
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This reverts commit dac8fc16af
2024-03-06 15:17:57 -06:00
Rose Thompson
9668fdd868
Revert "Closer to getting subword write misaligned working."
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This reverts commit 6a9c2d8dc4
2024-03-06 15:16:43 -06:00
Rose Thompson
dce7de59a3
Revert "Non-ideal fix. Added new output from pma which indicates if the write shift should occur."
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This reverts commit 3714b2bf4a
2024-03-06 15:16:37 -06:00
Rose Thompson
a48c16c0ef
Revert "Swapped to the more compact subwordreadmisaligned.sv."
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This reverts commit 1ece6f8eae
2024-03-06 15:16:32 -06:00
Rose Thompson
f752b5dd37
Revert "Beginning subword cleanup."
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This reverts commit 7e1ea1e6d9
2024-03-06 15:16:24 -06:00
Rose Thompson
a8024eee26
Revert "Updated subword misaligned."
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This reverts commit 69d31d50e2
2024-03-06 15:16:16 -06:00
Rose Thompson
298028b119
Revert "Cleanup."
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This reverts commit 45c30267a5
2024-03-06 15:16:03 -06:00
Rose Thompson
739e73ef81
Revert "Siginficant cleanup of subwordwritemisaligned."
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This reverts commit fbc18abaa0
2024-03-06 15:15:58 -06:00
Rose Thompson
e7ec2bedd4
Revert "Simplifications of subword code."
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This reverts commit a402883115
2024-03-06 15:15:51 -06:00
Rose Thompson
b64b883129
Revert "Removed duplicate endianswap."
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This reverts commit caac48b7f2
2024-03-06 15:15:43 -06:00
Rose Thompson
5447159cfd
Revert "Cleanup."
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This reverts commit e84b7cc147
2024-03-06 15:15:26 -06:00
Rose Thompson
3fa5faa6cf
Revert "Added sdc to pma allow shift."
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This reverts commit a2d5618d88
2024-03-06 13:29:08 -06:00
Rose Thompson
2ea0134329
Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned."
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This reverts commit cba3209e7f
2024-03-06 13:28:59 -06:00
Rose Thompson
068ffda5fb
Revert "Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned.""
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This reverts commit 8136b45ca7
2024-03-06 13:28:47 -06:00
David Harris
e0eb91f795
Changed always @(posedge clk) to always_ff @(posedge clk) where it was omitted in several places
2024-03-06 11:02:04 -08:00
David Harris
b386331cc8
Changed '0 to 0 where possible per Chapter 4 style guidelines
2024-03-06 05:48:17 -08:00
David Harris
dd33479056
Switched to ?: for gating per section 4.2.4.3
2024-03-06 04:59:58 -08:00
David Harris
86956026dc
Further simplified subwordread muxing
2024-03-06 04:24:31 -08:00
Kevin Kim
9d73e5bd0d
lsu supports quad enabled subwordreads
2024-03-05 17:07:39 -08:00
KelvinTr
00b61390d9
Optimized Inverse Mixcolumn
2024-03-05 14:56:24 -06:00
Rose Thompson
c093f53c9c
Merge branch 'main' of https://github.com/openhwgroup/cvw
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Cleaned up the cacheLRU.
2024-03-05 11:08:40 -06:00
Rose Thompson
e8e0538f6c
Changed to non-blocking in cacheLRU and removed clearing LRU bits on flush.
2024-03-05 10:33:47 -06:00
James E. Stine
5b445946b1
style file slight mods for sha_instructions
2024-03-05 09:14:22 -06:00
James E. Stine
6894ee4588
Separate gm2.sv to be separate module
2024-03-05 09:10:41 -06:00
James E. Stine
5aab40a35f
Missed some style module declarations
2024-03-05 09:06:48 -06:00
James E. Stine
5e247b9bf3
fix some spacing in aes_common
2024-03-05 09:02:22 -06:00
James E. Stine
7bbc6413fb
fix spacing in sha_instructions for style
2024-03-05 08:59:45 -06:00
James E. Stine
0d7ea36883
fix module name to lc in aes_instructions
2024-03-05 08:56:24 -06:00
James E. Stine
e6ffde61bd
fix module name to lc
2024-03-05 08:54:50 -06:00
David Harris
1a0097f6e7
Further fdivsqrt simplification after starting Sqrt at iteration 0
2024-03-04 16:40:49 -08:00
David Harris
9c04df8f69
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-03-04 16:04:24 -08:00
Rose Thompson
457d3481e7
How did this error get past for so long.
2024-03-04 17:58:41 -06:00
Rose Thompson
0222e8f42a
Don't want to clear the lru bits on invalidation (clearvalid).
2024-03-04 17:52:41 -06:00
Kevin Kim
10ab07975f
uslc comments
2024-03-04 14:31:21 -08:00
Kevin Kim
9b87a00698
sqrt mux lint fixes
2024-03-04 14:31:07 -08:00
Kevin Kim
587fdbdf8e
removed j1,j0 from iteration and put inside divider stage
2024-03-04 14:30:05 -08:00
KelvinTr
c163069484
Optimized mixcolumn
2024-03-04 15:23:11 -06:00
Kevin Kim
7dec9cdf21
optimization in uslc
2024-03-04 10:46:16 -08:00
Kevin Kim
9c95cba865
remove sqrt cycle muxing
2024-03-03 18:51:10 -08:00
Kevin Kim
0ff59ff157
remove redundant mux
2024-03-03 13:00:20 -08:00
Kevin Kim
c32173f163
changed U/C initialization to account for integer bit generation on divider stage for sqrt. Quick and dirty j1 logic fix
2024-03-03 10:30:18 -08:00
Kevin Kim
6c24afaf98
changed cycle count to account for integer bit generation for sqrt
2024-03-03 10:29:32 -08:00
Kevin Kim
c45d67f8ba
fdivsqrt changes
2024-03-02 20:29:03 -08:00
Kevin Kim
77ccc7b319
removed square root pre-process muxes
2024-03-02 15:55:34 -08:00
Rose Thompson
a22de45631
Removed unused storedelay from align.
2024-03-02 16:20:31 -06:00
Rose Thompson
8136b45ca7
Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned."
...
This reverts commit cba3209e7f
2024-03-02 11:55:43 -06:00
Rose Thompson
cba3209e7f
Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned.
2024-03-02 11:38:33 -06:00
Rose Thompson
4c3d927474
Renamed CacheHit to Hit.
2024-03-01 11:00:24 -06:00
Rose Thompson
e72880fd89
Changed cachefsm state STATE_HIT to STATE_ACCESS.
2024-03-01 09:59:54 -06:00
Rose Thompson
85691f0e8b
Simplified and clarified names in cacheLRU.
2024-02-29 17:18:01 -06:00
KelvinTr
c110d0bb03
Optimized Zbkx
2024-02-29 14:51:02 -06:00
KelvinTr
9f53c54f57
Optimized Zbkx
2024-02-29 14:50:15 -06:00
KelvinTr
e40ae126d3
Combined ZBC and ZBKC into one unit
2024-02-29 14:17:33 -06:00
KelvinTr
88d93b31b5
Combined byteop and revop logic
2024-02-29 12:51:42 -06:00
Rose Thompson
90ad5e7dab
Updated the cache for book clarity.
2024-02-28 17:07:32 -06:00
KelvinTr
01c45ab9d7
Fixed K extension changes
2024-02-28 17:05:08 -06:00
David Harris
90e89ced1d
Fixes for synthesis. HPTW change will break x detection
2024-02-26 04:20:08 -08:00
James E. Stine
eb1780a66d
control for bitmanip
2024-02-24 22:38:21 -06:00
James E. Stine
ce975a6336
Add ieu main module for k extension
2024-02-24 22:37:04 -06:00
James E. Stine
71cefdbbb2
main cvw module
2024-02-24 22:35:56 -06:00
James E. Stine
cd2a9b8712
Add mux7 for K ext
2024-02-24 22:26:21 -06:00
James E. Stine
50cbe54d7b
Add datapath.sv
2024-02-24 22:22:19 -06:00
James E. Stine
e06bafe972
Add alu + controller
2024-02-24 22:21:39 -06:00
Rose Thompson
ab750e150f
Fixed lint errors for alignment.
2024-02-23 14:00:19 -06:00
Rose Thompson
a2d5618d88
Added sdc to pma allow shift.
2024-02-23 13:46:04 -06:00
Rose Thompson
e84b7cc147
Cleanup.
2024-02-23 13:00:21 -06:00
Rose Thompson
ae36f1e5a5
Merge branch 'main' of github.com:ross144/cvw
2024-02-23 09:43:03 -06:00
Rose Thompson
caac48b7f2
Removed duplicate endianswap.
2024-02-23 09:42:39 -06:00
Rose Thompson
a402883115
Simplifications of subword code.
2024-02-23 09:41:59 -06:00
Rose Thompson
fbc18abaa0
Siginficant cleanup of subwordwritemisaligned.
2024-02-22 14:17:15 -06:00
Rose Thompson
45c30267a5
Cleanup.
2024-02-22 14:08:04 -06:00
Rose Thompson
69d31d50e2
Updated subword misaligned.
2024-02-22 13:29:39 -06:00
James E. Stine
cdd2aa6379
tweak of names
2024-02-22 12:27:40 -06:00
James E. Stine
c8468e99c0
slight tweak of names
2024-02-22 12:27:09 -06:00
James E. Stine
550f50debb
Modify ALU to handle Zkne/K extension
2024-02-22 11:55:00 -06:00
Rose Thompson
7e1ea1e6d9
Beginning subword cleanup.
2024-02-22 09:37:16 -06:00
Rose Thompson
1ece6f8eae
Swapped to the more compact subwordreadmisaligned.sv.
2024-02-22 09:34:16 -06:00
Rose Thompson
3714b2bf4a
Non-ideal fix. Added new output from pma which indicates if the write shift should occur.
...
The more ideal solution would be to have the pma indicate if the shift should occur and the maximum amount..
2024-02-22 09:14:43 -06:00
James E. Stine
7cb170c19b
update on aes_instructions
2024-02-21 17:12:50 -06:00
James E. Stine
7097b17785
update aes_instructions
2024-02-21 17:11:34 -06:00
James E. Stine
ac9068d22c
update aes_common with style on separate sv
2024-02-21 17:05:58 -06:00
James E. Stine
3d65ea7aba
separate aes_shiftword per style file
2024-02-20 22:57:59 -06:00
James E. Stine
f700b7da5a
separate galois function SV per the style file
2024-02-20 22:55:34 -06:00
Rose Thompson
6a9c2d8dc4
Closer to getting subword write misaligned working.
2024-02-20 20:23:42 -06:00
James E. Stine
32be22565a
add kmu instruction
2024-02-20 20:18:50 -06:00
James E. Stine
38348f9784
Add SHA instructions
2024-02-20 20:01:12 -06:00
James E. Stine
2cf1d43ec5
add aes instructions
2024-02-20 19:39:26 -06:00
James E. Stine
93d9bb4bc4
minor changes + date change on copyright
2024-02-20 19:13:11 -06:00
James E. Stine
488583aed9
minor tweak
2024-02-20 18:42:34 -06:00
James E. Stine
0cc0cdeae2
initial seed of AES engine
2024-02-20 18:31:17 -06:00
David Harris
c77afcb7e6
Removed floprc with synchronous reset and synchornous clear
2024-02-19 22:28:55 -08:00
Rose Thompson
dac8fc16af
Partially working optimized subwordwrite for misaligned.
2024-02-19 12:26:29 -06:00
David Harris
9ba35991e3
Finished FPU coverage
2024-02-15 20:01:28 -08:00
David Harris
36259b4e16
Removed unused term affecting cvt coverage
2024-02-15 17:46:05 -08:00
David Harris
944e33dcd6
Fixed spelling of operation in FPU
2024-02-15 17:22:32 -08:00
David Harris
c664c9717d
Commented fcvtmod behavior in specialcase
2024-02-15 17:19:21 -08:00
Rose Thompson
1fd678b433
Optimized the align logic for loads.
2024-02-14 12:14:19 -06:00
David Harris
6f53adad80
ifu cachefsm coverage
2024-02-08 13:15:06 -08:00
Kevin Kim
15da037794
added back comment
2024-02-07 15:40:52 -08:00
Kevin Kim
61c8b4d269
shift correction fix
2024-02-07 15:04:19 -08:00
David Harris
e7364290e3
Restored instead of in testbench because prevents coverage analysis. Improved FPU coverage
2024-02-07 06:27:53 -08:00
David Harris
c41e1c3a1c
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-02-04 19:02:49 -08:00
David Harris
66c1c71a56
Coverage improvements
2024-02-04 18:56:40 -08:00
Rose Thompson
7a4d485f5b
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-02-04 14:19:50 -06:00
David Harris
5d8d82414b
Coverage improvements
2024-02-04 11:40:38 -08:00
harshinisrinath
c7b647bde7
Wrote exclusions for ifu and lsu peripherals which were always supported
2024-02-01 17:12:33 -08:00
Rose Thompson
bd06a5ff88
Rough draft removal of duplicate BPBTAWrongE logic.
2024-02-01 16:57:33 -06:00
Rose Thompson
e900bb09db
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-02-01 12:12:05 -06:00
Rose Thompson
87d91c5b14
Coverage updates.
2024-02-01 12:12:01 -06:00
David Harris
1c62c5e433
Fixed logic to work with FLEN < XLEN
2024-01-31 20:24:16 -08:00
