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https://github.com/openhwgroup/cvw
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Missed some style module declarations
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@ -25,8 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aes_inv_sbox(input logic [7:0] in,
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output logic [7:0] out);
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module aes_inv_sbox(input logic [7:0] in, output logic [7:0] out);
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always_comb
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begin
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@ -25,8 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aes_inv_sbox_word(input logic [31:0] in,
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output logic [31:0] out);
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module aes_inv_sbox_word(input logic [31:0] in, output logic [31:0] out);
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// Declare the SBOX for (least significant) byte 0 of the input
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aes_inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0]));
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@ -25,8 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aes_inv_shiftrow(input logic [127:0] DataIn,
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output logic [127:0] DataOut);
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module aes_inv_shiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut);
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assign DataOut = {DataIn[31:24], DataIn[55:48], DataIn[79:72], DataIn[103:96],
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DataIn[127:120], DataIn[23:16], DataIn[47:40], DataIn[71:64],
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@ -26,8 +26,7 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aes_mixcolumns(input logic [31:0] in,
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output logic [31:0] out);
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module aes_mixcolumns(input logic [31:0] in, output logic [31:0] out);
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logic [7:0] in0, in1, in2, in3, out0, out1, out2, out3, t0, t1, t2, t3, temp;
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logic [15:0] rrot8_1, rrot8_2;
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@ -25,8 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aes_sbox(input logic [7:0] in,
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output logic [7:0] out);
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module aes_sbox(input logic [7:0] in, output logic [7:0] out);
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// case statement to lookup the value in the rijndael table
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always_comb
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@ -25,8 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aes_sbox_word(input logic [31:0] in,
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output logic [31:0] out);
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module aes_sbox_word(input logic [31:0] in, output logic [31:0] out);
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// Declare the SBOX for (least significant) byte 0 of the input
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aes_sbox sbox_b0(.in(in[7:0]), .out(out[7:0]));
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@ -25,9 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aes_shiftrow
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(input logic [127:0] DataIn,
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output logic [127:0] DataOut);
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module aes_shiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut);
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assign DataOut = {DataIn[95:88], DataIn[55:48], DataIn[15:8], DataIn[103:96],
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DataIn[63:56], DataIn[23:16], DataIn[111:104], DataIn[71:64],
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@ -25,9 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module galoismult_forward (
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input logic [7:0] in,
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output logic [7:0] out);
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module galoismult_forward(input logic [7:0] in, output logic [7:0] out);
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logic [7:0] leftshift;
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@ -44,4 +42,4 @@ module gm2 (gm2_In, gm2_Out);
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// Set output to Galois Mult 2
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assign gm2_Out = {gm2_In[6:0], 1'b0} ^ (8'h1b & {8{gm2_In[7]}});
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endmodule
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endmodule
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