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Cleanup.

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This commit is contained in:
Rose Thompson 2024-02-23 13:00:21 -06:00
parent ae36f1e5a5
commit e84b7cc147
3 changed files with 3 additions and 19 deletions
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14
src/lsu/align.sv
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@ -47,7 +47,6 @@ module align import cvw::*; #(parameter cvw_t P) (
input logic [P.LLEN-1:0] LSUWriteDataM,
output logic [(P.LLEN*2-1)/8:0] ByteMaskSpillM,
output logic [P.LLEN*2-1:0] LSUWriteDataSpillM,
output logic [P.XLEN-1:0] IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill
output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill
@ -71,7 +70,6 @@ module align import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] IEUAdrIncrementM;
logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM;
logic [$clog2(LLENINBYTES)+2:0] ShiftAmount;
logic PotentialSpillM;
/* verilator lint_off WIDTHEXPAND */
@ -142,18 +140,6 @@ module align import cvw::*; #(parameter cvw_t P) (
// merge together
mux2 #(2*P.LLEN) postspillmux(DCacheReadDataWordM, {DCacheReadDataWordM[P.LLEN-1:0], ReadDataWordFirstHalfM}, SelSpillM, ReadDataWordSpillAllM);
// shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit)
// 8 * is for shifting by bytes not bits
assign ShiftAmount = SelHPTW ? '0 : {AccessByteOffsetM, 3'b0}; // AND gate
// write path. Also has the 8:1 shifter muxing for the byteoffset
// then it also has the mux to select when a spill occurs
logic [P.LLEN*3-1:0] LSUWriteDataShiftedExtM; // *** RT: Find a better way. I've extending in both directions so we don't shift in zeros. The cache expects the writedata to not have any zero data, but instead replicated data.
assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << ShiftAmount;
assign LSUWriteDataSpillM = LSUWriteDataShiftedExtM[P.LLEN*3-1:P.LLEN];
mux3 #(2*P.LLEN/8) bytemaskspillmux({ByteMaskExtendedM, ByteMaskM}, // no spill
{{{P.LLEN/8}{1'b0}}, ByteMaskM}, // spill, first half
{{{P.LLEN/8}{1'b0}}, ByteMaskExtendedM}, // spill, second half

4
src/lsu/endianswap.sv
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@ -54,8 +54,8 @@ module endianswap #(parameter LEN) (
y[143:136] = a[119:112];
y[135:128] = a[127:120];
y[127:120] = a[135:128];
y[119:112] = a[142:136];
y[111:104] = a[152:144];
y[119:112] = a[143:136];
y[111:104] = a[151:144];
y[103:96] = a[159:152];
y[95:88] = a[167:160];
y[87:80] = a[175:168];

4
src/lsu/lsu.sv
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@ -126,7 +126,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic [P.LLEN-1:0] DTIMReadDataWordM; // DTIM read data
/* verilator lint_off WIDTHEXPAND */
logic [MLEN-1:0] DCacheReadDataWordM; // D$ read data
logic [MLEN-1:0] LSUWriteDataSpillM; // Final write data
logic [MLEN/8-1:0] ByteMaskSpillM; // Selects which bytes within a word to write
/* verilator lint_on WIDTHEXPAND */
logic [MLEN-1:0] ReadDataWordMuxM; // DTIM or D$ read data
@ -168,7 +167,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M,
.MemRWM,
.DCacheReadDataWordM, .CacheBusHPWTStall, .SelHPTW,
.ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM(LSUWriteDataM[P.LLEN-1:0]), .ByteMaskSpillM, .LSUWriteDataSpillM,
.ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM(LSUWriteDataM[P.LLEN-1:0]), .ByteMaskSpillM,
.IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .ReadDataWordSpillAllM, .SpillStallM,
.SelStoreDelay);
assign IEUAdrExtM = {2'b00, IEUAdrSpillM};
@ -179,7 +178,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
assign SelSpillE = '0;
assign ReadDataWordSpillAllM = DCacheReadDataWordM;
assign ByteMaskSpillM = ByteMaskM;
assign LSUWriteDataSpillM = LSUWriteDataM;
assign MemRWSpillM = MemRWM;
assign {SpillStallM, SelStoreDelay} = '0;
end